Gsa Dac 2011 3dic Guide

3D-IC DESIGN TOOLS & SERVICES TOUR GUIDE
DAC 2011
3 D-IC DESIGN TOOLS & SERVICES TOUR GUIDE: DAC 2 0 1 1
Table of Contents
Introduction .................................................................................................................... 3 Market Research 3D-Incites ............................................................................................................. 12 TechSearch International, Inc. ................................................................................. 13 Yole Developpement ............................................................................................... 15 EDA Vendors Apache (Booth #2448) ........................................................................................... 18 Atrenta (Booth #1643) ........................................................................................... 20 CAD Design Software .............................................................................................. 23 Cadence (Booth # 2237) ......................................................................................... 26 Coventor (Booth #1719) ......................................................................................... 30 DOCEA Power (Booth #1912) .................................................................................. 31 E-System Design, Inc. (Booth #3121) ...................................................................... 33 Gradient (Booth #3249) .......................................................................................... 36 Magma Design Automation (Booth #1743) ................................................................ 37 Mentor Graphics Verification (Booth #1542) .............................................................. 39 Mentor Graphics Test (Booth #1542) ........................................................................ 40 Micro Magic (Booth #2917) ..................................................................................... 41 R3Logic (Booth #1607) ........................................................................................... 42 Sigrity (Booth #2525) ............................................................................................ 44 Synopsys (Booth #3433) ........................................................................................ 47 R&D Centers & Industry Organizations CEA-LETI .............................................................................................................. 49 SEMATECH ............................................................................................................ 53 SEMI .................................................................................................................... 54 Si2 (Booth #1631) ................................................................................................. 56 Value-Chain Producer eSilicon ................................................................................................................. 58 About GSA ..................................................................................................................... 62
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Introduction
INTRODUCTION At DAC 2008, GSA started the EDA Interest Group with approximately one dozen founding members, representing EDA firms, foundries and design services and the goal to look for opportunities to grow industry revenues and profits. Within a few months it became clear that 3D/TSV technology was developing as a very significant opportunity to expand the role of EDA by contributing with 3D planning, implementation and verification tools to the growth of our semiconductor ecosystem. Over the last three years, the Interest Group spun off the 3D-IC Working Group and has met bi-monthly to discuss the progress of this technology with invited 3D experts. Sub-working groups have also been formed to analyze where/how EDA expertise can contribute to accelerate 3D market acceptance, including revenue and profit growth. Every 3D-IC Working Group meeting typically attracts 30 to 50 participants from Silicon Valley companies, plus an equal number participating via teleconference from companies around the world. In addition, the group has formed strong working relationships with other industry organizations, such as Fraunhofer Institutes, IMEC, ITRI, Leti, SEMI, Si2, the recently formed 3D Enablement Center (comprised of SEMATECH, SIA and SRC) and other industry organizations. The group has also been communicating with major foundries, OSATs and manufacturing- and test equipment vendors to learn how best to cooperate to achieve cost-competitive 3D solutions. To attend an upcoming meeting, please contact Herb Reiter at herb@eda2asic.com or Chelsea Boone at cboone@gsaglobal.org. To download a softcopy of this 3D-IC Tour Guide or review the presentations 3D experts gave at recent meetings, visit GSAs Website: http://www.gsaglobal.org/eda/index_wg.aspx?tab=3 This second edition of the Tour Guide to 3D-IC Design Tools & Services is a compilation of inputs from EDA, R&D, market research and services companies that have committed significant resources to developing 3D technology and/or to accelerating market acceptance of this important paradigm shift. GSA would like to thank all contributors to the latest 3D-IC Tour Guide and invites the readers to visit the exhibiting companies at DAC, learn more about their capabilities and plans, voice 3D requirements and call/email the ones not represented at DAC. WHAT A DIFFERENCE A YEAR MAKES When soliciting inputs for last years inaugural 3D-IC Tour Guide the following questions were repeatedly asked: Where are the customers for this new technology? I can see the technical benefits of 3D, but will my customers see them? Will they buy my 3D tools and services? Why should semiconductor vendors replace the production-proven PoP (Package-on-Package) or SiP (System-in-Package, wire-bonded) designs with a new, currently unproven technology? Since DAC 2010, 3D has earned many technical and business experts attention, and there has been a shift in the types of questions asked: Is 2.5D an intermediate step toward 3D or an alternative? Do you see the first 3D designs going into production early or late 2012? Are users combining logic and memory or something else in their first designs? Whats important to consider in my 3D business plan? How do I convince my boss to take this rapidly emerging technology seriously? As 2D SoC NREs and tooling costs continue to rise, many business minds look for alternatives. Likewise, IC designers are concerned about the technical challenges 22nm, 16nm or smaller minimum feature sizes will

confront them with in the near future. Both camps are looking for less risky alternatives with lower up-front costs for lower- and medium-volume applications. Only for very high volume runners, 2D SoC remains the front runner as stand-alone IC and/or as part of a 2.5D or 3D configuration. Fig. 1, presented by Rambus at a recent GSA conference, clearly depicts how Gartner Research sees design costs growing with shrinking feature sizes and shows the number of design starts decreasing.
Fig 1. Design Costs Grow as Feature Sizes Shrink; Design Starts Decrease
ALTERNATIVES FOR IMPLEMENTING A NEXT-GENERATION DESIGN Until recently, a decision on how to implement a companys next design was simple: Continue following Moores Law and choose the next-generation process technology offered by the companys fab. As smaller feature-size transistors start demanding new and costly materials and lithography challenges complicate IC design and mask-making and wafer manufacturing, the technology and implementation selection gets much more complex. Achieving lower cost and power dissipation, higher performance, and other features the demanding customer base requires, is no longer an issue for following Moores Law in every situation. But please dont misunderstand! 3D technology will not replace 2D SoCs in all cases, but 2.5D and 3D-ICs will offer technical and cost advantages for some applications now, more medium- and longer term. However, if you want to start a 3D design project and do not have the benefits of a large IDM with all the required design- and manufacturing expertise in-house, a company will need to collaborate with several partners, from the planning stage of the design all the way to ramping up volume production. Choosing all the right partners is still a challenging and time-consuming effort at this point. GSA contributes to building this 3D

ecosystem. Potential 3D-IC partners are represented in the 3D Tour Guide and outline on a few pages each, where and how they can contribute to your 3D project(s). In addition to information included in the 3D Tour Guide, resources such as DAC tutorials, a 3D Panel on Monday, June 6 (http://sitedevelopment.dac.com/exhibits+pavilion+panels.aspx?event=69&topic=7) and attendees individual discussions at DAC 2011 will give you a head start in the search for the right partner(s) to work on your 3D-IC planning-, implementation- and verification steps. If the applications targeted do not impose very tight space constraints or very strict power limits and/or performance requirements, an interposer-based 2.5D solution as a first step, or even as a long-term alternative, may want to be considered. Compared to multiple 2D SoCs on a PC board, a 2.5D design will also reduce power dissipation, while increasing speed significantly. A number of companies introduced 2.5D designs last year and have ramped up production in 2010 or earlier in 2011. The first 3D volume production runs, with Logic + Memory, are expected to start in 2012. In Table 1, several criteria are applied to compare major design alternatives:
The 2D SoC column on the left shows that in addition to the increasing NREs and design risks, SoCs are not well suited for implementing heterogeneous designs, e.g., implementing analog, memory, RF, etc., cost-effectively in the same process technology. The PoP column shows this proven and widely used alternative cannot help in fighting todays biggest design challenge reducing power dissipation. Also, for mobile applications the height of these configurations makes them difficult, if not impossible, to use. The SiP column shows that wire-bonded, stacked die in a package are, like the two previous alternatives, also production proven. SiPs offer lower package height than PoPs, but do not address power dissipation, latency or bandwidth challenges many designs face today. Every die still needs the large and power-hungry I/O buffers to drive the bonding wires and the big I/O buffers at the receiving die. The 2.5D column highlights: This technology can reduce power dissipation, compared to the alternatives in the three columns to the left. Unlike these, 2.5D doesnt require the big and powerhungry I/O buffers, saving area and cost. It also reduces power, improves latency and bandwidth significantly. Die can be arranged, like flip-chips, face-down on the interposer, with relatively short and high-density interconnects between them or, if only two die are needed, face-to-face with an interposer in-between, with TSVs for power routing and signal lines. Several companies have already introduced 2.5D designs. Fig. 2 shows the combination of four FPGAs Xilinx introduced in Fall 2010. This link refers to more info about this 2.5D design: http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Tech nology.pdf The 3D column refers to stacking die vertically and using TSVs to interconnect them. 3D offers, compared to 2.5D, further power reduction, much lower latency and increased bandwidth. Several suppliers have already stacked memory die to build much larger memories than 2D technology would allow. Such memory stacks, on top of logic, will soon be deployed in mobile applications, such as smartphones, tablets or netbooks. Stacking multiple logic die in such a configuration requires further progress in design tools and manufacturing methods before logic die stacks become practical.
The True 3D column on the far right looks into the future and refers to ongoing development efforts at very large corporations. Their goal is to stack multiple layers of functions by running wafers multiple times through the wafer fab, each time putting another chip on top of the previous ones. As this table indicates, Technology Readiness is difficult to predict for this alternative. The top six rows focus on technical topics and the bottom two rows of Table 1 look at commercial considerations: NRE cost, risk, time-to-market and general technology readiness. They are important decision criteria as well, especially for lower to medium production volumes. These two rows also indicate when it will be possible to find development and manufacturing partners for the new technology alternatives.
2-dimensional
System-on-Chip
Monolithic IC
SoC
Package on Package PoP
System in Package SiP
Interposer with 2 or more die 2.5D
Vertically stacked die with TSVs 3D
3-dimensional
Monolithic
(sub)system True 3D
Power Dissipation
All on chip
Ext. Memory
Latency Bandwidth Package Height

Boardspace
Heterogeneous Functions
All on chip Ext. Memory All on chip Ext. Memory
Side by side
Vertically
Time2 Mkt,
Risk,NRE,
Technology
Memory
Logic
Readiness
Limiting
o.k.
Good
Very good
Table 1. Technology Alternatives and Trade-offs
Fig. 2. Combination of four FPGAs Xilinx introduced in Fall 2010
A CLOSER LOOK AT KEY BENEFIT OF 2.5D AND 3D TECHNOLOGY More bandwidth and lower latency As outlined above and further detailed in the white paper the link leads to, 2.5D technology allows Xilinx to fit much more functionality into a package than a monolithic die, even in the next-generation process would allow them to achieve. In this case a 2.5D IC combines a number of FPGAs into a larger configuration and offers users higher complexity, lower latency, much more bandwidth between the FPGA slices and significant power savings, compared to four individually packaged FPGAs. Notably, the higher bandwidth, combined with power savings, makes 2.5D and 3D very attractive for combining high-speed logic with a large amount of memory, in one or multiple die. Today the performance of single-core, and especially multi-core CPUs, is typically limited by the bandwidth to memory. To overcome the limitations in pin-counts, latency and data bus width, developers need to plan large amount of costly on-chip memory on 2D SoCs. 2.5D allows much wider busses than chip-to-chip interfaces on a PC board and reduces power dissipation significantly, compared to individually packed die. 3D technology offers practically unlimited data bus widths, much less latency and several orders of magnitude lower power dissipation than DDR3 or even LPDDR3 interfaces.

One important reason for combining logic die (CPU, GPU, etc.) with large amounts of memory in 2.5D or 3D is the demand for streaming HD video in mobile devices. HD requires 12.8 Mbits/sec of bandwidth. In batterypowered devices, 2.5D and 3D make this high data-rate practical. Recognizing the need for wide data busses and standardization, a number of companies have joined forces and already established the Wide I/O Standard. See more about this 512 bit wide bus in YOLEs MicroNews, Issue 17 at http://www.i-micronews.com/upload/3DPackaging/3DPackaging_17.pdf. A high degree of IP reuse reducing engineering efforts, time-to-market and re-spin risk A typical 2D SoC is comprised of a large amount of on-chip memory, power-hungry I/O buffers and logic circuitry. Up to 90% of this logic is legacy code (in-house IP) and third-party IP. Instead of focusing the available IC design resources on the remaining 10 percent, 2D SoC designers need to implement and verify the entire circuit a time-consuming task, were mistakes are costly. Such a partially new SoC design requires the same NRE and engineering efforts for prototyping and production ramp-up as an entirely new design and requires the same volumes to recoup these cost. 2.5D offers a high degree of IP reuse and a much more economical approach to lower- and medium volume designs. Engineers may be able to arrange proven flip-chip SoCs side-by-side on an interposer, connect them to each other and a new die, containing the added functionality. For higher volume 2.5D designs, proven die can be cost-reduced by replacing the I/O buffers with smaller versions, saving power and silicon area (cost), if the project schedule allows. As soon as in-house or merchant 3D-IP (entire die, ready for TSV interconnects) becomes more widely available, designers can plan on stacking proven IP in die form and interconnect them with TSVs. This will not only reduce power and latency further as well as boost bandwidth even more, but also offer system architects a lot of added flexibility: They can mix and match proven designs with new, differentiating circuits and get to market quickly. Heterogeneous integration: Combining logic, analog, RF, FPGA, MEMS, etc., cost-effectively 2D SoCs, especially when using very small feature sizes and sub-1V supply, make it very difficult to utilize a single process technology to combine high speed logic, stable memories, precision analog, high-quality RF circuits and other functions (MEMS, FPGAs, etc.) on the same die. 2.5D and 3D ICs allow the combination of dielevel IP on an interposer or as part of a vertical die stack. Every one of these die can be designed for and manufactured in a different process technology to minimize cost and power dissipation, while achieving the best possible performance in the most appropriate process technology. Reduced form factor: Smallest space and weight possible today Form factor may sound trivial, but it is very important for achieving small and thin mobile internet devices. Electronic devices such as medical applications will demand even smaller form factors. Sensors, analog and RF circuits, CPUs and memory will need to be packed into tiny devices to monitor and assist humans and increase their quality of life. BUSINESS- AND ENGINEERING CHALLENGES 2.5D AND 3D TECHNOLOGY FACES This message would be incomplete if it only praised the many benefits these new technologies offer without emphasizing that these are emerging technologies. Like previous technology transitions demonstrated, new technology is riskier and initially more costly than a mature alternative.

Readers who have lived through a number of these technology transitions will appreciate the growing pains as being temporary challenges, and not lose sight of the long-term benefits their companies can gain by being early adopters. Especially in EDA, where users tend to remain loyal to good tools, the early winners during the initial wave of adoption will, most like, earn their long-term leadership too. The EDA challenges, addressed by the majority of contributors to the 3D-IC Tour Guide, are one important area in the complex semiconductor ecosystem. Equally, if not more challenging, are the development efforts manufacturing- and test equipment vendors need to complete to establish cost-effective 3D production capabilities. The OSATs (outsourced assembly and test service providers) provide only a small portion of 2D SoC products value; however, 3D technology makes the OSATs role much more important and the opportunity for financial gain much larger. 2.5D and 3D also impose changes for the roles and responsibilities in the supply chain. To take full advantage of all the benefits, the semiconductor ecosystem needs to learn how to solve the remaining technical and business challenges 3D is introducing. New ways and rules for cooperating more broadly across the entire supply chain are needed. It is also very important to define data exchange formats between the many 3D design steps. Rules for design hand-off to manufacturing and transfer of responsibilities need to be agreed upon. Likewise, the manufacturing partners (fab, assembly, test) need to define who does what and who takes responsibility for the outcome. 3D die stacking with TSV interconnects is a revolutionary step. The many skeptical questions and comments faced a year ago were clearly justified. Stacking die and various ways of interconnecting them directly had been tried multiple times. These efforts started more than a decade ago, but never became main stream, because of their revolutionary nature and significant transition cost. Smart engineers in the industry always found a way to push the 2D SoC envelope and made the traditional way of designing and manufacturing more cost-effective for most applications than either one of these new technologies, which delayed their introduction. PoP and SiP are examples for three-dimensional configurations that succeeded in certain applications, because they offer part of the benefits of 3D/TSV technology at reasonable cost. However, a broad market adoption of 3D/TSV technology is still a few years away. R&D departments are working hard to develop high-yielding and reliable TSV manufacturing flows. EDA vendors are communicating with material suppliers, fabs, assembly houses and tester vendors to reflect all these companies capabilities in their 3D-IC design tools and methodologies. To bridge this 3D development time, and to create a viable, long-term alternative to 3D ICs for many applications, R&D experts developed the interposer-based 2.5D technology. 2.5D ICs have already demonstrated some of the technical benefits of 3D ICs, offer manageable development cost, as well as attractive unit cost and made 2.5D a sensible alternative to 2D SoCs and even 3D in many applications. 2.5D, interposer-based configurations are an evolutionary step. If the applications you target do not impose very tight space constraints or very strict power limits and/or performance requirements, consider an interposer-based 2.5D solution as your current, and possibly long-term solution. Compared to multiple 2D SoCs, a 2.5D design will also reduce power dissipation and latency, while increasing speed and bandwidth. A number of companies introduced 2.5D designs in 2010 and ramped up production in the later part of last year or earlier this year. Fig. 2 shows how Xilinx utilizes 2.5D to win demanding customers and grow FPGA revenues.

When evaluating 2.5D and 3D benefits for applications, study the main part of this 3D-IC Tour Guide to see which companies can assist you. Check if starting a 2.5D design now makes sense for your applications and if/when you should consider utilizing 3D technology to grow your business. ADDITIONAL INFORMATION SOURCES Partners represented in the 3D-IC Tour Guide The market research companies provide useful information about these emerging technologies, both from a technical and commercial perspective for any 3D business plan. The EDA vendors show their design tools for planning, implementation and verification steps. R&D centers outline their experience and plans for 2.5D and 3D technologies. Large industry organizations outline their activities and plans for driving standards. A value chain producer shows how to partner for development and production ramp-up. Books Focused on 2.5D and 3D Topics at Amazon.com Three Dimensional System Integration: IC Stacking Process and Design
Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits (2 Vol. Set) Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures (Integrated Circuits and Systems) Three-dimensional Integrated Circuit Design (Systems on Silicon)
Other Information Sources Dr. Phil Garrous Information From The Leading Edge, e.g. # 48 (the latest): Many other 3D - IC articles and resources at www.google.com
Download an electronic copy of this report at: http://www.gsaglobal.org/eco/index.aspx?tab=8#eda_pres
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MARKET RESEARCH
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3D-Incites
3D INCITES: STIRRING UP INTEREST IN 3D INTEGRATION Incite means to "stir up" and "inspire interest in", as such, 3D InCites was created to stir up interest in 3D integration. It is a partner/sponsor supported interactive web community where visitors and contributing partners share information and engage in discussion of technologies and trends that will lead to market adoption of 3D integration technologies. More than just an online publication, 3D InCites exists to benefit its contributing partners, registered members, and visitors alike. Ideally, it is a work in progress that continues to expand with partner participation. A Global Community for 3D Integration Enthusiasts 3D InCites Members: Embrace Change Explore Ideas Share Knowledge Achieve Goals Integration is the Key.. The word "Integration" not only refers to the technical process of integrating, but also to the integration of people and their knowledge. Erik Jan Marinissen, imec Your 3D blog is part of the solution. It is the education component that is critical to lowering any adoption barrier, spreading knowledge and ideas to anyone considering 3D and TSVs. Bill Martin, E-System Design Partnership Privileges and Opportunities
Contributor Access Forums Discussions Dedicated Blogs White Paper Posting Live Events Videos, Photos Press Releases Product Announcement And much more
BECOME A MEMBER: www.3dincites.com To Discuss Partnership/Sponsorship Opportunities Contact Leo Archer, Leo@3dincites.com
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TechSearch International, Inc.
3D TSV MARKET TRENDS AND TECHNOLOGY RESEARCH TechSearch International, Inc. was founded in 1987 as a market research and consulting company specializing in emerging semiconductor packaging trends. Multiand single-client services encompass market research, technology trends, strategic planning, and technology licensing. TechSearch has a focused effort on analyzing the applications, barriers, and infrastructure for 3D integration with TSVs and developments in 3D ICs. Company analysts have published three studies on the topic and have delivered presentations around the globe, chairing panels and delivering keynote addresses. 3D TSV 3D Through Silicon Via (TSV) technology is one of the hottest topics in the industry today. Potential applications for 3D TSV include image sensors, memory, memory and logic, and other areas. There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. While image sensors for camera modules are already in volume production, the adoption time for other applications is longer than originally predicted, as is common with the introduction of many new technologies. Design, thermal, test, and infrastructure issues remain a barrier to TSV adoption in some applications, although progress is being made. TechSearch International analysts provide extensive coverage of the latest developments in 3D IC and provide market forecast for each application area. Major application areas for 3D TSV include processors (i.e., CPUs, GPUs) and field programmable gate arrays (FPGAs) (Table 1). Memory is also a major application area both as a stacked cube and combined with logic. Stacked memory using TSVs is expected to be introduced by several memory makers very soon and mass production is scheduled in the next 12 to 18 months, according to Microns COO. Elpida, Samsung, and Toshiba are also in various stages of devising TSV-based 3D chips. Table 1. 3D TSV Applications Status Application Image sensors CPUs + memory GPUs + memory FPGAs Wide I/O memory with processor Memory (stacked) Driver Performance, form factor Performance Performance Performance Performance (bandwidth extension, lower power consumption), form factor Performance, form factor (z-height) Barrier None Cost, process yield, infrastructure Cost, process yield, infrastructure Cost, process yield, infrastructure Cost, process yield, KGD, infrastructure (including business logistics) Cost, process yield, assembly
Source: TechSearch International, Inc.
3D TSV is moving from PowerPoint engineering into real engineering. The demand for the technology remains driven by performance needs and many companies have documented its benefits. Typically the driver is high bandwidth between memory and processor and the need for lower power. The industry is clearly focused on solving problems associated with improving yield and lower cost. Many standardization efforts are underway. A number of issues that need to be resolved before 3D TSV can be realized. They include: Availability of design guidelines and software tools Foundry capacity and process development Assembly (bump, singulation, assembly, and test)
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Silicon Interposers TechSearch International has published extensively on silicon interposer technology. Silicon interposers are an option for partitioning large die, integrating single chips into a module, and reducing die size where substrate density is the constraint. One driver that has emerged more recently is the challenge of assembling die with extra-low-k (ELK) dielectrics. The problem is worst for large die, where thermal excursions are largest and stresses on the fragile dielectrics highest. Silicon substrates offer the following advantages: High wiring density due to the very flat substrate CTE matched to the silicon die Excellent electrical and thermal performance Lower laminate substrate cost due to reduced wiring density Lower cost of active devices due to partitioning large die with minimal effect on performance Higher yield (lower cost) of active devices due to smaller flip chip bump pitch Lower power requirements than equivalent single-chip packages due to multiple chips combined on one substrate Possibility of integrating passives into the substrate Xilinx recently announced its 28nm Virtex-7 LX2000T using a Stacked Silicon Interposer as the worlds first multi-die FPGA providing more than 3.5X the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers. The device is made possible by using four FPGA slices fabricated by TSMC that sit in a side-by-side configuration connected with Cu pillar micro bumps to a passive silicon interposer. The interposer, fabricated by TSMC uses 65nm silicon technology and has four conventional metal layers to connect each FPGA slice. The passive silicon interposer has several thousand TSVs. While many companies have contemplated the design of structures with silicon interposers, the industry infrastructure and supply base for the widespread adoption of the technology has been a concern. The Xilinx announcement aids in the development of the infrastructure that includes equipment manufacturers, fabs, and OSATs. A robust supply chain enabled by a close partnership among Xilinx for FPGA, interposer and package design plus final package test, TSMC for 28nm FPGA and interposer fabrication, Amkor for micro bumping, die singulation, chip-on-chip attach, and assembly, and Ibiden for package substrate clearly shows the importance of virtual integration in moving from R&D projects into commercialization. According to Xilinx, other important factors in commercializing this technology include known good die (KGD) and the promotion of standards. Additional Research Topics Additional research topics from TechSearch International include wafer level packaging, flip chip interconnect, CSPs, BGAs, manufacturing in China and India, multichip packages (MCPs) such as stacked die CSPs and System-in-Package (SiP), embedded components, microvia substrates, LED assembly, and Pb-free manufacturing. Market forecasts and trends in advanced semiconductor packages and materials are also available. TechSearch International professionals have an extensive network of more than 15,000 contacts in North America, Asia, and Europe and travel extensively, visiting major electronics manufacturing operations and research facilities worldwide. TechSearch International Inc. 4801 Spicewood Springs Rd., Suite 150, Austin, TX 78759 Phone: 512-372-8887 | Fax: 512-372-8889 | http://www.techsearchinc.com E-mail: tsi@techsearchinc.com Contacts: E. Jan Vardaman, Becky Travelstead
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Yole Developpement
YOLE DVELOPPEMENT: STRATEGY CONSULTING & MARKET RESEARCH COMPANY IN THE FIELD OF 3DIC INTEGRATION & ADVANCED PACKAGING Yole Developpement is a market research and strategy consulting company founded in 1998. Located in Lyon, France, the company account for a team of more than 20 analysts operating worldwide in the fields of MEMS, LED, power electronics, solar, microfluidic and advanced packaging. The company has developed three main activities in the 3DIC area:
Consulting business: www.yole.fr Media business with a news feed website and a quarterly published 3D Packaging Magazine: http://www.i-micronews.com/3DIC.asp Report business: http://www.i-micronews.com/reports/#8
Extract of Recent Research The continuation of Moores law by conventional CMOS scaling is becoming more and more challenging, requiring huge capital investments. 3D Packaging with 3D TSV interconnects provides another path towards the More than Moore, with relatively smaller capital investments. 3D integration are strategic innovations for the future semiconductor industry as it will enable the possibility for SOC System-on-Chips to keep pace with the Moore law for at least two more decades if the design / manufacturing / cost requirements are met quickly. As of today, more than 15 different 300mm 3D-IC pilot lines running or currently being installed worldwide have been identified (R&D centers, at packaging houses, CMOS foundries or within IDM fabs).
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Strong dynamics in MEMS, CMOS image sensors, memory, analog, power, RF and digital industries continue and will drive adoption of TSVs to high volumes within the next decade to benefit from this disruptive interconnect technology!
However, challenges are still ahead before volume adoption of 3D-ICs into mass markets:
3D infrastructure and supply chain is the biggest immediate issue identified for the broad adoption of 3D-ICs. As many scenarios are possible for the implementation of 3D TSV interconnects (via first/via middle/via last/via After Bonding), a big question at the moment is WHO will take the risk to invest and will have the ownership of the realization of the different 3D TSV process steps (to be implemented in front-end, mid-end, back-end)? I/O standardization between interfaces, such as memory to digital layers is also a serious issue that needs to be fixed rapidly. Indeed, 3D integration of memory and logic ICs is perceived as the next big wave for volume adoption of 3D TSV in the near future. Multiple applications are targeted, including CPU, GPU, DSP, FPGA, ASICs and Basebands ICs that will be used in future cell phones, super-computers, network / storage systems, notebooks, automotive and medical processing units among others. Thermal management and interconnect reliability could also reduce 3D-IC application space in the longer run. However, different solutions are currently underway in response to this possible challenge.
Jean-Christophe Eloy CEO & President, Yole Developpement 45, rue Sainte Genevive, 69006 Lyon, FRANCE Email eloy@yole.fr | Tel + 33 472 83 01 80
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EDA VENDORS
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Apache (Booth #2448)
OVERVIEW OF DEDICATED 3D CAPABLE TOOLS:
Design Steps Modeling of die-to-die and/or die-to-package power delivery network interactions. Power analysis of 3D / stacked die with TSV and micro-bumps.
Brief Description Creates power model of the die with die-to-die or die-to-package protocol interface to support 3D analysis. Performs static, dynamic, and low-power analysis of multiple stacked die with TSV and micro-bumps in either full-detail or model-based methods.
Product Names Chip Power Model, RedHawk RedHawk
Power Noise Challenge for Multiple Stacked Die with TSV 3D structures can cause considerable challenges in power delivery network (PDN) designs. The top die of the structure is susceptible to noise coming from its own switching, as well as the power noise coming from the die below, and the increased distance from the package makes the PDN noise considerably higher. Therefore, the power delivery network cannot be analyzed in isolation due to the coupling of the switching current on multiple networks and increased parasitic impedance in the supply paths. An accurate analysis of power and noise for a 3D structure with TSV requires having accurate die and TSV modeling and highcapacity simulation solutions. Apaches Solutions Apache Design Solutions offers two methods for analyzing the power noise of a stacked die configuration; a model-based and a concurrent simulation approach. A model-based approach utilizes a Chip Power Model (CPM) to represent each of the dies power behavior. Using RedHawk, multiple CPMs along with the extracted model of the TSV structures, are simulated for full-chip power analysis. It considers the count, design, and placement of the TSV arrays to accurately connect them to the on-die power network of multiple die. This approach is useful when the 3D-IC integrator does not have access to the full layout database of one or more of the die in the stack.
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A concurrent analysis-based approach performs simultaneous simulation of the full design database and the layout of the die, along with extracted TSV arrays. Its high-capacity extraction and simulation engine enables RedHawk to perform both DC and time-domain analysis of the full 3D-IC design, in under an hour to within a few hours, respectively. Both the model-based and concurrent analysis-based approaches include the package parasitic in its simulation for more accurate representation of the full 3D-IC chip design. For More Information http://www.apache-da.com/products/redhawk/redhawk-nx http://www.apache-da.com/products/redhawk/chip-power-model http://www.apache-da.com/system/files/DAC_2010_UT_PosterAnalysis_of_Power_Delivery_Network_Multiple_Stacked_ASICs_0.pdf
Learn more about Apaches products/services at booth #2448. Visit with one of our Power Team Experts!
Email: apache_sales@apache-da.com | Phone: 408-457-2000
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Atrenta (Booth #1643)
EARLY PARTITIONING AND PLANNING OF 3D STACKS (PathFinding) Atrenta and imec are collaborating on the development of design methodologies and an advanced planning and partitioning tool flow for heterogeneous 3D-SICs. The tool flow enables optimization of 3D ICs and the associated technology based on a 3D system prototyping approach, sometimes referred to as PathFinding. We have already demonstrated the first EDA design tool flow for 3D exploration that will minimize design iterations and facilitate a costeffective search of the solution space. Overview Figure 1 provides a high-level overview of the design flow we will discuss. While early planning and partitioning is viewed by some as a nice-to-have technology for conventional 2D system on chip (SoC) design, it becomes a must have technology for 3D stacked die design. The number of potential solutions to a given system design problem becomes very large (e.g., front-to-front, front-toback, silicon interposer, technology choice for slices, TSV configurations, etc.) Exploring this solution space through multiple full implementation scenarios is simply too expensive and time-consuming. The available time and financial budget for any reasonable project will not support multiple implementation iterations. This makes it critically important to perform robust, accurate partitioning and prototyping early in the design process, well before detailed implementation begins. Highlights of the work The current work is based on a combination of synthesized test cases and real design examples from partner companies associated with this research. To illustrate the approach we consider an arrayed structure of CPUs, with each node in the array consisting of a CPU core with associated L1 memories, a switch to provide the interconnection to adjacent nodes (i.e., NoC) and L2 cache. 3D partitioning allows one to easily move components of the array to a different tier/die and determine the performance metrics associated with that decision. Figure 2 illustrated the process.
Fig. 1. Overall design flow
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Fig. 2. Partitioning From logical to stack view Once the partitioning is performed, the floorplanning of individual tiers can be performed. Figure 3 illustrates a case where automated partitioning of a 2D design was accomplished with user directives. Automated floorplanning of the individual tiers was implemented and back-side routing for multiple TSV/bump configurations was accomplished, creating representative 3D design options.
Fig. 3. Automated partitioning Inter-die connections for 3D are evolving. Previously, TSVs acted as I/O pads anywhere in the die. Today, redistribution layer routing and microbumps provide more flexibility. These structures can be aligned, nonaligned, constrained or freely placed. A sophisticated tool is needed to optimize these situations, as shown in Figure 4.
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3D stacked design also presents significant challenges regarding thermal profiles (heat dissipation) and mechanical stress due to assembly configurations. imec has developed a compact thermal model that allows heat maps to be rapidly generated and overlaid on the design floorplan produced by Atrentas SpyGlass Physical prototyping tool, allowing multiple scenarios to be assessed as shown in Figure 5.
Fig. 4. Inter die connectivity
Please visit Atrenta in booth #1643 at DAC to learn more and see a live demo of our 3D prototyping flow
Fig. 5. Compact thermal model
For more information, contact: Brad Nold, nold@atrenta.com
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CAD Design Software
CAD DESIGN SOFTWARE, DIV. OF CAD DESIGN SERVICES, INC. 2975 Bowers Ave., Suite 315, Santa Clara, CA 95051 408-436-1340 Ext. 302 www.CAD-Design.com hschiesser@cad-design.com CAD Design Software 3D Designer This module extrudes the 2D outlines of components, substrates, cavities, TSVs, Vias, holes and wires to make 3D shapes. It automatically generates ACIS compatible solids including voids, holes and boundaries from a design done with CAD Design Software. It is automatically configured from thicknesses stored in the material stack-up section of the Technology system. It makes 3D models of TSVs, Vias and bond wires by combining a side view profile (unlimited numbers of profiles can be made) with the top view of the TSVs, Vias and wires. It extrudes along the custom Bond Wire profiles to make any shape 3D bond wires. It extrudes TSVs, Vias, holes and then subtracts them from the substrates, traces, pads, planes etc. To make a full 3D model of an entire design once a 3D model is made the advanced rendering options in AutoCAD can be used to generate realistic images or simple wire frames. It can then be exported to ACIS or STEP to transfer a 3D model into a thermal or electrical analysis tool. This product may also be purchased separately as an add-on module to any CDS Designer Suite. Sample Designs
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CAD Design Software Master and Designer Suites Master PCB Designer Suite (MPD) Master Ceramic / MCM Designer Suite (MCMD) Master RF Designer Suite (MRFD) Master Lead Frame Designer Suite (MLFD) Master BGA Designer (MBGAD) Master IC Test Designer Suite (MITD) Value PCB Designer Suite (VPCB) PCB Designer Suite (PCBD) Ceramic / MCM Designer Suite (CMD) RF Designer Suite (RFD) Lead Frame Designer Suite (LFD) BGA Designer Suite (BGAD) Flex Designer Suite (FLXD) PCB CAM Suite (PCAM) Ceramic / MCM CAM Suite (CMCAM) Lead Frame CAM Suite (LFCAM) BGA CAM Suite (BGACAM) Import / Export to and from Simulation Tools Simulate new or existing Lead Frames by exporting to various simulation software including ANSYSs HFSS and Q3D, CSTs MWS, and even into Cadence APD/SIP to enable co-design of the die in Virtuoso.
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Full system design with 2 stacked Dies connected with TSVs in a package attached to a BGA substrate are designed with CDS Master Designer Suites.
Contact for 3D info: Hans Schiesser, Tel 408-436-1340 Ext. 302 Email: hschiesser@CAD-Design.com
www.CAD-Design.com
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Cadence (Booth # 2237)
OVERVIEW OF CADENCE METHODOLOGY AND PRODUCT PORTFOLIO SUPPORTING 3D-ICs Below is a complete set of capabilities that Cadence offers today to help you realize your 3D-IC designs. Our methodology is validated on multiple test and production chips. Key 3D design steps Brief description of your tools purpose Remarks or Product Names Cadence Design IP portfolio
Wide I/O memory controller
Promises high bandwidth, low power consumption. Enables stacked die configurations; can also be used in silicon interposer implementations with side-byside die Analyzes cost delta between implementing logic in 1 large die vs. 2 or 3 smaller die, and the performance impact
System partitioning/ exploration tools for 3D-IC designs
Cadence Chip Planning Solution + Encounter Digital Implementation System Encounter RTL Compiler and Encounter Test
3D-IC design for test (DFT) insertion and test generation
Enables modular SoC testing at Wafer test by using DFT wrappers (IEEE 1149.1 boundary scan standard and IEEE 1500 embedded core test standard) and extending them to interconnect testing of signals between dies, including TSVs with enhanced 3D-IC specific extensions. DFT architecture was jointly developed with IMEC. Optimizes through silicon via (TSV) and micro bump placement through entire stack (co-design among analog, digital, and package) Placement, optimization, and routing (co-design among analog, digital, and package) - Verifies power and signal integrity across stack - Analyzes effectiveness of integrated caps (co-design among analog, digital, and package) - Thermal analysis and signoff: floorplan optimization, signoff for hotspots, impact on performance or leakage - Interacts with package environment - Chip-package-board optimization - Testbench support for chip/die/analog/RF
3D-IC floorplanning and optimization Tools for 3D-aware implementation Tools for verification and extraction of 3D stacked die Tools for thermal 3D stack analysis
- Encounter Digital Implementation System - Encounter Power System - Encounter Timing System - Cadence QRC Extraction - Cadence Physical Verification System - Analog: Virtuoso unified custom/analog flow - Package: Cadence SiP co-design solutions
SiP co-design
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OVERVIEW OF CADENCE 3D-IC METHODOLOGY Plan Implement Test Verify
Key Features and Benefits: Cadence Wide I/O Memory Controller and IP Portfolio Wide I/O memory is a new DRAM technology and an emerging JEDEC standard that calls for a 512-bit wide interface and 12.8GB/second bandwidth. In addition to high bandwidth, it promises low power consumption. It targets mobile devices, where space is at a premium, performance and power demands are stringent, and for which 3D-IC design is ideal.
Cadence announced the industrys first Wide I/O Memory Controller IP solution in March 2011: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=032811_iomem Cadence Design IP delivers the highest quality IP and ensures the lowest risk path to SoC Realization: http://www.cadence.com/solutions/dip/Pages/Default.aspx
Encounter Digital Implementation System Encounter Digital Implementation (EDI) System is a high-performance, advanced design closure solution for both flat and hierarchical designs that also addresses the latest requirements for low-power, mixed-signal, and advanced-node design, including 32/28nm. EDI System gives engineers an early, accurate view of design feasibility and allows them to progress immediately to full-scale implementation and final signoff for large-scale, complex designswithout ever leaving the solution environment. http://www.cadence.com/products/di/edi_system/pages/default.aspx
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EDI System has also extended its technology into the 3D-IC world by providing an automated and integrated 3D-IC/TSV implementation and analysis design solution that supports timing, thermal, and signal integrity analyses. For details, please contact Samta Bansal: samta@cadence.com DesignCon DesignVision Award finalist, 2010 and 2011 EDN Innovation Award 2010 for 3D-IC capabilities: http://www.edn.com/article/457631-EDN_s_20th_annual_Innovation_Awards_Finalists.php
SiP Co-Design Tools SiP development requires co-design directly with chip teams based on the connectivity-authored interconnect strategy. Cadence solutions provide I/O optimization, tradeoff simulation, and constraint-driven implementation. Cadence analog and RF SiP design begins with chip design data and enables package-level simulation, optimization, and verification. http://www.cadence.com/products/pkg/Pages/default.aspx Analysis Tools (Encounter Timing System, Encounter Power System, QRC Extraction) Cadence signoff analysis technology brings together logical, physical, electrical, and manufacturing domain requirements in a single, easy-to-use environment, enabling front-end to back-end design handoff, signoffdriven implementation, and final signoff. It analyzes timing, signal integrity, power consumption, statistical static timing, electro-migration, and thermal characteristics using effective current source models (ECSMs). With multi-dimensional root-cause analysis, designers can shave weeks off tapeout schedules and prevent silicon failures. Cadence 3D-IC stacked die analysis: http://www.cadence.com/products/di/Pages/default.aspx Physical Verification System Physical Verification System (PVS) supports DRC and LVS verification flows for 3D-IC and is qualified as part of TSMC Reference Flows 11.0 and 12.0. The PVS DRC flow checks uBump alignment; PVS LVS verifies the connectivity among designs through the die interfaces (mBumps or pads locations), and check pads without TEXT and Signals. Integrated with industry-standard digital and custom design flows, PVS enables designers to procure a front-to-back design and signoff flow from a single EDA vendor. Its one tool, one deck model for digital and custom design minimizes support overhead. http://www.cadence.com/products/mfg/pvs/pages/default.aspx Virtuoso Unified Custom/Analog Flow The Cadence Virtuoso-based unified custom/analog flow automates many of the routine tasks in custom IC design, allowing engineers to focus on differentiating their designs. http://www.cadence.com/products/cic/Pages/default.aspx Encounter Test Product designers are striving to pack a lot of functionality into silicon by using smaller geometries and 3D-IC packaging. Encounter Test technology delivers a highly integrated synthesis and test flow that provides very high defect coveragewithout overstressing design area, timing, power, and packaging constraintsin a lowcost, pin-limited test environment. We have extended the DFT test insertion support for 3DIC stacks in Encounter RTL compiler and Encounter Test with close collaboration with IMEC .
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Encounter DFT Architect is the industrys first full-chip, truly synthesis-based, power-aware test architecture design technology. It supports full and partial scan, JTAG (1149.1/6) insertion and verification, and I/O test, as well as flexible, scalable, low-pin, and bottom-up hierarchical compression architectures that can support multisite wafer test. Encounter DFT Architect also supports BIST solutions, optimizes both pre- and post-synthesis test coverage, and automates on-product clock generation (OPCG) and script generation for static and transition-based test patterns. http://www.cadence.com/products/ld/test_architect/pages/default.aspx Cadence Chip Planning Solution Cadence Chip Planning System helps electronics companies realize the biggest benefits by considering and quantifying a variety of architectural and IP reuse options early in the IC design cycle. It helps users plan IC designs, consider the reuse of internal or external IP, and accurately estimate key technical and economic metrics of a potential IC. http://www.cadence.com/products/ld/chip_planning_system/pages/default.aspx Learn more about 3D-IC from Cadence in Booth #2237 at DAC: Cadence EDA360 theater: Booth #2237 Hear Cadence and partners talking about 3D-IC topics and sharing our experiences on the real work weve been collaborating on. Cadence 3D-IC technology demonstrations: Booth #2237 Come see 3D-IC with TSV in actiona truly integrated analog, digital, and package system. We will showcase how to achieve Silicon Realization by capturing 3D-IC design intent upfront and abstracting the stack data to speed multi-chip analysis and convergence on design goals. 3D-IC DFT: Achieving High-Quality Products with a Highly Integrated Synthesis and Test Flow: Get a preview of the Cadence 3D-IC DFT techniques during this session. TSMC Booth: Learn more about the Cadence 3D-IC methodology in the Reference Flow 12.0.
For any questions on Cadence 3D-IC offerings Ask for Samta Bansal - email samta@cadence.com / Visit us at www.cadence.com Visit the Cadence Booth # 2237
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Coventor (Booth #1719)
COVENTOR: THE LEADER IN MEMS DESIGN AUTOMATION SOLUTIONS Coventor, Inc. is the market leader in automated design solutions for microelectromechanical systems (MEMS) and virtual fabrication of MEMS and semiconductor devices. Since its inception in 1996, Coventor has been exclusively focused on developing and delivering best-in-class simulation technology and design automation software for MEMS. The company offers a platform of simulation technologies, domain expertise, and partnerships that have been used to develop hundreds of MEMS designs. Its solutions enable designers to rapidly explore design trade-offs, understand the intricacies of their design and process, and optimize system and packaging aspects up front and in parallel with dramatic time and cost savings compared to traditional build and test methodologies. A Complete Platform for MEMS Coventor offers a range of 3D modeling tools that allow the design and analysis of MEMS and MEMS+IC at multiple levels of abstraction and at different stages of the development process.
Process Development Device Design Design Verification System Optimization
Simulate
Sensitivity Linearity Frequency response Signal-to-noise Cross-axis sensitivity Temperature stability Switching time Contact force Efficiency (Q) Power transmission
Design exploration and system design MEMS +IC design
MEMS+
Multi-physics simulation Stress analysis Damping effects Packaging effects
CoventorWare
SEMulator3D
Process emulation 3D Silicon-accurate geometry
Process corners Continuity & shorts Release etching And more
MEMS+IC Coventors approach goes beyond the MEMS device. Its platform extends world-leading simulation tools from Cadence and The Mathworks, adding capabilities to accurately predict non-linear, electromechanical device behavior and simulate system performance, including process effects, packaging effects, and MEMS+IC coupling. This eliminates the need for hand crafting models and dramatically reduces the number of wafers and fab cycles typically required of design and test MEMS strategies.
Visit Coventor at DAC Booth# 1719

Phone: (919) 854-7500 ext. 132 E-mail: sales@coventor.com
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DOCEA Power (Booth #1912)
ACEPLORER, LOW POWER ARCHITECTURAL EXPLORATION OF 3D DESIGN
Key features of Aceplorer and use for: Architecture and low power strategies exploration, use case profiling / System dimensioning Power aware embedded software development Power management software validation against dynamic behavior Power driven hardware and software partitioning Early power and thermal distribution estimation for temperature sensitive designs Early Analysis of risks (e.g. power budget, peak temperature, IR drops, thermal runaways) Making decision support for process technology, packaging or cooling system selection Export and support of power intent format, UPF
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User Benefits Productivity Gains: Reduced development and maintenance time and more in-depth analysis compared to the spreadsheet approach Automated exploration of low power strategies to select the most efficient 3D architecture Scalable solution enabling collaborative work, model reuse and know-how capitalization Graphical tools, scripts, batch mode design space exploration, model checker to assist and secure model development Secure and optimize design: Very fast simulation allowing large design space exploration and what-if analysis Modeling uncertainties and interdependencies between parameters leads to more reliable prediction than traditional approach Exploring the impact of embedded software on power consumption at the architectural level Assessing risks that may cause design failures or threaten reliability with thermal simulation and IR-drop analysis at the architectural level. Earlier decision making for reducing time to market: Quickly identify at architecture level where design efforts will focus on Assess power management strategies and IP/IC before implementing them Automatically generate analysis reports, specs and UPF code for implementation teams
Input data and formats required Architecture and power models: Power simulation report, csv format, .lib, mathematical equations Architecture specifications Use case: Capture through the GUI vcd format from ESL or performance analysis tools
Output data and formats provided: A rich set of graphs and metrics are provided to enable an efficient communication and a comprehensive documentation to both customers and design teams. Aceplorer also outputs automatically UPF specifications used in further implementation stages, which limits the risk of miscommunication on the power intent of each design block.
More at the Companys booth: # 1912 Ridha Hamza, Tel +33 427 858 262 email: info@doceapower.com www.doceapower.com
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E-System Design, Inc. (Booth #3121)
INTRODUCING SPHINX 3D EXT, A 3D PARASITIC EXTRACTOR FOR 3D INTEGRATION
SI/PI integrity solutions for any dimension!

3D EXT was created to aid designers in choosing and optimizing 3D structures with minimal impact on electrical performance. Similar to Sphinx for Signoff, 3D EXT was developed based on research at Georgia Institute of Technology to provide: Accuracy over a broad frequency range Simulation speed Capacity Compatibility with standard spice simulators Accuracy is a given. 3D structures, whether they are wirebonds, vias, flex interconnects, column grid arrays or Through Silicon Vias (TSV) in a 3D stack are special since their physical structure can lead to skin, proximity, slow wave and dielectric effects. Any planning/analysis tool must account for various physical dimensions (separation, oxide thickness, height, conductivity, shape, signal:ground ratio, etc.) to correctly analyze these affects. A user can evaluate the various configurations to determine both local and global effects to determine the best solution based on their requirements. Capacity and Simulation speed is a must. Capacity and simulation speed are also very critical for 3D designs. If 3D interconnect structures are being considered, users should not be limited to a few 3D interconnects. Many bus standards contain 10-100s of interconnects. The signal speeds on these can vary from DC - mm-wave. This requires tools that have the capacity and simulation speed to provide quick turnaround time. Benefits of using 3D EXT are: Supports multiple 3D structures for IC stacking and interposer that include TSV, Column Grid arrays, Wire Bond, flex interconnects and Custom design structures Supports arrayed, staggered and custom configurations Allows users to create complex (side) profiles for vias Allows users to create detailed Wire Bond structures especially when they crisscross in a 3D stack Allows users to try various configurations and determine proximity affects based on signal:ground ratio long before implementation begins Outputs: Touchstone files, RLCG files ,current density and conversion into spice netlists A simple example demonstrates why3D Ext is critical solution to any 3D flow TSVs are notorious for creating residual coupling between each other at low frequencies due to slow wave effects and increased coupling at higher frequencies causing increased jitter and other signal integrity issues. These structures therefore have to be modeled well to extract their parasitic behavior.
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An example of a 3x3 TSV array is shown on the near right with a shell based representation. The far right is this structure implemented in 3D EXT. The positions are as shown with the numbers 1-9 representing the input ports and 10-18 the output ports. So, the result of the analysis is an 18 x 18 S-parameter matrix.
3 5 7 8 6 9
1 4
10 13 16
11 14
12 15 17 18
Frequency domain results for this small and simple example The below left view (a) shows Insertion loss from Top to Bottom of 3 of the TSVs. An insertion loss of -2 dB is quickly reached at ~1.5GHz, indicating the loss mechanism due to silicon. The below right view (b) shows crosstalk between various TSV pairs. Notice that each pair has different dB separation with the coupling between the nearest TSVs being the highest (-20 dB) and between the farthest TSVs (ports 1 and 9), the coupling is significant (-40 dB). Depending on the physical dimensions chosen, these signal integrity values can improve or worsen.
(a)
(b)
Time domain results for this small and simple example If we take the above response (b) and convert to time domain, we can view the mV impact due to this specific TSV configuration. The below left view (c) shows the nearest TSVs (ports 1 & 2) crosstalk while the below right view (d) shows the farthest TSVs (ports 1 & 9) crosstalk. Two important observations should be noticed: the
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cross talk is higher in TSV compared to PCB via arrays (~6X) for similar dimensions AND the NEXT pulse width is broader as compared to PCB via arrays and it broadens as one moves farther away from the source (not shown). These effects can be major problems since they affect jitter, voltage and timing margins.
See more at the E-System Designs DAC booth: # 3121 For additional 3D info, contact: Gene Jakubowski, Tel (678) 296-3772 email: ski@e-systemdesign.com
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Gradient (Booth #3249)
HEATWAVE 3D-IC Proven Thermal Simulator for IC and 3D-IC What if you knew the realistic operating temperature profile within your die-stack, before you tapeout? Highperformance chips have areas with very high-power density, causing temperature to rise unevenly within the die. Smaller form factors make it harder to remove the heat. For 3D-IC, thermal risks are increased relative to single-die; more thermal aggressors and victims are stacked together, closer to each other. Gradient has been working with 3D-IC research teams worldwide, to simulate temperature profile within stacked-die structures. HeatWave is a device-level thermal simulator for ICs and stacked-die SiP. It is used by leading semiconductor vendors worldwide to improve their circuit performance and reliability. HeatWave is the only thermal simulator that combines full-chip capacity with device-level resolution, and computes a 3-D temperature profile of your chip with spatial resolution that is commensurate with the layout feature sizes. Automates Device-Level CAD Data Exchange: HeatWave fits into the standard EDA ecosystem and makes use of existing IC design data, such as layout and power-source values and geometries, so that you can simulate the full-chip temperature without laborious data preparation. Thermal Floorplanning: HeatWave helps avoid thermal hazards early in the design cycle. It can be used for accurate thermal simulations of one or more defined regions on a chip, while only using layout and power abstractions for the remainder of the partially designed chip. Input data: HeatWave uses the full knowledge of the following: Chip layout geometries Power dissipation (values and bounding box locations) Thermal techfile (die stack-up and layer material properties) Package thermal model Output data: Device-level temperature profile can be viewed with GUI display, or annotated into your electrical analysis tools (e.g. circuit simulator), bringing thermally awareness to your design flow. Benefits: HeatWave enhances your ability Heat flux magnitude in TSV array to detect reliability and wear out/lifetime issues, using accurate and realistic temperature data. The designer can pinpoint hotspots and excessive temperature variationsand avoid thermally-induced circuit failures, performance degradations, and reliability issuesbefore building the chip or 3D-IC.
More at the Companys demo suites or booth: # 3249

(408) 748-3395 | sales@gradient-da.com
http://gradient-da.com
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Magma Design Automation (Booth #1743)
OVERVIEW OF 3D CAPABILITIES AND SOLUTONS
Proven Capability in 3D Implementation Magmas complete mixed-signal design and implementation system has been used for many 3D chip projects and tapeouts.
3D Design Activity
Modeling
3D SOLUTIONS
SiliconSmart ACE Tekton / QCP / FineSim Hydra
DESCRIPTION
Model creation timing/power/noise across multiple processes and conditions. Simulation of electrical behavior across multiple processes and process conditions. Automated design partitioning to achieve optimal quality of results and meet design goals. Convert 3D design into 2D blocks. TSV assignment.
Design Partitioning
Chip/Block Layout Layout Editing Physical Verification Timing Signoff
Talus Vortex Titan Quartz DRC/LVS Tekton / QCP FineSim
3D routing and physical implementation.
Define / edit TSVs. Visualize / edit multiple die. Integrated 3D DRC/LVS checking. DRC checking die. LVS checking across multiple die with TVS aware connectivity extraction. 3D extraction. Timing signoff at die level. 3D aware timing signoff across multiple die.
We have completed over 50 3D designs using Magmas technology for dozens of customers We use Magma for 3D DRC, 3D LVS, 3D Timing verification and for 3D routing. -- Robert Patti CTO, Tezzaron Semiconductor Corp.
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Magmas Integrated System for Digital/Analog/Custom 2D and 3D Design & Implementation
Die 2
Die 3
Die 5 Die 4
Die 1
Silicon interposer
Circuit Board
Want more information? Visit us at DAC Booth # 1743 Ask for Rob Knoth or Hamid Savoj Email: 3D_Info@magma-da.com Website: www.magma-da.com
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Mentor Graphics Verification (Booth #1542)
CALIBRE EXTENDED TO HANDLE 3D-IC VERIFICATION Calibre is the leading platform for IC physical verification, extraction, LVS and DFM. IC designers rely on Calibre to ensure their designs are manufacturable at the leading foundries around the world, and they expect Calibre to have the technology they will need, well before it becomes a critical path. 3D-IC is no exception, and Mentor has the solutions in place to meet the needs of designers building stacked die products today, whether they are based on SiP, silicon interposers or stacked dies with TSVs. Extending Calibre Solutions for 3D-IC At the current stage of 3D-IC evolution, customers need a solution that integrates well with their current design flows and design styles. That means the ability to easily assemble multi-die stacks from separately verified die. This allows users to achieve higher density, low power, greater bandwidth and mixed process systems-on-chip without disruption to their existing flows. The industry is converging on two basic configurations for stacked die with TSVs. Other, more complex, configurations combining 3D and 2.5 D are also possible.
3D: Vertical, chip-on-chip stack A 3D-IC stack verification, regardless of the configuration, includes DRC, LVS, parasitic extraction (PEX) and simulation. The typical approach is to do DRC/LVS/PEX of the individual dies separately, and then consider the interfaces (between the vertically stacked dies, as well as between the dies and an interposer). Separate 3D assembly GDS and netlist are formed consisting of the interface layers. The Calibre Solution Based on stack information (die order, x/y position, rotation and orientation etc.) provided in a rule deck, Calibre performs all DRC and LVS checking of complete multi-die 2.5D-IC and 3D-IC systems, and also provides parasitics in the form of individual chip netlists and a 3D stack top level netlist for simulation. Calibre delivers these capabilities without breaking your current tool flow or requiring new data formats. In addition, by enabling independent verification of individual chip designs, it provides maximum flexibility to mix die components manufactured with different processes or at different process nodes.
2.5D: Silicon Interposer based
Learn More at Mentors DAC Session on 3D-IC To learn more about Mentors 3D-IC verification solution, plan to attend our overview session at DAC entitled Meeting the Challenges of 3D IC Verification Today Sign up at the Mentor booth, #1542.
Visit us at Mentor booth #1542 Ask for Michael White, Matthew Hogan or Dusan Petranovic. http://www.mentor.com/products/ic_nanometer_design/
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Mentor Graphics Test
TESSENT SOLUTIONS FOR 3D-IC TESTING Available now from the leader in silicon test and yield analysis The migration to 3D-ICs using through silicon vias (TSV) presents three new challenges for IC test: The escape rate of defective die at wafer test must be lower to achieve post-packaging yield. There must be a way to deliver scan test patterns to the upper die in a packaged stack since only the bottom die has external connections The test strategy must include a way to test interconnects between the stacked die. Mentor Graphics Tessent product line provides test solutions for these unique 3D-IC requirements. Known Good Die (KGD) Requirements To improve KGD quality, test coverage and quality must be maximized. Through the use of advanced fault models, such as at-speed transition, in addition to the standard stuck-at and bridging models, Tessent minimizes test escapes that will show up later in the 3D manufacturing flow. Hierarchical test capability simplifies test development and debugging, reduces test time, and allows high coverage even for complex chips that might be limited by I/O pin count, or, in the case of 3D-ICs, inter-die test paths. Integrating automatic test pattern generation (ATPG), compression and (built-in self-test) BIST techniques provides the highest test coverage at the lowest cost. Solving the 3D-IC Test Access Problem The Tessent tool suite supports IMEC (the European microelectronics research center) extensions to IEEE1149.1 allowing unique 3D-IC architectural elements to be added. This enables test patterns to be routed from the bottom die, to the die above via a test elevator. The test elevator is an implementation of TSVs for die to die test access. Tessent tools re-sequence patterns to ensure correct pattern distribution and application across multiple die. The appropriate control patterns are generated to manage bypass logic and patterns are resequenced to account for retiming elements placed on die interconnect. For logic-memory stacks, Tessent MemoryBIST creates BIST logic to fully test stacked DRAM. The MBIST control logic is on the logic chip, maximizing real estate for memory cells, and allowing at-speed testing of the memory bus logic and connecting TSVs. Tessent also supports post-silicon reprogramming of the BIST patterns to accommodate changes in the memory die, or variant stacks that use different memory designs. The product also supports shared bus configurations where multiple memory die are connected to a processor core on the logic die via the same electrical interconnects, for example, TSVs extending through multiple memory die. To fully test TSV connections between logic die, Tessent SoCScan and Tessent FastScan work together to implement a hierarchical test approach. Scan chain test patterns on one die provide stimuli and capture results from another die, thereby testing the integrity of interface logic and TSV connections. All test data is applied through package connections on the bottom dieno connections to upper stacked die are required. Learn more at Mentor session: Tessent Support for 3D IC Testing, Booth #1542 Email: Steve_Pateras@mentor.com White paper at http://www.mentor.com/products/silicon-ield/techpubs/download?id=66946
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Micro Magic (Booth #2917)
MICRO MAGICS MAX-3D FOR PHYSICAL DESIGN OF 3D TSV CHIPS The worlds only transistor-level layout tool for TSV designs. Production-proven, with commercial tape-outs. Many updates and enhancements since MAX-3Ds introduction in 2007.
Datasheet available here: http://www.micromagic.com/tools/MAX-3D.html MAX-3Ds Unique Capabilities: Combine distinct process wafers, and allows the designer to view, edit and connect the independent wafers into one 3D stack chip. Each wafer maintains its own tech file throughout the design process. The TSV interconnect also maintains an independent tech file. Combines, edits, and traces connectivity for the entire design. Direct integration with leading LVS and DRC tools. MAX-3D Speed and Capacity for Large, Complex 3D Designs The size and complexity of a 3D chip design will exceed the capacity of other layout editors severely restricting designer productivity. MAX-3D has the proven ability to handle multiple wafer levels, layers, devices and connections. Integrates with Your Tool Flow Individual wafer levels may be designed by separate design teams, and combined using MAX-3D. For example, a processor design in a 32 nm technology could be combined with a 65 nm memory and a 180 nm Analog device on the same 3D chip. Furthermore, no changes need to be made to the foundry-supplied PDKs to incorporate these technologies in MAX-3D. Full OpenAccess compliance ensures that your design data is interoperable with industry-leading design tools.
See MAX-3D at DAC: Booth # 2917 Mark Mangum, 408-414-7607 | Email: markm@micromagic.com
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R3Logic (Booth #1607)
R3INTEGRATOR: THE 3D PATHFINDING TOOL THAT PLUGS INTO YOUR EXISTING FLOW The 3D EDA Company Winner of the Frost & Sullivan 2011 North American EDA Tools for 3D IC New Product Innovation Award Designing in three dimensions looks a lot easier than it actually is. Most people who have done it will attest to the fact that one can design 3D systems by patching current 2D tools with scripts and hacks but, in the words of one veteran 3D designer, it is like repairing your car with chewing gum and scotch tape. There are so many possibilities for configuring a 3D stack and so many ways of combining different die technologies that a true-3D tool must be stack technology independent and not require hacking existing 2D PDKs or libraries. The fact is that existing tools can already almost do the job. R3Integrator, working within an OpenAccess framework gracefully fills the gaps that current 2D tools cant or dont do well.
Features
Automated TSV placement Optimize Signal-Pin Placement and 3D TSV Assignments Congestion Visualization Route 3D Metallization 3D Netlist Extraction & Connectivity Tracing Integrated 3D Layout Editing Multiple Die Technologies Multiple Stack Topologies Command-Driven Scriptable API (TCL-based) OpenAccess Database Plug-and-Play with Standard 2D Flows Integrate Package Data for Full System CoDesign Embedded 3D Viewer
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Ease of IP Re-Use and Re-Configuration To convincingly predict a cost and / or performance benefit to 3D chip implementation, a 3D pathfinding tool has to be able to dive deep enough into the physical design of the stack so that one can have confidence in its predictions. R3Integrator lets the designer have full flexibility to find the sweet spots in the design space by choosing both the tier placement and the IP library for each system component. It then partitions the system architecture accordingly, so that 2D synthesis tools can complete the tier physical design. It is easy to create a new stack configuration or modify the 3D via structure by changing the external 3D technology file.
TSV Planning and Assignment TSV planning and assignment is crucial in a 3D pathfinding tool because even slight changes in functional block placement on one tier can lead to significant cost increases by impacting cell placements on other tiers. R3Integrator will automatically place and assign 3D interconnects based on the designers constraints, whether to minimize footprint, number of routing layers, or IR drops. Multi-Grid Routing The use of multiple disparate technologies also implies multiple disparate manufacturing grids, and hence, for true inter-tier co-design to take place, multiple routing strategies are needed. R3Integrator implements both PCB-style escape routing as well as traditional channel routing algorithms to optimize area and minimize cost.
Be sure to visit R3Logic at booth: # 1607 Ask for Lisa, Patrick or Olivier Or contact us at info@r3logic.com www.r3logic.com
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Sigrity (Booth #2525)
ADVANCED ANALYSIS SOLUTIONS ENSURING POWER & SIGNAL INTEGRITY IN CHIPS, PACKAGES, AND BOARDS. PHYSICAL DESIGN FOR 3D-IC & COMPLEX IC PACKAGES Key Features and Benefits of Sigrity Products OrbitIO Provides multi-substrate design planning of die, interposers, packages, and pcb enabling the development and optimization of device placement and connectivity in context of the full system. It supports the planning and development of 2.5D systems utilizing interposers with thru-silicon-vias (TSV), stacked 3DICs, as well as traditional SiP packaging in stacked or flat configurations. Its unified environment provides simultaneous interaction and visibility of all substrates within the system with the ability to implement and propagate changes across substrates and immediately evaluate their impact. The codesign environment of OrbitIO can utilize best-available data to start at a high level of abstraction to enable early planning then incorporate detailed content as the design moves toward physical implementation. OrbitIO facilitates IO pad ring development, die placement, bump pattern generation, TSV placement and RDL routing. Design data is managed on an individual substrate basis and is brought together via Orbits hierarchy management to establish device relationships to produce the top-level placement and net list. Automated net mapping manages differences in net name syntax between substrates while connectively optimization can be driven from the die (top-down), pcb (bottom-up), or take place in a true concurrent fashion (middle-out). OrbitIO is easily incorporated into design flows using industry standard data formats and includes a robust API for scripting and customization.
Die Slice 1 TS V
Die Slice 2
Interpose r BGA PCB
Device hierarchy display of 2.5D design with interposer in OrbitIO Key features of OrbitIO for Interposer and 3DIC Design Multi substrate capable - simultaneously view and interact with all substrates within one tool Automated rules-driven IO pad ring development Device placement and stack-up definition Automatic RDL routing with interactive editing Highly adaptable bump pattern construction and editing Platform for design reuse and technology exploration Automated net mapping for net syntax correlation across the system TSV placement and optimization
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Unified Package Designer (UPD) Provides for the physical design of a wide variety of semiconductor packaging formats including; stacked-die, package-on-package (PoP), package-in-package (PiP), wafer level chip scale packages (WLCSP), and interposers with thru-silicon vias (TSV). Its a constraint-driven system that enforces a correct by construction methodology with the objective of producing manufacturing-ready outputs. UPDs package-specific architecture expedites the design process while integrated analysis engines provide insight into electrical performance. UPD integrates with a number of IC and packaging tools through use of standard and proprietary formats as well as produce manufacturing output in DXF, GDSII, Gerber, AIF, OLP, and ASCII formats. XcitePI XcitePI provides IO and power delivery electrical models for all chips. It also provides a chip-centric cosimulation environment for time domain (transient waveforms) and frequency domain (impedance) to characterize chip/package/board systems. TSVs are simply another object to XcitePI, therefore it addresses die, interposers and 3DICs equally well. XcitePI can also provide early die power models to support package power design in parallel with chip flows. A wizard-driven interface is applied to generate such pre-layout models before GDSII or LEF/DEF information is available. All XcitePI electrical models can be used in 3DIC system simulations, including projects with stacked die and implementations with silicon interposers. XcitePI electrical models for core power and IO (signals and power) are applied for both early and verification simulations. XcitePI supports automated connection amongst chip, package and board electrical models with hundreds, or even thousands, of pins through application of industry-standard protocols. All XcitePI electrical models are SPICE compatible. This includes spatially distributed RLCK models for interposers and die IO/power models for ICs and 3DICs, which include both passive RLCK networks for the passive portion as well as transient current sources to represent switching activity in the silicon. XcitePI accurately includes inductance, mutual inductance and skin effect loss effects. TSVs include all relevant effects, including: inductance, mutual inductance and capacitance. Because of their conceptual similarity to SiP packages, design of interposers is supported uniquely well through postprocessing and display technology leveraged from XtractIM, Sigritys package extraction/design software.
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XtractIM and SpeedXP Suite Sigrity provides a set of products integrated with XcitePI to enable package and system cosimulation and electrical model extraction. XtractIM provides electrical model extraction and performance assessment for IC packages. It is at least an order of magnitude faster than classical package extraction methodologies with the same level of accuracy. It has the capacity to address per-net or per-pin electrical models for whole packages with pin counts over 10,000. Many intuitive displays of results assist package design flows uniquely well. SpeedXP Suite includes individual products, such as PowerSI, Speed2000 and PowerDC. These various products address system-level simulation and model extraction. Capabilities include PCB as well as package characterization, both frequency and time domains system cosimulation and DC as well as high-frequency simulation. TSMC Reference Flow Sigrity has been actively working with TSMC on their project to facilitate 3D-IC and 2.5D silicon interposer design enablement. Goals of the work with TSMC are achieving higher performance, reduced power and a smaller form factor. Sigrity products included in the TSMC Reference flow include: XcitePI, OrbitIO, XtractIM, PowerSI and OptimizePI.
There will be more at the Sigritys DAC booth and suites: #2525 Also feel free to us for additional information on 3D-IC: Leslie Landers, Tel (408) 688-0145 x148 email: leslie@sigrity.com www.sigrity.com.com
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Synopsys (Booth #3433)
OVERVIEW OF 3D CAPABLE TOOLS
Overview of 3D capable tools Tools to create models for dieto-die interconnect (e.g. TSVs) Tools for 3D-aware implementation
Tools for 3D-aware analysis and verification
Key 3D design steps TSV device modeling for mechanical stress, thermal interaction and electrical analysis Multi-die bump and TSV floorplanning, chip-package interface, multi-die aware DFT and compression, TSV-aware place and route, RDL routing Parasitic extraction of inter-die interconnect, TSVs, microbumps, interposer; multi-die timing and IRdrop analysis; TSV-aware stack DRC/LVS; multi-technology circuit simulation
Product Names Sentaurus Interconnect
Design Compiler DFTMAX IC Compiler
StarRC PrimeTime PrimeRail IC Validator HSPICE
Synopsys 3D-IC Design Flow

TSV Modeling
Sentaurus Interconnect Thermo-mechanical stress analysis Electrical variation
Mfg.
Synthesis & Design-for-Test

3D-IC Design & Verification
Design Compiler/DFTMAX TSV connectivity checking with JTAG Test compression

IC Compiler Multi-die bump & TSV floorplanning TSV-aware place & route RDL routing
Physical Design Parasitic Extraction Circuit Simulation Stack Analysis/Sign-off
StarRC TSV, microbump, RDL metal extraction
HSPICE Multi-technology analysis
IC Validator, PrimeTime Inter-die timing analysis TSV-aware stack DRC/LVS
More about Synopsys 3D-IC solution at booth: #3433 Ask for Steve Smith | Email: ssmith@synopsys.com www.synopsys.com
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R&D CENTERS & INDUSTRY ORGANIZATIONS
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CEA-LETI
CEA-LETIS HOLISTIC APPROACH TOWARDS 3D CIRCUIT DESIGN AND FABRICATION By Alexandre Valentian, David Henry, Denis Dutoit and Arnaud Verdant CEA-LETI, MINATEC Campus, Grenoble, FRANCE | www-leti.cea.fr The 3D research field is now mature enough so that it is pointless to state the numerous potential advantages tied to 3D circuits, whether it deals with power, performance or cost. However, for companies willing to enter this field and market in the future , a lot of questions remain open: what about prototype fabrication? Or even pre-fabrication pilot lines? Will the target performance be achieved? What design flow should I use? To answer those questions and simultaneously speed up 3D technology adoption by industry, CEA-LETI is tackling those issues on two fronts: (1) On the one hand, it will offer an open 3D fabrication service, called Open 3D, in which customers will have access to low-cost, mature 3D technologies in order to make proof-of-concept prototypes and even small volume production. (2) On the other hand, CEA-LETI has engaged in a number of joint laboratories with leading EDA partners to collectively define a complete 3D design flow, from systempartitioning to 3D physical implementation and stack thermal analysis. Open 3D initiative @ LETI The Open 3D initiative is a new concept proposed by CEA-LETI in 2011. The aim is to offer a one-stop shop 3D fabrication service dedicated to industrial partners or universities, in order to manufacture prototypes and/or go towards small volume production (Fig. 1). Based on our customers needs, Open 3D will eventually provide a global 3D offer, including design, layout, 3D technological steps, reliability tests and final packaging. This offer is based on a limited set of mature technologies in order to ensure low prices, short cycle time and good results. Open 3D will be compatible with 200 & 300 mm substrates. Those technologies will be operated on CEA-LETIs technological platforms, leveraging the expertise of our operation, process, metrology, characterization and maintenance teams (Fig. 2).
Fig. 1 Schematic view of Open 3D offer
Fig. 2 CEA-LETI technological platforms
The starting technological catalogue will include the following technological modules: Through Silicon Vias (TSV) with aspect ratios of 1:1 and 1:2 (Fig. 3a); Interconnections for chips to wafers (Fig. 3b); Interconnections for chips to substrates; Redistribution layers (RDL) (Fig. 3c); Temporary bonding, thinning and debonding; Components stacking and underfilling (Fig. 3d). This catalogue will be regularly enriched with new modules in the future.
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Fig. 3a TSV AR 2:1
Fig. 3b Interconnections
Fig. 3c RDL
Fig. 3d Chips stacking
The Open 3D Initiative will start at CEA-LETI in 2011 and the objective is to be fully operational in the beginning of 2012. Contact: David Henry, david.henry@cea.fr Overview of the 3D Design Flow Being Nurtured Under CEA-LETIs Umbrella Despite of its many advantages, the other side of the coin of 3D TSV technology is that it adds a great deal of complexity to the chip design itself. The design space becomes huge, requiring chip architects to decide how many tiers will be used, which technology on which tier, what TSV pitch, what interconnect between tiers (Cu pillars, molecular bonding) and so on. Faced with too many choices, chip designers need the help of dedicated EDA tools currently being developed. CEA-LETI has brought together several of these tools, by engaging in joint labs with leading EDA partners like Atrenta, R3Logic and Docea Power, to help define a comprehensive 3D Design Flow (Fig. 4). This flow allows us to do early architecture Techno information partitioning, stack definition (also System Architects Early RTL known as 3D Pathfinding), concurrent & 3D Stack definition Atrenta floorplanning, TSV placement, and Black Box Models - Multiple techno nodes - Die partitioning thermal analysis. The various parts of - Architecture exploration this flow are described below. - Simultaneous floorplan &
3D System (circuit & package) co-design flow co-design flow co-design flow
i e e ec Sp
floorplan Prototyping Tool Definition and guidance State of the Art 3D Stack/Package analysis & The prototyping tool for integrated optimization: circuit design addresses architectural - Early floorplan & R3Logic exploration during the definition and TSV Placement 3D Handoff - 3D Thermal Profile & feasibility phases of a design. This tool power analysis Docea Implementation enables evaluation and comparison of - Test Presto guidance Clean RTL several architectures in terms of cost, processing performance and power 3D Implementation consumption without going up to the - 3D Floorplan finishing physical implementation. The iteration - Power planning - 2D Place & CTS & Route time required by this architectural - 3D analysis (power/timing) exploration remains compatible with the time assigned for the definition Fig. 4 Overview of the 3D design flow and feasibility phases of an integrated circuit design. Finally, this prototyping tool brings guidance to the users which will facilitate the design-execution process.
To this aim, CEA-LETI has engaged in a joint laboratory with Atrenta. The collaboration is centered on the SpyGlass-Physical Atrenta design tool. This tool analyzes the architectural and micro-architectural compromises by comparing Key Performance Indicators of various solutions: their area, power consumption, signal propagation time, and interconnect congestion. It also evaluates multiple floorplan configurations, analyzes implementation feasibility, enables appropriate IP selection, creates physical partitions and generates implementation guidance for IP and SoC implementation. The tool, used by System-on-Chip architects, does not require expertise in physical implementation.
RTL Design Flow RTL Design Flow RTL Design Flow
s: a a am , , , Te al d d ed m er ity l liz i i al T e Th e r , T teg n n In ng In rin l I d na n n P i P i Pa Sig
TSV location exploration
Package and
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This prototyping tool is currently being expanded towards 3D technology (Fig. 5), with the aim of displaying the following functionalities: Evaluation of different 3D stack configurations: assembly options between front-to-front and front-toback, technology node per die, TSV density, interposer choice, RDL needs; Exploration of different architectures: IP partitioning among tiers, memory partitioning, memory-to-logic interface explorations; Simultaneous floorplan optimization across tiers to determine the feasible location for TSV structures; Partitioning the 3D structure to multiple independent 2D designs to guide down-stream implementation and to leverage the existing 2D tools and design flows.
Early RTL & Black Box Models Techno information SoC Architects
Partitioned RTL & Black Box Models
Fig. 5 3D prototyping design tool
Bridging to 3D physical implementation This early stack and floorplan definition gives system architects enough confidence that design closure is within reach. It will then serve as guidance to 3D physical implementation tools, like R3Integrator from R3Logic, the first tool of its class with true 3D design capabilities (Fig. 6). R3Logic is another EDA company with which CEALETI has engaged in a joint laboratory. The centerpiece of R3Integrator is its 3D partitioner/floorplanner that adds spatial awareness to system prototyping tools. The initial coarse system partitioning, which was based on black boxes and RTL models, can now be refined with placed-and-routed functional blocks. If needed, the system design can be quickly reconfigured. It is worth noting that, up to now, 3D test chips in various research institutions were made using standard 2D EDA tools and a workaround survivor kit, composed of various scripts. In this respect, the very first salient feature brought by a true 3D EDA tool is technology independence, i.e. a chip designer can load any number of design kits and 3D technology add-ons: the resulting 3D design kit is clean, and is obtained without renaming foundry-provided design kits, which is always a risky business. The second salient feature of such a tool is 3D hierarchy: it understands that a function may be split into multiple tiers, in different technologies. This feature is especially important for (1) maximizing IP reuse one of the advantages of going 3D , and (2) co-designing the entire stack, in order to reduce the number of design re-spins. It is very convenient to stack proven 2D IPs and check whether pin placement is correct or not with R3Integrator. Often, a pin swapping will be necessary. Thermal-Aware Architecture Exploration and Design The simulation flow proposed by Docea Power with the Aceplorer tool allows the evaluation of different power strategies. The tool proposes an exploration of three facets that are properly captured at architectural level and separate: the power model, the thermal model and the application model, a.k.a. the scenarios (Fig. 7). The power model of the architecture consists in describing its different components and the power and clock distribution networks that connect them. A set of power states is defined for each component, depending on the supplied voltages and frequencies and on the requested activity. This way, standard low power methods like clock gating, power gating and dynamic voltage and frequency scaling can be modeled and simulated. Leakage and dynamic current descriptions can be split to enable a fine analysis of the power behavior. The overall modeling technique is very flexible to cope with the heterogeneity that can be found in complex systems mixing numerous digital and analog blocks.
RTL Design Flow RTL Design Flow
3D Stack Design Flow
3D Stack definition
Atrenta
Technology nodes and assembly options evaluation Architecture and IP partitioning Simultaneous floorplan and TSV location optimization
3D stack configuration and floorplan guidance
Fig. 6 3D physical implementation flow
Fig. 7 The Aceplorer simulation flow
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The thermal model describes for each component its thermal interaction with its environment (other component, package, etc.) through simple thermal resistors and capacitors. It is derived from data available in the design flow (the floorplanning, the layout and technology properties). Finally, different transient scenarios that specify the power states of the components at different steps can be run. These scenarios represent how the applications activate the various components of the system. The solver thus provides the transient power consumption for each component and its thermal behavior over the application time. 3D stacking leading to hard constraints concerning power dissipation, there is a need for thermally-oriented 3D architectural exploration. The Aceplorer exploration tool must then be completed according to the 3D technology specificities: Power and thermal modeling of TSVs and RDLs (average-lengths calculations) Compact thermal modeling of substrate with different densities of TSVs Compact thermal modeling of capping and 3D integration at the packaging level Such a tool will especially allow simulating the impact of blocks positioning of stacked wafer on temperature budgets and provide an early 3D floorplanning for IR drop estimation. Moreover, it will allow estimating the additional cost of glue logic in 3D architectures (from thermal and power points of view). Conclusion CEA-LETI is about to open a 3D technology service called Open 3D to make industrial partners and universities benefit from its strong technological expertise. This service, to be fully operational in 2012, will offer a portfolio of mature technologies, to keep the cost down and at the same time ensure good quality and short cycle time. Open 3D is dedicated to prototype fabrication and small volume, pre-production runs. This offer will eventually be expanded to include additional services like design, layout, reliability test and packaging. At the same time, CEA-LETI is focused on shaping a comprehensive 3D Design Flow, by engaging in collaborations with leading EDA partners. The entry point of this flow is a high-level system partitioning tool. Dedicated to system architects, this tool helps reduce the solution space from a set of black boxes and RTL models, and a set of constraints. Then this initial partitioning and stack definition can be refined using a 3D physical implementation tool: this tool helps finalize the floorplan and stack definition by automatically placing TSVs, swapping macro-block pins, etc. It is then used to finalize the physical implementation, legalizing TSVs, placing copper pillars or another die-todie interconnect and routing the RDL layer. In parallel, the 3D chip can be thermally analyzed throughout the design phases in order, for instance, to avoid stacking local hot spots on top of each other. Since this tool does concurrent power and thermal analyses two sides of the same coin it will also be used to estimate IR drop in the given 3D stack.
Contact: Alexandre Valentian, alexandre.valentian@cea.fr
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SEMATECH
SEMATECH is an international consortium of leading semiconductor manufacturers that conducts state-of-the-art research and development to accelerate the commercialization of technology innovations into manufacturing solutions. SEMATECH manages cross-industry pre-competitive collaborative efforts by bringing chipmakers, equipment and materials suppliers, and assembly and packaging service companies together to share costs and risk and to solve common technical and manufacturing challenges. SEMATECHs advanced technology programs focus on EUV and alternative lithography, 3D interconnects, and next-generation transistors, materials, and metrology.
SEMATECHs 3D Interconnect Program By using strengths developed over its 20-year history in organization, technology assessment, and benchmarking, SEMATECH has built its 3D Interconnect program to solve the challenges of 3D-TSV by:
Driving industry consensus on integration approaches, process architectures, and tool sets Increasing knowledge of process flow costs and product dependencies Developing mature specific unit processes Creating a roadmap and driving for standards
SEMATECHs 3D program consists of three components: Unit Process Development (UPD), Integration, and 3D Enablement Center: Unit Process Development This project focuses on demonstrating the manufacturability of the various process modules required to implement 3D-IC stacking, with a focus on 5x50 micron via-mid TSV. These process modules include TSV fabrication (etch, liner/barrier/seed, plating, CMP); wafer-to-wafer and die-to-wafer aligning/bonding, including both temporary and permanent bonding, wafer backgrinding and final thinning, and 3D metrology. Integration This project uses test vehicles to demonstrate the integration of the 3D unit processes and evaluate TSV and bonding electrical characteristics, yield, and early reliability. 3D Enablement Center SEMATECH has teamed with the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC) to establish the 3D Enablement Center to enable industry-wide ecosystem readiness for costeffective TSV-based stacked IC solutions. Its initial focus is on facilitating industry-wide standards and specifications. Membership is open to fabless, fab-lite and IDM companies, outsourced assembly and test (OSAT) suppliers, and others, including EDA and tool vendors.
To learn more about SEMATECH's 3D Interconnect program, contact 3DInterconnect@sematech.org
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SEMI
3DS-IC STANDARDIZATION UNDERWAY AT SEMI Three-dimensional Stacked Integrated Circuits The first 3DS-IC SEMI Standards Committee was formed in North America late last year. Soon after, activities were organized into three Task Forces (TFs): Thin Wafer Handling, Bonded Wafer Stacks, and Inspection and Metrology. After a kick-off meeting in January, the 3DS-IC committee met again during the recent North America Standards Spring 2011 meetings and made further progress in targeting the Committees initial priorities. The Thin Wafer Handling TF aims to develop standards for reliable handling and shipping of thin wafers and dies (e.g., micro-pillar grid arrays, or MPGA) used in high-volume manufacturing. As part of this effort the TF will define thin wafer handling requirements including physical interfaces used in 3DS-IC manufacturing, as well as shipping requirements, including packaging, reliability, and other relevant criteria for both thin wafers and MPGAs. The TFs first effort is a guide for multi-wafer transport and storage containers for thin wafers. Current standards for shipping boxes, FOUPs, and FOSBs are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3DS-IC manufacturing. Wafer thicknesses of 30-200 m will need significant changes to the current design criteria of current wafer transport and storage containers. This document will include specifications for tape frames, thin wafers on tape frames, container capacity requirements, and transportation/vibration and mechanical shock requirements. The Inspection and Metrology TF is working on standards to be used in measuring the properties of TSVs, bonded wafer stacks, and dies used in 3DS-IC manufacturing. Specific areas that have been identified to be in need of inspection and metrology standards include TSV physical properties (depth, top, bottom critical dimensions, side wall, etc.) and bonded wafer stack properties (overlay, bond inspection). The TF will initially focus on the physical parameters of TSVs. Multiple different technologies exist for measuring various physical parameters of a single TSV or arrays of TSVs, such as pitch, top critical dimensions, top area, depth, and taper. However, currently it is difficult to compare measurements from the various technologies, as in some cases parameters are called by similar names but are different aspects of the same measurement. This standard will group the various technologies and allow for valid correlations and comparisons. Still, there are other TSV parameters that the TF also plans to address. Additional candidates for standardization include whole wafer damage inspection (crack, break, etc.) at the macro level as well as inspection at the micro level (microbump, pad, etc.). The TF is working on a process flow map that identifies known, as well as potential, areas for metrology, and all members are encourage to identify areas where they can contribute. The Bonded Wafer Stacks TF has two activities underway. The first is a specification for parameters, as existing wafer standards (such as SEMI M1: Specification for Polished Single Crystal Silicon Wafers) do not adequately address the needs of wafers used in bonded wafer stacks. Wafer thickness, edge bevel, notch, mass, bow, warp and diameters are changed when wafer stacks are bonded together, or when wafer stacks are bonded and thinned. These deviations from wafer parameters specified in SEMI M1 have numerous impacts in other equipment and hardware standards that reference SEMI M1, and are the motivation for a new standard to reflect wafer parameters associated with bonded and bonded/thinned wafer stacks. This activity will include both silicon and glass carrier wafers.
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Similarly, the wafer identification and marking needs of bonded wafer stacks are not covered by current standards. Locations currently used for ID marking (such as backside near notch in SEMI T7: Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol) will be removed during backside thinning operations or edge-trim operations, or buried under an opaque layer of silicon and rendered unreadable by optical readers when bonded. Multiple wafer stacks will combine wafers with multiple process history, including tracking of temporary carrier wafers, and a standard needs to be developed to combine and track bonded wafer stacks with multiple wafer histories. Lastly, an additional new task force is being formed to work on standards for dimensions and sizes of carrier wafers as well as edge trimming of device wafers. The output of this task force will be used in the development of the bonded wafer stacks specification by the Bonded Wafer Stacks TF. The above activities are just the beginning of what promises to be a global, industry-wide effort. Over 125 technologists from industry, research institutes, and academia around the world have already joined the SEMI 3DS-IC Standards Committee and are at work on these critical standards. The committee and task force will next be meeting at SEMICON West 2011 in July, and the Standards Program will also present a 3DS-IC Workshop to introduce the development and commercialization status of key aspects of TSV manufacturing and TSV integration. About the SEMI Standards Program The SEMI International Standards Program, established in 1973, brings experts from the microelectronic, display, photovoltaic, and related industries together to exchange ideas and develop globally-accepted technical standards. Published standards include specifications, test methods, terminologies and safety guidelines. Over 3,500 technologists representing more than 700 companies work in 23 global technical committees and over 200 task forces. The resulting SEMI Standards contribute to increased manufacturing efficiency and faster time-to-market, especially for new and emerging technologies, and have enabled the efficient proliferation of global wafer fab development, saving advanced manufacturing industries billions of dollars. Participation in the SEMI Standards Program is free, but requires registration. To learn more, please visit: www.semi.org/standards. The SEMI Standards Membership Application From is available at: www.semi.org/standardsmembership.
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Si2 (Booth #1631)
OPEN3D PROJECT SUMMARY OVERVIEW: INTEROPERABILITY FOR 3D STACKED DIE DESIGN FLOWS The 3D project at Si2, named Open3D Technical Advisory Board (TAB), is chartered to develop standards to: Define the necessary formats / interfaces / APIs to enable the transfer and sharing of design and model data throughout 3D-IC design flows Enable the transfer of required design data from the 3D-IC design system to package design systems for the design of packages for the 3D ICs
Open3D Project Approach Stage project over multiple phases, focusing on most urgent items first: Phase 1: Design exchange formats / APIs and sub-flows Examples include formats for: 3D partitioning and floorplanning information for design of tiers Tier-2-tier constraints due to thermal distribution, mechanical stress, exclusion zones for bumps, etc. Phase 2: Model exchange formats / APIs and sub-flows Examples include formats for electrical, thermal / mechanical stress models, etc. Phase 3: Format / API standards for full 3D design flows Include 3D project member companies and domain experts from academia Open3D Kick-off Meeting @ DAC Date: Tuesday, June 07, 2011 Time: 01:00PM 03:00PM, Pacific Time Room: 24A Attendance: By invitation only Contacts: Bob Carver / Phone: 512-801-4350 / Email: bobc@si2.org Sumit DasGupta / Phone: 512-342-2244, x-301 / Email: dasgupta@si2.org
Si2 Booth at DAC: #1631
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VALUE-CHAIN PRODUCER
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eSilicon
eSilicon is a Value Chain Producer, according to GSAs definition. The company produces chips for other companies, including OEMs and fabless semiconductor suppliers. It has expertise in design and manufacturing across a broad range of technologies and uses multiple suppliers, both fabs and outsourced assembly and test houses (OSATs). Because of its strong connection to the end silicon, eSilicon manages yield and design for manufacturability and ensures that its customers' products are cost-effective and high quality, as well as making sure their designs are optimized and right the first time. Figure 1 shows the different tasks eSilicon can perform and the different paths to production its customers can take. Customers automatically get everything below that level, no matter what level they come in.
Fig. 1 3D-IC and its potential to deliver More than Moore is of interest to the majority of the industry, especially to companies whose volumes (or the certainty of achieving them) make it tough to justify a high NRE typically several million dollars in a leading-edge technology node. 3D chips also offer the promise of being able to combine heterogeneous technologies for example, using 28nm for a standard microprocessor-based subsystem (which can be re-used in multiple designs), while using a more mature 65nm process with a much lower NRE for the customized portion of the logic, and 130nm for a mixed-signal function. There are different needs and reasons for the interest in 3D in different application areas. For example, the mobile space is driven mostly by the potential benefits of reduced power and space. The comms infrastructure and networking space however, is driven by yield improvement and the ability to insert more memory than would be possible using monolithic devices. Increasingly, companies in this space are also interested in the
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lower-power benefits as well. Mobile devices need thin architectures and need to meet very thin package thicknesses. On the other hand, larger networking devices require thicker 3D ICs or interposers in order to handle the flatness needed for larger die and side-by-side architectures of the devices.
Tiles such as logic, FPGA, memory-stacks, IPD, etc. Microbumps Active die with TSV Bumps
Organic Laminate
Balls
Fig. 2: 3D-IC Concept
When it comes to readiness, eSilicon believes that the industry is not ready for full 3D-IC production today. Thru-silicon vias (TSVs), the enabling technology for 3D-ICs, must be inserted into silicon containing active circuitry. This needs to be done without compromising long-term reliability, and the issues associated with this have not yet been fully resolved. However, there has been a lot of progress over the last 12 months and for anyone planning a chip for volume production after 2013, its time to start considering the benefits of using 3DIC technology. More significantly, the so-called 2.5D approach using silicon interposers is ready now. A 2.5D-based product uses a piece of passive silicon called an interposer to act like a miniature PCB, onto which other chips are placed (Fig. 3). As the interposer consists solely of passive silicon, there are no worries about the TSVs compromising the long-term reliability of the active circuitry. eSilicons approach uses a standardized form of interposer and builds Tiles of active silicon on top.
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Tiles such as logic, FPGA, memory-stacks, IPD, etc.

Microbumps Passive Silicon Interposer
Bumps
Organic Laminate
Balls
Fig. 3: 2.5D Concept eSilicon will be building a library of the Tiles that form the basis of the 2.5D approach, both by itself and with IP partners. Tiles will include functions such as: Microprocessor sub-systems Memory FPGAs High-performance PHY functions High-performance analog functions such as ADCs and DACs The use of FPGAs as a Tile makes a prototype system easy to build. The customer can use the FPGA to create any custom logic required by the system, plus connecting functions on other Tiles. Then for production, as shown in Figure 4, the design can adopt one of three possible paths, depending on volume certainty: 1. Stay with an FPGA-based solution if the costs are acceptable 2. Convert the FPGA to an ASIC, without having to alter any of the existing Tiles 3. Move to a full ASIC if the volume is proven to make the tradeoff of paying a full leading-edge NRE worthwhile
60

28nm uP core and cache tile High-density FPGA logic tile Memory tile High-perf 40nm PHY tile
Proto and low volume: SIP FPGA approach
65nm silicon interposer: Passive interconnect only
Medium volume: SIP ASIC approach

28nm uP core and cache tile ASIC tile Memory tile High-perf 40nm PHY tile
High volume: Full SoC approach Customer System

Cust. Blks Cust. Blks
Subsystem
uP core
65nm silicon interposer: Passive interconnect only

Fig. 4: Routes to Production eSilicon is connected to all aspects of the semiconductor supply chain; fabs, test and assembly companies, EDA companies and design houses. We are therefore in a good position to assess the readiness of the industry for 3D packaging as a whole and help customers interested in doing first projects to make the right decisions. eSilicon will manage the entire supply chain for its customers using the fabs and OSATs that are ready for 2.5D and 3D ICs. eSilicon is currently working on its first 2.5D project and expects to tape out an interposer-based SIP device before the end of 2011.
Contact info: info@esilicon.com 877-769-2447 www.esilicon.com
61
The Global Semiconductor Alliance (GSA) mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP , EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 25 countries across the globe.
GSA Member Benefits Include:
Access to Profile Directories Ecosystem Portals IP ROI Calculator IP Ecosystem Tool Suite Global Semiconductor Funding, IPO and
M&A Update
Discounts on various reports and publications including:
Wafer Fabrication & Back-End Pricing Reports Understanding Fabless IC Technology Book IC Foundry Almanac, 2011 Edition
Global Exposure Opportunities:
Global Semiconductor Financial Tracker End Markets Tool MS/RF PDK Checklist AMS/RF Process Checklist MS/RF SPICE Model Checklist Collaborative Innovation Study with the
Wharton School
Advertising Sponsorships Member Press Section on GSA Web site Company Index Listing on Ecosystem Portals Member Spotlight on GSA Web site
12400 Coit Road, Suite 650 | Dallas, TX 75251 | 888-322-5195 | T 972-866-7579 | F 972-239-2292 | www.gsaglobal.org

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3D-IC DESIGN TOOLS & SERVICES TOUR GUIDE

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Package on Package PoP

System in Package SiP

Interposer with 2 or more die 2.5D

Vertically stacked die with TSVs 3D

Latency Bandwidth Package Height

All on chip Ext. Memory All on chip Ext. Memory

Table 1. Technology Alternatives and Trade-offs

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Fig. 2. Combination of four FPGAs Xilinx introduced in Fall 2010

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Download an electronic copy of this report at: http://www.gsaglobal.org/eco/index.aspx?tab=8#eda_pres

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Source: TechSearch International, Inc.

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OVERVIEW OF DEDICATED 3D CAPABLE TOOLS:

Product Names Chip Power Model, RedHawk RedHawk

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Fig. 1. Overall design flow

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Fig. 4. Inter die connectivity

Fig. 5. Compact thermal model

For more information, contact: Brad Nold, nold@atrenta.com

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