IVY BRIDGE

A Paper on

22nm processor

Authors:

V.Naveen III/IV B-Tech(ECE) 09481A04B1 No:9533408084 Mail:prince111naveen@gmail.com

T.Keerthana III/IV B-Tech(ECE) 09481A04A5 No:9502891118 Mail:keerthanatunuguntla@gmail.com

GUDLAVALLERU ENGINEERING COLLEGE SESHADRI RAO KNOWLEDGE VILLAGE

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GUDLAVALLERU
ABSTRACT: Ivy Bridge (IVB) is the first chip to use Intel's 22nm tri-gate transistors, which will help scale frequency and reduce power consumption. Mobile Ivy Bridge will be the first Intel CPU to bring four cores into a 35W TDP. At a high level Ivy Bridge looks a lot like Sandy Bridge. It's still a monolithic die that features an integrated GPU. The entire die is built at 22nm, continuing Intel's march towards truly addressing integrated graphics performance. Ivy Bridge won't get rid of the need for a discrete GPU but, like Sandy Bridge, it is a step in the right direction. The Ivy Bridge chips will be the first to use tri-gate, also called 3D, transistors, which will be up to 37 percent faster and consume less than half the power of 2D transistors on current chips.The chips will be made using the 22-nm process, while current Sandy Bridge microprocessors are made using the 32-nm process. As a result of this new 3D design named Tri-Gate, Intel will be able to produce smaller and faster chips which are going to be widely implemented from servers and desktop computers to laptops, tablets and mobile phones.Going forward in the semiconductor chip scene has been widely known as Moores Law. What this means is that basically every 18 to 24 months the transistors placed on an integrated circuit must inexpensively double.The traditional transistor design consists of just one conducting channel placed on the top of a narrow silicon fin. The for Tri-Gate additional

technology

allows

conducting channels to be formed on all three sides of that fin one is the traditional top, and two on sides. This allows electrons not just to flow on the one, vertical side of the fin, but on all three.

3d transistors:

Computers

with

three-dimensional

transistors - these will incorporate vertical components, unlike the flat chips that we're used to seeing. This structure will allow them to have shorter gates, which are the components that allow the

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transistors to switch the electrical current on and off, and to direct its flow. The shorter the gate( gate length of 22 nanometers), the faster the computer can operate.

Intel's performance targets :

Up to 20% increase in CPU performance. Up to 30% increase in integrated GPU performance.

Motherboard & Chipset Support: Ivy Bridge features:

Tri-gate transistor technology (less than 50% power consumption at the same performance transistors). PCI Express 3.0 support. Max CPU multiplier of 63 (57 for Sandy Bridge). RAM support up to 2800MT/s in 200MHz increments. Intel HD Graphics with DirectX 11, OpenGL 3.1, and OpenCL 1.1 support. The built-in GPU is believed to have up to 16 execution units (EUs), compared to Sandy Bridge's maximum of 12. A new random number generator and the RdRand instruction,[14] which is codenamed Bull level as 2-D planar Ivy Bridge is backwards compatible with existing LGA-1155 motherboards,

although there will be a new chipset for Ivy Bridge and new motherboards to enable some features (e.g. PCI Express 3.0, native USB 3.0). The new chipset family falls under the 7-series banner. Ivy Bridge finally supports USB 3.0 natively. The consumer 7-series chipsets feature 14 total USB ports, 4 of which are USB 3.0 capable. The CPU itself features 16 PCIe (1x16, 2x8 or 1x8 + 2x4) gen 3 lanes to be used for graphics and/or high performance IO.An Ivy Bridge CPU will supply performance similar to that of a Sandy Bridge CPU while consuming less power, and it will offer greater

performance while consuming the same amount of power. That means you'll see laptops that provide better battery life without sacrificing speed, as well as faster desktops that are easier on your utility budget.

Mountain. Intel Quick Sync Video DDR3L low voltage for mobile processors. Multiple 4K video playback.

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In Sandy Bridge Intel did a ground up redesign of its branch predictor. Once again it doesn't make sense to redo it for Ivy Bridge so branch prediction remains the same. In the past prefetchers have stopped at page boundaries since they are physically based. Ivy Bridge lifts this The front end in Ivy Bridge is still 4-wide with support for fusion of both x86 instructions and decoded uOps. The uOp cache introduced in Sandy Bridge remains in Ivy with no major changes. Some structures within the chip are now better optimized for single threaded The number of execution units hasn't changed in Ivy Bridge, but there are some changes here. The FP/integer divider sees another performance gain this round. Ivy Bridge's divider has twice the throughput of the unit in Sandy Bridge. The advantage here shows up mostly in FP workloads as they tend to be more computationally heavy. MOV operations can now take place in the register renaming stage instead of making Ivy Bridge reworks a number of these data structures to dynamically allocate it occupy an execution port. Intel also introduced a number of ISA changes in Ivy Bridge. The ones that stand out the most to me are the inclusion of a very high speed digital random number generator (DRNG) and supervisory mode execution protection (SMEP). Ivy Bridge's DRNG can generate high quality random numbers (standards restriction.

execution. Hyper Threading requires a bunch of partitioning of internal structures (e.g. buffers/queues) to allow instructions from multiple threads to use those structures simultaneously.

resources to threads. Now if there's only a single thread active, these structures will dedicate all resources to servicing that thread. One such example is the DSB queue that serves the uOp cache mentioned above. There's a lookup mechanism for putting uOps into the cache. Those requests are placed into the DSB queue, which used to be split evenly between threads. In Ivy Bridge the DSB queue is allocated dynamically to one or both threads.

compliant) at 2 - 3Gbps. The DRNG is available to both user and OS level code. This will be very important for security and algorithms going forward.

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DDR3L in addition to DDR3, enabling 1.35V memory instead of the standard1.5V DDR3.

From Nehalem to Sandy Bridge, Intel introduced fairly healthy amounts of power gating throughout the processor. With little more to address in Ivy Bridge, Intel power gated one of the last available portions of the die: the DDR3 interface. If there's no external memory activity, the DDR3 interface can now be turned off Cache, Memory Controller & completely. External IOs leak current like any other transistor so this change makes sense. Power gating simply increases die size but at 22nm Intel should have some extra area to spend on things like this. Memory overclocking also gets a bump in Ivy Bridge. The max supported DDR3 frequency in SNB was 2133MHz, Ivy Bridge moves this up to 2800MHz.

Overclocking Changes: There haven't been any changes to Ivy Bridge's cache. The last level cache (L3) is still shared via a ring bus between all cores, the GPU and the system agent. Quad-core Ivy Bridge CPUs will support up to 8MB of L3 cache, and the private L1/L2s haven't increased from their sizes in Sandy Bridge (32+32K/256K). The memory controller also remains relatively unchanged, aside from some additional flexibility. Mobile IVB supports

Power Efficiency Improvements:

When Intel introduced its 22nm tri-gate transistors Intel claimed that it could see

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an 18% increase in performance at 1V compared to its 32nm process. At the same switching speed however, Intel's 22nm transistors can run at 75 - 80% of the voltage of their 32nm counterparts. Ivy Bridge's process alone should account for some pretty significant power savings. In addition to process however, there are a few architectural changes in IVB that will reduce power consumption.

it is specified to run at (e.g. 3.3GHz for a 2500K) and turbo is the highest available turbo frequency (e.g. 3.7GHz for a 2500K). Intel determines the lowest voltage possible for each one of those frequencies. Sandy Bridge obviously runs at more than just three frequencies, there are many more intermediate frequencies that it may run at depending on the current workload. The voltages at those

Lower System Agent Voltages:

Sandy Bridge introduced the System Agent, a name that used to refer to the uncore of a processor but now refers to the display output, memory controller, DMI and PCI Express interfaces. As of Sandy Bridge, the L3 cache was no longer included in the uncore and thus it wasn't a part of the System Agent. The System Agent operates on a separate voltage plane than the rest of the chip. On Ivy Bridge Intel now offers even lower System Agent voltage options for the lower voltage SKUs, which in turn helps power optimize those SKUs.

intermediate frequencies are interpolated from the three points that I mentioned above. With Ivy Bridge, Intel characterizes even more points along the frequency curve. A curve is then fit to the frequency/voltage data and depending on IVB's operating frequency a more accurate voltage point is calculated. The result from all of this seemingly simple work is a reduction in core voltage at these intermediate

frequencies. Voltage changes have a cubic affect on power, so even a small reduction here can have a tangible impact. Ivy Bridge should be more power efficient in cases where you have all cores active.

Voltage Characterization:
Today Intel defines three different voltages for every Sandy Bridge CPU: LFM, nominal and turbo. LFM is the lowest frequency the CPU can run at (e.g. completely idle), nominal is the frequency

Power Aware Interrupt Routing:

Ivy Bridge has logic to properly route interrupt requests to cores that are already awake vs. those that are asleep in their lowest power states. Obviously this

approach can save a lot of power, however

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it may rob those active cores of some performance. IVB will allow prioritizing performance as well. Interrupt handling can thus be handled similarly to how it is today, or optimally for power savings.

the dock.The most interesting are the 17W ULV Ivy Bridge parts .Today you do sacrifice clock speed to get into the form factor of a MacBook Air. A clever OEM armed with Ivy Bridge might be able to deliver a cooling dock that would give you the best of both worlds: an ultra portable chassis on the go, and higher clock speeds while docked.The New GPU Westmere marked a change in the way Intel approached integrated graphics. The GPU was moved onto the CPU package and used an n-1 manufacturing process (45nm when the CPU was 32nm). Performance improved but it still wasn't exactly what we'd call acceptable. Sandy Bridge brought a completely

Configurable TDP:
Ivy Bridge introduces configurable TDP that allows the platform to increase the CPU's TDP if given additional cooling, or decrease the TDP to fit into a smaller form factor.

redesigned GPU core onto the processor die itself. As a co-resident of the CPU, the Aan Ivy Bridge notebook with an optional dock that could enhance the cooling capabilities of the machine. When GPU was treated as somewhat of an equal - both processors were built on the same 32nm process. With Ivy Bridge the GPU remains on die but it grows more than the CPU does this generation. Intel isn't disclosing the die split but there are more execution units this round (16 up from 12 in SNB) so it would appear as if the GPU occupies a greater percentage of the die than it did last generation. It's not near a 50/50 split yet, but it's continued indication that Intel is taking GPU performance seriously.

undocked the notebook's processor would operate at a max TDP of 17W, for example, but toss it in a dock with additional cooling and the TDP would jump up to 33W. It's up to the OEMs to decide how they want to take advantage of this feature. It could be something as simple as a mobile dock with more fans, or something as complex as a modular water cooling solution with a bigger radiator in

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Sandy Bridge, which has implications for both GPU compute and general 3D gaming performance.

The Ivy Bridge GPU adds support for OpenCL 1.1, DirectX 11 and OpenGL 3.1. This will finally bring Intel's GPU feature set on par with AMD's. Ivy also adds three display outputs (up from two in Sandy Bridge). Finally, Ivy Bridge improves anisotropic filtering quality. As Intel Fellow Tom Piazza put it, "we now draw circles instead of flower petals" referring to image output from the famous AF tester.Intel made the Ivy Bridge GPU more modular than before. In SNB there were two GPU configurations: GT1 and GT2Ivy Bridge was designed to scale up and down more easily. GT2 has 16 EUs and 2 texture samplers, while GT1 has an unknown number of EUs and 1 texturesampler. Intel also added a graphics-specific L3 cache within Ivy Bridge. Despite being able to share the CPU's L3 cache, a smaller cache located within the graphics core allows frequently accessed data to be accessed without firing up the ring bus.There are other performance enhancements within the shader core. Scatter & gather Quick Sync Performance Improved: With Sandy Bridge Intel introduced an extremely high performing hardware video transcode engine called Quick Sync. The solution ended up delivering the best combination of image quality and Despite the focus on performance, Intel actually reduced the GPU clock in Ivy Bridge. It now runs at up to 95% of the SNB GPU clock, at a lower voltage, while offering much higher performance. Thanks primarily to Intel's 22nm process (the aforementioned improvements help as architectural well), GPU

performance per watt nearly doubles over Sandy Bridge. In our Llano review we found that AMD delivered much longer battery life in games (nearly 2x SNB) - Ivy Bridge should be able to help address this.

performance of any available hardware accelerated transcoding options from

AMD, Intel and NVIDIA. Quick Sync leverages a combination of fixed function

operations now execute 32x faster than

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hardware, IVB's video decode engine and the EU array. The increase in EUs and improvements to their throughput both contribute to

LG Nilson (February 5, 2011). "Ivy Bridge should work in H67 and P67 motherboards". beats. VR-Zone Retrieved

Technology

increases in Quick Sync transcoding performance. Presumably Intel has also done some work on the decode side as well, which is actually one of the reasons Sandy Bridge was so fast at transcoding video. The combination of all of this results in up to 2x the video transcoding performance of Sandy Bridge. There's also the option of seeing less of a performance increase but quality. delivering better image

November 12, 2011. Anand Lal Shimpi (June 1, 2011). "Correction: Thunderbolt Ivy Bridge Featured, and not

Integrated". AnandTech. Retrieved November 11, 2011. "Intel's CEO Discusses Q3 2011 Results - Earnings Call Transcript". Barak, Sylvie (2011-10-21). "Intel Ivy Bridge CPUs may launch in March". EE Times. Retrieved

2011-11-11.

Conclusion:
Sandy Bridge brought about a significant increase in CPU performance, but Ivy seems almost entirely dedicated to

Gruener, Wolfgang (2011-10-19). "Intel to Sell Ivy Bridge Late in Q4 2011". Tom's Hardware. Retrieved 2011-11-11.

addressing Intel's aspirations in graphics. With two architectures in a row focused on improving GPU performance, we might see this trend continue,get more effective architectures by the developments in fabrication technologies.

Shvets, Gennadiy (2011-11-24). "Launch dates of Ivy Bridge

processors". Retrieved 2011-12-04. "Intel's CEO Discusses Q3 2011 Results - Earnings Call Transcript". Webster, Clive (2011-10-10). "Ivy Bridge Media Upgrades and

References:
Cole (May 27, 2011). "Ivy Bridges BackwardsCompatibility Explained". Retrieved November 11, 2011.

Security Features". bit-tech. Dennis Publishing Limited Shvets, Gennadiy (2011-11-27). "Ivy Bridge desktop CPU lineup details". CPU World.

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