TDA4865J; TDA4865AJ

Vertical deection booster

Rev. 02 3 November 2006 Product data sheet

1. General description
The TDA4865J and TDA4865AJ are deection boosters for use in vertical deection systems for frame frequencies up to 200 Hz. The TDA4865J needs a separate yback supply voltage, so the supply voltages are independently adjustable to optimize power consumption and yback time. For the TDA4865AJ the yback supply voltage will be generated internally by doubling the supply voltage and therefore a separate yback supply voltage is not needed. Both circuits provide differential input stages.

2. Features
I I I I I Power amplier with differential inputs Output current up to 3.8 A (p-p) High vertical deection frequency up to 200 Hz High linear sawtooth signal amplication Flyback generator: N TDA4865J: separate adjustable yback supply voltage up to 70 V N TDA4865AJ: internally doubled supply voltage (two supply voltages only for DC-coupled outputs)

3. Quick reference data

Table 1. Symbol VP1 VP2 VFB VP3 Vi(INN) Vi(INP) IP1 Quick reference data Parameter supply voltage 1 supply voltage 2 yback supply voltage of TDA4865J yback generator output voltage of TDA4865AJ input voltage on pin INN input voltage on pin INP supply current 1 during scan IVOUT = 1.9 A Conditions Min 9 VP1 1 VP1 1 0 1.6 1.6 Typ 6 Max 35 70 70 Unit V V V

VP1 + 2.2 V VP1 0.5 V VP1 0.5 V 10 mA

NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster
Quick reference data continued Parameter quiescent supply current 2 vertical deection output current (peak-to-peak value) ambient temperature Conditions IVOUT = 0 Min Typ 25 Max 60 3.8 Unit mA A

Table 1. Symbol IP2 IVOUT(p-p)

Tamb

20

+75

4. Ordering information
Table 2. Type number TDA4865J TDA4865AJ Ordering information Package Name DBS7P Description plastic DIL-bent-SIL power package; 7 leads (lead length 12/11 mm); exposed die pad Version SOT524-1

5. Block diagram

THERMAL PROTECTION

TDA4865J

DIFFERENTIAL INPUT STAGE

VERTICAL OUTPUT

FLYBACK GENERATOR

REFERENCE CIRCUIT

7 INP

6 INN

5 VOUT
RS1 CS1

4 GND

3 VP2

2 VFB
D1

1 VP1

C1 RP R3 deflection coil

C4

C2

R4

from deflection controller

R2

R1

VN

VF

VP
001aad296

Fig 1. Block diagram of TDA4865J

TDA4865J_TDA4865AJ_2

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Product data sheet

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

THERMAL PROTECTION

TDA4865AJ

DIFFERENTIAL INPUT STAGE

VERTICAL OUTPUT

FLYBACK GENERATOR

REFERENCE CIRCUIT

7 INP

6 INN

5 VOUT
RS1 CS1

4 GND

3 VP2
CF

2 VP3

1 VP1

D1 deflection coil C1 C2 R5

RP R3

R6

from deflection controller

R2

R1

VN

VP
001aad297

Fig 2. Block diagram of TDA4865AJ

6. Pinning information
6.1 Pinning

VP1 VFB VP2 GND VOUT INN INP

1 2 3 4 5 6 7
001aad298

VP1 VP3 VP2

1 2 3 4 5 6 7
001aad299

TDA4865J

GND VOUT INN INP

TDA4865AJ

Fig 3. Pin conguration for DBS7P (TDA4865J)

Fig 4. Pin conguration for DBS7P (TDA4865AJ)

TDA4865J_TDA4865AJ_2

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

6.2 Pin description

Table 3. Symbol VP1 VFB VP3 VP2 GND VOUT INN INP Pin description Pin TDA4865J 1 2 3 4 5 6 7 TDA4865AJ 1 2 3 4 5 6 7 positive supply voltage 1 yback supply voltage yback generator output supply voltage 2 for vertical output ground or negative supply voltage vertical output inverted input of differential input stage non-inverted input of differential input stage Description

7. Functional description
Both the TDA4865J and TDA4865AJ consist of a differential input stage, a vertical output stage, a yback generator, a reference circuit and a thermal protection circuit. The TDA4865J operates with a separate yback supply voltage (see Figure 1) while the TDA4865AJ generates the yback voltage internally by doubling the supply voltage (see Figure 2).

7.1 Differential input stage

The differential sawtooth input current signal (from the deection controller) is connected to the inputs (inverted signal to pin INN and non-inverted signal to pin INP). The vertical feedback signal is superimposed on the inverted signal on pin INN.

7.2 Vertical output and thermal protection

The vertical output stage is a quasi-complementary class-B amplier with a high linearity. The output stage is protected against thermal overshoots. For a junction temperature of Tj > 150 C the protection will be activated and will reduce the deection current (IVOUT).

7.3 Flyback generator

The yback generator supplies the vertical output stage during yback. The TDA4865J is used with a separate yback supply voltage to achieve a short yback time with minimized power dissipation. The TDA4865AJ needs a capacitor (CF) connected between pins VP3 and VP2 (see Figure 2). Capacitor CF is charged during scan, using the external diode D1 and resistor R5. During yback the cathode of capacitor CF is connected to the positive supply voltage and the yback voltage is then twice the supply voltage. For the TDA4865AJ the resistor R6 in the positive supply line can be used to reduce the power consumption.

TDA4865J_TDA4865AJ_2

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Product data sheet

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

In parallel with the deection coil a damping resistor RP and an RC combination (RS1 = 5.6 and CS1 = 100 nF) are needed. Furthermore, another additional RC combination (RS2 = 5.6 and CS2 = 47 nF to 150 nF) can be used to minimize the noise effect and the yback time (see Figure 7 and Figure 8).

8. Internal circuitry
Table 4. Symbol TDA4865J VP1 VFB VP2 GND VOUT INN INP 1 2 3 4 5 6 7
INP 7 INN 6 VOUT 5 GND 4 VP2 3 VFB 2 VP1 1

Internal circuits Pin Equivalent circuit

TDA4865J

001aad300

TDA4865AJ VP1 VP3 VP2 GND VOUT INN INP 1 2 3 4 5 6 7

INP 7 INN 6 VOUT 5 GND 4 VP2 3 VP3 2 VP1 1

TDA4865AJ

001aad301

TDA4865J_TDA4865AJ_2

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

9. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages referenced to pin GND; unless otherwise specied. Symbol VP1 VP2 VFB VP3 Vi(INN) Vi(INP) Vo(VOUT) IP2 Io(VOUT) IVFB IVP3 Tstg Tamb Tj Vesd Parameter supply voltage 1 supply voltage 2 yback supply voltage of TDA4865J yback generator output voltage of TDA4865AJ input voltage on pin INN input voltage on pin INP output voltage on pin VOUT supply current 2 output current on pin VOUT current during yback of TDA4865J current during yback of TDA4865AJ storage temperature ambient temperature junction temperature electrostatic discharge voltage machine model human body model
[1] [2] [3] Internally limited by thermal protection; will be activated for Tj 150 C. Class C according to EIA/JESD22-A115-A. Class 3A according to JESD22-A114C.01.
[1] [2] [3] [1]

Conditions

Min 0 25 20 400 4000

Max 40 70 70 VP1 + 3 VP1 VP1 72 2.0 2.0 2.0 2.0 +150 +75 150 +400 +4000

Unit V V V V V V V A A A A C C C V V

10. Thermal characteristics

Table 6. Symbol Rth(j-mb)
[1]

Thermal characteristics Parameter thermal resistance from junction to mounting base Conditions
[1]

Typ 4

Unit K/W

To minimize the thermal resistance from mounting base to heat sink [Rth(mb-h)] follow the recommended mounting instruction: screw mounting preferred; torque = 40 Ncm; use heat sink compound; isolation plate increases Rth(mb-h).

11. Characteristics
Table 7. Characteristics VP1 = 25 V; Tamb = 25 C; voltages referenced to pin GND; unless otherwise specied. Symbol Supplies VP1 VP2 VFB supply voltage 1 supply voltage 2 yback supply voltage of TDA4865J 9 VP1 1 VP1 1 35 70 70 V V V Parameter Conditions Min Typ Max Unit

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TDA4865J; TDA4865AJ
Vertical deection booster

Table 7. Characteristics continued VP1 = 25 V; Tamb = 25 C; voltages referenced to pin GND; unless otherwise specied. Symbol VP3 IP1 IP2 Vi(INN) Vi(INP) Iq(INN) Iq(INP) IVFB IVP3 VVP2-VFB(r) Parameter Conditions Min 0 1.6 1.6 2.3 2.8 3.5
[1]

Typ 6 25 100 100 2 2.2 2.7 1.5 1.7 2.1 2 2.2 2.7 1.5 1.7 2.1 1.3 1.5 2.6 2.0 2.2 2.6 -

Max VP1 + 2.2 10 60 VP1 0.5 VP1 0.5 500 500 1.9 1.9 1.9 3.8 1.7 2.3 3.0 1

Unit V mA mA V V nA nA A A V V V V V V V V V V V V A A V V V V V V %

yback generator output voltage of IVOUT = 1.9 A TDA4865AJ supply current 1 quiescent supply current 2 input voltage on pin INN input voltage on pin INP input quiescent current on pin INN input quiescent current on pin INP current during yback of TDA4865J current during yback of TDA4865AJ reverse voltage drop during yback IVOUT = 1 A of TDA4865J IVOUT = 1.25 A IVOUT = 1.9 A forward voltage drop during yback IVOUT = 1 A of TDA4865J IVOUT = 1.25 A IVOUT = 1.9 A reverse voltage drop during yback IVOUT = 1 A of TDA4865AJ IVOUT = 1.25 A IVOUT = 1.9 A forward voltage drop during yback IVOUT = 1 A of TDA4865AJ IVOUT = 1.25 A IVOUT = 1.9 A during scan IVOUT = 0

Differential input stage

Flyback generator

VVP2-VFB(f)

VVP3-VP1(r)

VVP3-VP1(f)

Vertical output stage; see Figure 5 IVOUT IVOUT(p-p) Vo(sat)n vertical deection output current vertical deection output current (peak-to-peak value) output saturation voltage to ground IVOUT = 1 A IVOUT = 1.25 A IVOUT = 1.9 A Vo(sat)p output saturation voltage to VP2 IVOUT = 1 A IVOUT = 1.25 A IVOUT = 1.9 A LIN
[1]

non-linearity of output signal

Deviation of the output slope at a constant input slope.

TDA4865J_TDA4865AJ_2

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Product data sheet

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

input signal on pin INN

input signal on pin INP

t VFB(1)
output voltage on pin VOUT V P1

GND

deflection current through the coil

001aab327

(1) VFB for TDA4865J; 2VP1 for TDA4865AJ.

Fig 5. Timing diagram

12. Application information

VF VFB
1N4448 > 1 k

VP

TDA4865J

guard output HIGH = error

BC548

VOUT

2.2 BC556

3.3 k

22 F

220 k

vertical output signal

001aad302

Fig 6. Application diagram with TDA4865J for external guard signal generation

TDA4865J_TDA4865AJ_2

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

THERMAL PROTECTION

TDA4865J

DIFFERENTIAL INPUT STAGE

VERTICAL OUTPUT

FLYBACK GENERATOR

REFERENCE CIRCUIT

7 INP

6 INN

5 VOUT
RS1 CS1 5.6 100 nF RP 270 deflection coil

4 GND

3 VP2

2 VFB
D1 BYV27

1 VP1

CS2(1) RS2 5.6

470 F

470 F 4.3

470 F

R3

from deflection controller

1.8 k R2 1.8 k R1 0.5 (1 W)

VN 8 V

VF +50 V

VP +9 V
001aad303

Remark: the heat sink of the IC must be isolated against ground of the application (it is connected to pin GND). (1) With CS2 (typical value between 47 nF and 150 nF) the yback time and the noise behavior can be optimized.

Fig 7. Application diagram with TDA4865J

TDA4865J_TDA4865AJ_2

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

THERMAL PROTECTION

TDA4865AJ

DIFFERENTIAL INPUT STAGE

VERTICAL OUTPUT

FLYBACK GENERATOR

REFERENCE CIRCUIT

7 INP

6 INN

5 VOUT
RS1 CS1 5.6 100 nF RP 270 deflection coil

4 GND

3 VP2
CF 100 F R5 (2) 240 (2 W)

2 VP3

1 VP1

D1 470 F BYV27 3.9 (2 W) R6 (3)

CS2(1) RS2 5.6

R3

from deflection controller

1.8 k R2 1.8 k R1 0.5 (1 W)

470 F

VN 12.5 V

VP +12.5 V
001aad304

Remark: the heat sink of the IC must be isolated against ground of the application (it is connected to pin GND). (1) With CS2 (typical value between 47 nF and 150 nF) the yback time and the noise behavior can be optimized. (2) With R5 capacitor CF will be charged during scan and the value (typical value between 150 and 270 ) depends on Ide, tb and CF. (3) R6 reduces the power dissipation of the IC. The maximum possible value depends on the application.

Fig 8. Application diagram with TDA4865AJ

12.1 Example for both TDA4865J and TDA4865AJ

Table 8. Symbol Ide(max)(M) Ldecoil Rdecoil RP R1 R2 R3 VF[1] Tamb Tdecoil Rth(j-mb) Rth(mb-h) Rth(h-a)
[1]

Values given from application Value 1.6 (peak value) 10 4 270 0.5 1.8 1.8 50 50 75 4 0.5 2 Unit A mH k k V C C K/W K/W K/W

Flyback voltage measured against 0 V; for TDA4865J only.

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Product data sheet

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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster
Calculated values Value TDA4865J TDA4865AJ 15 15 12.1 3.85 8.25 7.27 103.6 720 V V W W W K/W C s 8 13 8.5 3.85 4.65 12.9 93 650 Unit

Table 9. Symbol VP1 VN Ptot Pde PIC Rth(tot)(max) Tj(max)[1] tb

[1]

With a heat sink of 2 K/W.

VP1, VN and VFB are referenced to ground of application; voltages are calculated with +10 % tolerances. The calculation formulae for supply voltages are as follows: V P1 = V o ( sat ) p + ( R1 + R deflcoil ) I defl ( max ) U' L + U D1 V N = V o ( sat )n + ( R1 + R deflcoil ) I defl ( max ) + U' L where: UL = Ldecoil 2Ide(max) fv fv = vertical deection frequency UD1 = forward voltage drop across D1 The calculation formulae for power consumption is: P IC = P tot P defl I defl ( max I defl ( max P tot = ( V P1 U D1 ) ---------------------) + V N ---------------------) + ( V P1 + V N ) 0.01 + 0.2 4 4 R deflcoil + R1 2 P defl = -------------------------------- I defl ( max ) 3 where: PIC = power dissipation of the IC Ptot = total power dissipation Pde = power dissipation of the deection coil Calculation formulae for maximum required thermal resistance for the heat sink at Tj(max) = 110 C: R th ( tot ) = R th ( j-mb ) + R th ( mb-h ) + R th ( h-a ) T j ( max ) T amb R th ( h-a ) = ----------------------------------- R th ( j-mb ) R th ( mb-h ) P IC
TDA4865J_TDA4865AJ_2

(1) (2)

(3) (4) (5)

(6) (7)
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NXP Semiconductors

TDA4865J; TDA4865AJ
Vertical deection booster

Calculation formulae for yback time (for TDA4865J only): L deflcoil V F + ( R deflcoil + R1 ) I defl ( max ) t flb = -------------------------------- ln ------------------------------------------------------------------------------- V F ( R deflcoil + R1 ) I defl ( max- R deflcoil + R1 ) where: VF measured against 0 V (8)

12.2 Application example for different driver circuits

TDA4865J or TDA4865AJ
7 INP
R2a

6 INN

5 VOUT
RS1 CS1

4 GND

Vref
R2b

5.6 100 nF CS2 RS2 5.6 RP 270 deflection coil

Idefl Idefl(max)(P) Idefl Idefl(max)(N) t

Iv(drv) Iv(drv)(max)
R3

Iv(drv) Iv(drv)(min) t

R1 1

001aad305

Fig 9. Application for single-ended driver currents with inverting amplier

TDA4865J or TDA4865AJ
Iv(drv) Iv(drv)(max) Iv(drv) 7 INP 6 INN 5 VOUT
RS1 CS1

4 GND

Iv(drv)(min)

R2

t
CS2 RS2 5.6 RP 270

5.6 100 nF

Idefl Idefl(max)(P)

deflection coil

Idefl Idefl(max)(N)

R3a

R3b

Vref
R1 1

001aad306

Fig 10. Application for single-ended driver currents with non-inverting amplier

TDA4865J_TDA4865AJ_2

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TDA4865J; TDA4865AJ
Vertical deection booster

TDA4865J or TDA4865AJ
Vdrv Vdrv(max) 7 INP 6 INN 5 VOUT
RS1 CS1 5.6 100 nF CS2 RS2 5.6 RP 270 deflection coil

4 GND

Vdrv Vdrv(min) t

Idefl Idefl(max)(P) Idefl Idefl(max)(N) t

R3a

R3b

Vref
R1 1

001aad307

Fig 11. Application for single-ended driver voltage output with non-inverting amplier

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TDA4865J; TDA4865AJ
Vertical deection booster

13. Package outline

DBS7P: plastic DIL-bent-SIL power package; 7 leads (lead length 12/11 mm); exposed die pad SOT524-1

non-concave x Eh

q1

Dh D D1 P k view B: mounting base side A2 q2

L2 L

L3

L1

1 Z e1 e bp

w M 0 5 scale e e1 e2 k 3 2 L L1 L2 L3 4.5 3.7 10 mm

Q m e2

v M

DIMENSIONS (mm are the original dimensions) UNIT A2(2) bp mm c D(1) D1(2) Dh E(1) Eh 3.5

m 2.8

q1

q2

Z(1) 2.92 2.37

2.7 0.80 0.58 13.2 6.2 2.3 0.65 0.48 12.8 5.8

14.7 3.5 2.54 1.27 5.08 14.3

12.4 11.4 6.7 11.0 10.0 5.5

3.4 1.15 17.5 4.85 3.8 3.1 0.85 16.3 3.6

0.8 0.3 0.02

Notes 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. Plastic surface within circle area D1 may protrude 0.04 mm maximum. OUTLINE VERSION SOT524-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-07-03 03-03-12

Fig 12. Package outline SOT524-1 (DBS7P)

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TDA4865J; TDA4865AJ
Vertical deection booster

14. Soldering
14.1 Introduction to soldering through-hole mount packages
This text gives a brief insight to wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.

14.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specied maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

14.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.

14.4 Package related soldering information

Table 10. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[2]
[1] [2]

Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable

For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. For PMFP packages hot bar soldering or manual soldering is suitable.

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TDA4865J; TDA4865AJ
Vertical deection booster

15. Revision history

Table 11. Revision history Release date 20061103 Data sheet status Product data sheet Change notice Supersedes TDA4865_1 Document ID TDA4865J_TDA4865AJ_2 Modications:

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors Legal texts have been adapted to the new company name where appropriate Preliminary specication -

TDA4865_1

19921208

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Vertical deection booster

16. Legal information

16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

17. Contact information

For additional information, please visit: http://www.nxp.com For sales ofce addresses, send an email to: salesaddresses@nxp.com

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Vertical deection booster

18. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 8 9 10 11 12 12.1 12.2 13 14 14.1 14.2 14.3 14.4 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Differential input stage . . . . . . . . . . . . . . . . . . . 4 Vertical output and thermal protection . . . . . . . 4 Flyback generator . . . . . . . . . . . . . . . . . . . . . . . 4 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 8 Example for both TDA4865J and TDA4865AJ 10 Application example for different driver circuits 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering by dipping or by solder wave . . . . . 15 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 15 Package related soldering information . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2006.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 November 2006 Document identifier: TDA4865J_TDA4865AJ_2