LTE MIMO System Level Design

LTE MIMO System-Level Design
(Preliminary)
Copyright Agilent Technologies 2009 Agilent Restricted 1
Agenda
MIMO Overview MIMO Transmitter Case Study MIMO Receiver Case Study Early R&D LTE Hardware Testing
Basic channel access modes

Transmit Antennas
The Radio Channel
Receive Antennas
Transmit Antennas
The Radio Channel
Receive Antennas
SISO
Single Input Single Output
SIMO
Single Input Multiple Output (Receive diversity)
MISO
MIMO
Multiple Input Single Output (Transmit diversity)
Multiple Input Multiple Output (Multiple stream)

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Advantages of multiple antennas

MISO (Tx diversity) increases the robustness of the signal to poor channel conditions. It does not increase data rates but increases coverage and therefore cell capacity. SIMO (Rx diversity) improves the received SNR by combining multiple copies of the same signal. Like MISO it does not increase data rates but extends coverage and hence cell capacity. MIMO uses multiple data streams to increase cell capacity. The data streams can be allocated to one user to increase single-user data rates.
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Multiple antenna techniques

Multiple antenna techniques are fundamental to LTE and an appreciation of the different methods and their relative advantages and disadvantages is important
There are three main multi-antenna techniques used in LTE 1. Transmit/receive diversity 2. Spatial multiplexing Single User MIMO (SU-MIMO) Multi-user MIMO (MU-MIMO) 3. Beamforming
Transmit/receive diversity
This is the same as what already exists for UMTS Transmit diversity has been specified for W-CDMA since R99. Receive diversity was introduced in Rel-6 for HSDPA.
Stream 1
eNB UE
Stream 1
The same data is sent on two antennas which provides better SNR Improves performance in low SNR conditions and with fading Simple combining is used in the receiver
Single user MIMO

SU-MIMO
= data stream 1
UE 1
= data stream 2
eNB 1
This is an example of downlink 2x2 single user MIMO with precoding. Two data streams are mixed (precoded) to best match the channel conditions. The receiver reconstructs the original streams resulting in increased singleuser data rates and corresponding increase in cell capacity. 2x2 SU-MIMO is mandatory for the downlink and optional for the uplink
Multiple user MIMO

MU-MIMO
= data stream 1 = data stream 2
UE 1 UE 2 eNB 1
Example of uplink 2x2 MU-MIMO. In multiple user MIMO the data streams come from different UE. There is no possibility to do precoding since the UE are not connected but the wider TX antenna spacing gives better de-correlation in the channel. Cell capacity increases but not the single user data rate. The key advantage of MU-MIMO over SU-MIMO is that the cell capacity increase can be had without the increased cost and battery drain of two UE transmitters. MU-MIMO is more complicated to schedule than SU-MIMO
SystemVue MIMO Source
SystemVue MIMO Channel Model
Simulated Spectrum with MIMO Fading
SystemVue MIMO Receiver
Agenda
Mixed-Signal Challenges: System Design Tradeoffs

Channel
D/A Bits In
Coding Algorithms
A/D
Tx
Gain Linearity Output Power
Rx
Gain NF Phase Noise
Decoding Algorithms
Bits Out
Considerations: Key Algorithms Baseband Implementation/ Fixed-Point Effects RF Design Impairments/Non-Linearities Phase Noise, ADC Jitter Channel Impairments
Fixed Point Baseband Designs
Math Algorithms FPGA HDL Code
System-Level Architecture Design

Partition Design Requirements to Meet LTE Specifications without Over-Designing
Coding/ Decoding Algorithms Mixed-Signal Receiver
Baseband Fixed-Point
With LTE having such high performance targets every part of the transmit and receive chain becomes critical to the link budget So how to decide the optimum balance, without over-designing? How are design requirements impacted going from QPSK to 16QAM to 64QAM?
ADC and DAC Impairments
RF Transmitter/ PA Nonlinarities
RF Channel
D/A Bits In A/D
Coding Algorithms
Tx
Rx
Decoding Algorithms
Bits Out
Baseband Libraries
Algorithm Test Vectors for FPGA Development
Coding/ Decoding Algorithms
(Preliminary)
Configurable References
(Preliminary)
FPGA Scrambler Example

Switch between C++ model and math algorithm model
SystemVue Scrambler Output
Diff
HDL (Actual Scrambler Code Not Shown)

FPGA HDL CoSim Output
(Preliminary)
FPGA Scrambler Example

Switch between C++ model and math algorithm model
SystemVue Scrambler Output
Diff
HDL (Actual Scrambler Code Not Shown)

FPGA HDL CoSim Output
(Preliminary)
Transmitter Design
Start with SystemVue Pre-Configured Template
Design Fixed Point IQ Modulator and Replace Ideal IQ Modulator

Baseband Fixed-Point
4X UpSample
I(t)*CosWc(t)
I in
FIR RRC Fs/4 Carrier Multiplexing I(t)*CosWc(t)Q(t)*SinWc(t)
FIR RRC
Q in
4X UpSample
Q(t)*SinWc(t)
10
64QAM EVM Results with FIR Wordlength =10 for Fixed Point IQ Modulator Design
EVM = 0.5 %
(Preliminary)
64QAM EVM Results with FIR Wordlength =8 for Fixed Point IQ Modulator Design
EVM = 1.3 %
(Preliminary)
11
64QAM EVM Results with FIR Wordlength =6 & 7 for Fixed Point IQ Modulator Design
FIR Wordlength = 7 bits FIR Wordlength = 6 bits
EVM = 2.9 %
EVM = 46 % !
(Preliminary)
Enable HDL Code Gen to Target an FPGA
12
Add RF Design: Transmitter and Antenna Cross Talk

Specify LO Phase Noise dBc/Hz @ Freq. Offset
RF Transmitter/ PA Nonlinarities
Specify 1dB Comp. Pt.
-80 dBc/Hz Phase Noise @ 10kHz with -30 dB CrossTalk

Specify Phase Noise in dBc/Hz vs. Frequency Offset
RS EVM = 1.3 %
RS EVM = 1.3 %
QPSK
26
64 QAM
(Preliminary)
13

RS EVM = 3.5 %
RS EVM = 3.5 %
QPSK
27
64 QAM
(Preliminary)

Phase noise is introducing significant ICI , which is impacting OFDMA subcarrier orthogonality
RS EVM = 11.2 %
RS EVM = 11.2 % , but composite EVM is 85%
QPSK
28
64 QAM
(Preliminary)
14
LTE MIMO Downlink BER with ADI A/D Converter

MIMO Source MIMO Channel MIMO Receiver
Sweep SNR
Mixed-Signal Receiver ADC and DAC Impairments
ADI A/D Converter
QPSK BER Results with Swept ADI A/D Converter Jitter
6% Jitter 4% Jitter 2% Jitter
(Preliminary)
15
QPSK , 16QAM, 64QAM Results vs. Swept ADI ADC Jitter

6% Jitter 6% Jitter 4% 2% Jitter Jitter 6% Jitter 4% Jitter 2% Jitter 2% Jitter 4% Jitter
QPSK
16 QAM
64 QAM
(Preliminary)
QPSK , 16QAM, 64QAM Results vs. Swept LO Phase Noise

-60 dBc/Hz
-65 dBc/Hz -70 dBc/Hz
QPSK
16 QAM
64 QAM
(Preliminary)
16
Agenda
SISO Early R&D SDR Hardware Testing

Simulated COTS Waveform
RF IF
Simulated COTS Receiver

I
Demodulator A/D Converter
Baseband De-Coding
RF/RF BER
SystemVue + VSA SW
MXG, ESG
Step 1 Download Signal
Step 2 Capture Signal
MXA, PSA
17

RF IF

I
Demodulator
A/D Converter
Baseband De-Coding
RF/IF BER
SystemVue + VSA SW
MXG, ESG
MXA, PSA

RF IF

I
Demodulator
A/D Converter
Baseband De-Coding
RF/ Analog IQ BER

SystemVue + VSA SW
MXG, ESG
MXA with BB IQ
18

RF IF
I
Demodulator
A/D Converter
Baseband De-Coding
Simulated COTS Baseband Receiver
RF/Digital IQ BER RF/Digital IF BER

SystemVue + VSA SW
MXG, ESG
Logic Analyzers
Picture of LTE OFDMA Mixed-Signal DUT SISO BER Test Setup

14 Bit A/D Board DUT
N6705A DC Power Analyzer MXG (Download Signal from SystemVue) ESG (DUT Clock)
16822A Logic Analyzer with Agilent SystemVue*
* Note: SystemVue does not ship with Logic Analyzer

19
LTE OFDMA SISO BER Test Setup Diagram

LAN Cable Download SystemVue LTE TDD/FDD Signal via LAN Event 1 Marker Out Trigger In
SVue LTE TDD/FDD Signal at 7.68 MHz IF
MXG
Analog In
SystemVue
30.72 MHz
Clk In
14-Bit A/D Converter Board (DUT)

+ 5V
Dig. Out
ESG
+ 3.3V
16822 Logic Analyzer with SystemVue installed

LAN Cable
N6705A DC Power Analyzer

LTE OFDMA SISO BER Results (TDD)
(Preliminary)
20
Automate Testing with SystemVue Math Scripting
Power Supply/ Analyzer MXG
14-Bit A/D Converter DUT Sweep from: QPSK to 16 QAM to 64QAM Sweep DC Bias with Power Supply/ Analyzer
Sweep RF Power on MXG BER Logic Analyzer with SystemVue Installed (Preliminary)
41
FDD SISO BER with Swept QPSK, 16QAM, 64QAM, +5V Bias
(Preliminary)
21
New LTE Reference Vector White Paper

http://www.agilent.com/find/eesof-lte-whitepaper
From an Agilent FPGA Developer using SystemVue: SystemVue helped me discover a typing error in my 16QAM scrambler which was failing tests. It has saved MBD at least 3 months of development time already, and is crucial for meeting - and exceeding - our on-going development time goals. http://cp.literature.agilent.com/lit web/pdf/5990-3671EN.pdf
New LTE Book

www.agilent.com/find/ltebook
22
For More Information:

www.agilent.com/find/systemvue
For More Information: www.agilent.com/find/lte
23
Summary
Trade-off baseband and RF design impairments for system-level design requirements Evaluate fixed-point design impairments on system-level metrics such as EVM and BER; Generate HDL from fixed-point design to target FPGAs Generate LTE reference vectors to validate hand-written HDL code for FPGA implementations Perform system-level design trade-offs to minimize over-designing to meet specs (e.g. fixed point vs. LO phase noise vs. RF nonlinearities vs. ADC jitter) Combine simulation with test equipment to perform coded BER on RF/mixed-signal hardware, using simulation to provide baseband coding/decoding functionality
Thank You!
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LTE MIMO System Level Design

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LTE MIMO System-Level Design

Copyright Agilent Technologies 2009 Agilent Restricted 1

Copyright Agilent Technologies 2009 Agilent Restricted 2

Basic channel access modes

The Radio Channel

The Radio Channel

Single Input Multiple Output (Receive diversity)

Multiple Input Single Output (Transmit diversity)

Multiple Input Multiple Output (Multiple stream)

Advantages of multiple antennas

Copyright Agilent Technologies 2009 Agilent Restricted P 4 age 4

Multiple antenna techniques

Copyright Agilent Technologies 2009 Agilent Restricted P 5 age 5

Copyright Agilent Technologies 2009 Agilent Restricted P 6 age 6

Single user MIMO

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Multiple user MIMO

SystemVue MIMO Source

Copyright Agilent Technologies 2009 Agilent Restricted 9

SystemVue MIMO Channel Model

Simulated Spectrum with MIMO Fading

Copyright Agilent Technologies 2009 Agilent Restricted 10

SystemVue MIMO Receiver

Copyright Agilent Technologies 2009 Agilent Restricted 11

Copyright Agilent Technologies 2009 Agilent Restricted 12

Mixed-Signal Challenges: System Design Tradeoffs

Fixed Point Baseband Designs

Math Algorithms FPGA HDL Code

Copyright Agilent Technologies 2009 Agilent Restricted 13

System-Level Architecture Design

ADC and DAC Impairments

Copyright Agilent Technologies 2009 Agilent Restricted 14

Coding/ Decoding Algorithms

FPGA Scrambler Example

SystemVue Scrambler Output

HDL (Actual Scrambler Code Not Shown)

FPGA Scrambler Example

SystemVue Scrambler Output

HDL (Actual Scrambler Code Not Shown)

Copyright Agilent Technologies 2009 Agilent Restricted 19

Design Fixed Point IQ Modulator and Replace Ideal IQ Modulator

Copyright Agilent Technologies 2009 Agilent Restricted 20

Enable HDL Code Gen to Target an FPGA

Copyright Agilent Technologies 2009 Agilent Restricted 24

Add RF Design: Transmitter and Antenna Cross Talk

Specify 1dB Comp. Pt.

Copyright Agilent Technologies 2009 Agilent Restricted 25

-80 dBc/Hz Phase Noise @ 10kHz with -30 dB CrossTalk

-70 dBc/Hz Phase Noise @ 10kHz with -30 dB CrossTalk

-60 dBc/Hz Phase Noise @ 10kHz with -30 dB CrossTalk

RS EVM = 11.2 % , but composite EVM is 85%

LTE MIMO Downlink BER with ADI A/D Converter

Mixed-Signal Receiver ADC and DAC Impairments

ADI A/D Converter

Copyright Agilent Technologies 2009 Agilent Restricted 29

QPSK BER Results with Swept ADI A/D Converter Jitter

6% Jitter 4% Jitter 2% Jitter

QPSK , 16QAM, 64QAM Results vs. Swept ADI ADC Jitter

QPSK , 16QAM, 64QAM Results vs. Swept LO Phase Noise

-65 dBc/Hz -70 dBc/Hz

Copyright Agilent Technologies 2009 Agilent Restricted 33

SISO Early R&D SDR Hardware Testing