Probabilistic Decision Diagrams for Exact Probabilistic Analysis

Afshin Abdollahi University of California, Riverside Afshin@ee.ucr.edu

exact probabilistic analysis of such circuits. Identical nodes in PDDs are merged (not represented twice) and unnecessary decisions are skipped. These are partly the reasons for compactness of PDDs. The PDD for a circuit is formed based on probabilistic behavior of individual gates to provide an exact model that implicitly takes signal dependencies (correlations) into account. The resulting PDD can be used to compute the reliability of the circuit i.e., the probability that the circuit generates the correct output. Some other probabilistic behavior of the circuit (such as output error probability for arbitrary input probability distribution) can be obtained by extracting the desired information directly from PDDs (As opposed to obtaining output information for all input combinations and combine this information afterwards.) One important application to probabilistic analysis is to verify a fault tolerant design or identify components of a circuit that are most affected by probabilistic error for improvement for example by adding redundancies. Decision diagrams in general are used not only for logic simulation but have also proven to be an effective means for synthesis of logic circuits. The proposed PDDs are no exception to this fact; although we have not included a PDD based synthesis in this paper because of limited space, the reader can appreciate the amenability of this representation to synthesis algorithms, judging by previous work in other areas [3][4]. The remainder of this paper is organized as follows. In section II, related works are outlined. In section III, some preliminary concepts are presented. In Section IV, probabilistic decision diagrams are introduced followed by methods for using and manipulating the PDDs. Experimental results and conclusions are presented in sections V and VI.

Abstract A decision diagram based framework is proposed for representing the probabilistic behavior of circuits with faulty gates. We introduce Probabilistic decision diagrams (PDD) as an exact computational tool which along with vast expressive power holds many other useful properties such as space efficiency (on average) and efficient manipulation algorithms (polynomial in size.) An algorithm for constructing the PDD for a circuit is proposed. Useful information about probabilistic behavior of the circuit (such as output error probability for arbitrary input probability distribution) can be directly extracted from the PDD representation. Experimental results demonstrate the effectiveness and applicability of the proposed approach.

I. INTRODUCTION Probabilistic errors-caused by temporary malfunction of nano-devices- pose a major concern as device dimensions are reaching their fundamental physical limits. In addition, most emerging nano-architectures are susceptible to probabilistic errors because of inherent uncertainty in behavior of devices and interconnects in such small scales [1][2]. Common sources of error are power supply fluctuations and ground bounce, capacitive and inductive coupling, reduced noise margin and increased leakage. Probabilistic error will be even more challenging in emerging technologies such as nanowire, carbon nano-tubes and resonant tunnel diodes (RTD.) Probabilistic errors need to be considered as an intrinsic property of each gate, and nano-architectures must be designed to perform reliable computation from these unreliable devices. Traditional deterministic logic representations such as truthtable and binary decision diagrams will not suffice to fully describe the behavior of probabilistic gates and circuits. New formalisms and models are required to analyze, evaluate, and design (reliable) circuits from unreliable gates. Decision diagrams have been successfully used for several applications in logic synthesis and verification [3][4]. In this paper probabilistic decision diagrams are proposed to model the probabilistic behavior of circuits with faulty gates. PDDs offer a compact representation that allows for fast

II. PREVIOUS WORK Although in this section we will mostly focus on related work on probabilistic analysis rather than synthesis, we will also mention some substantial works in probabilistic synthesis.

In [5] Triple Modular Redundancy and NAND multiplexing methods were proposed for the first time. A number of researchers worked on computing the theoretical error bounds for circuits of faulty gates [5][6][7]. Matrix representation for logic gates have been used in some works. First such approach was proposed in [8] and later continued in [9] where the notion of probabilistic transfer matrix was introduced. In [9] parallel composition of gates is represented by tensor products. These techniques are difficult to scale as the tensor products introduce excessive space and performance complexity. In [10] algebraic decision diagrams are used to represent the gate matrices (and hence indirect modeling of the circuit). This indirect use of decision diagram results in suboptimal (in space and hence performance) representation of circuits as will be discussed later in this paper. Among other approaches are: using Bayesian models in [11] and Markov models in [12]. The problem of probabilistic analysis of a circuit is known to be of exponential complexity [10]. However we introduce PDDs to alleviate the complexity since PDDs take advantage of several useful properties (such as node sharing and unnecessary node elimination) which results in polynomial complexity (in space and performance) on average. In this part we shortly outline the history of research on decision diagrams. The concept of decision diagrams was first proposed in [13] and later developed in [14][15]. Using complement edges can further reduce the size of the decision diagrams as proposed in [16]. In [17] edge-valued binary decision diagrams were proposed, which can represent and manipulate integer functions and can be used for functional decomposition. Multiplicative binary moment diagrams were introduced in [20] for manipulation of arithmetic functions. An extension of the structure in [20] - Kronecker multiplicative binary moment diagrams was proposed in [21] for the purpose of design verification. III. PROBABILISTIC GATES AND CIRCUITS We start this section by an example of a faulty gate. Consider an AND gate that produces an incorrect output with probability p<0.5 for any given input. We will refer to such unreliable gates as probabilistic gates. This particular faulty AND gate is equivalent to an accurate AND gate followed by a probabilistic inverter (depicted as an inverter with a line thru it in Figure 1(i)) which inverts its input with probability p and acts as a buffer with probability 1p. The table in Figure 1(ii) describes the behavior of the probabilistic inverter. The second column includes the probability of the output being 1 for different input states of the inverter. In general for a probabilistic gate we define the notion of probability table as a table that includes the probability of output being 1 for different input states. Figure 1(iii) shows the probability table for the faulty AND gate.

x y

z (i) z 0 1

z'

xy 00 01 10 11

z' p 1p

z' p p p 1p (iii)

(ii) Figure 1. Probabilistic gates and tables

Notice that this example does not necessarily mean that a probabilistic gate must be configured as in Figure 1(i). In general a probabilistic gate is described by its probabilistic table. We define the operator * which will help us simplify equations throughout this paper. For two probability values a and b we define: a b = (1 a)b + a(1 b) To help better understand the * operator consider two probabilistic inverters with probabilities a and b. The series configuration of these inverters is equivalent to a probabilistic inverter with probability a * b. The reader can verify that this operator is commutative and 1 associative. Lets also define as the inverse of *: c = a b a = c 1 b (Notice that c 1 b = c b ) 1 2b The behavior of the probabilistic inverter can also be described using the following formula: z' = p z In general consider a probabilistic circuit (composed of probabilistic gates) with inputs x1 , x2 , , xn and output y.

The probabilistic function f ( x1 , x2 , , xn ) is defined as the probability of y being 1. For example the function of the probabilistic AND gate in Figure 1(i) is: z ' = f ( x, y) = p ( xy) The objective is to provide a graph based representation for probabilistic functions. In this paper we will refer to probabilistic functions as functions for simplicity.

IV. PROBABILISTIC DECISION DIAGRAMS In this section we introduce Probabilistic Decision Diagrams for the first time along with rules to create PDDs and related manipulation algorithms. There are some previous work in literature are concerned with introducing probabilities into decision diagrams [18][19].

The subject of these works and the nature of their approaches are completely unrelated to the problem at hand as well our approach. Furthermore an important contribution of this paper which is fundamentally original is to encode probabilities into the decision diagrams using weights of edges in the graph. We will demonstrate that this technique will results in considerable compactness and performance of the proposed structure and algorithm. We define PDD as a graph with weighted, directed edges. It has a single terminal node which represents the constant 0. The terminal node has no outgoing edges. Any other node has a decision variable, x, and two outgoing edges as demonstrated in Figure 2(i). f'
p

f'
0.2

f'
0.8

f g'
0.1

x h'
1 0.9

x
0

0 (i)

0 (ii)

Figure 3. An example of equivalent nodes

f x g' (i) h'

g' 0 h' 1 x (ii)

p f'

Functions corresponding to different edges and nodes are obtained as follows: g = 0.1 0 = 0.1 h = 1 0 = 1 f = (1 x) g + xh = 0.9 x + 0.1 f = 0.2 f = 0.54x + 0.26 As one can easily see, the function f = 0.54x+0.26 can also be represented using the graph in Figure 3(ii). To make the PDD a compact and canonical representation, we impose three important rules as follows: (I) First rule is on the edge weights: One of two edges originated from each node should have 0 weight. Consider a general node as in Figure 4(i). Based on previous discussions: f ' = p [(1 x)(q g ) + x(r h)] . If 0 r 1 q 1 , edge weights are replaced according to Figure 4(ii) otherwise (in which case 0 < q 1 r < 1 ) the values in Figure 4(iii) are adopted. It can be verified that, this does not change f. f
p

Figure 2. A generic PDD node and circuit equivalent Each edge and each node of the graph represent a function. The function of an edge (e.g. f) is determined in terms of its weight (p) and the function of its end node (f) as follows: with probablity 1 p (i.e., f f = p f ) f= p 1 f with probablity

The weight of an edge, p, has the following circuit interpretation: Suppose there is a probabilistic circuit, with function, f. Then f can be achieved by a applying a probabilistic inverter to f. The function of a node (f) is described in terms of its decision variable, x, and outgoing edges (g', h'.) as follows: g if x = 0 (i.e., f = (1 x ) g + xh ) f = h if x = 1 The dashed edge corresponds to x=0 and the solid edge corresponds to x=1. This relation also can be described by a multiplexer as in Figure 2(ii). Notice that this circuit representation (Figure 2(ii)) is only to help understanding the PDD and does not necessarily represent the circuit implementation of the function. Given the function for the node, f, the functions of outgoing edges can be obtained by using cofactor relations: g ' = f x =0 h' = f x =1 As an example consider the graph in Figure 3(i).

f
pq

f
pr

x
q r 0

x
r*-1q q*-1r

x
0

(i)

(ii)

(iii)

Figure 4. First Rule: one of the outgoing edge weights is 0. From now on, when the weight of an edge is zero we will not display it in the PDD. (II) Second rule: equivalent sub-graphs of PDD are merged and a node that has equivalent outgoing edges (edges to the

same node with the same weight) is eliminated. (III) Third rule: a unique order on decision variables is maintained for all paths from the root node to the terminal node. A. The construction of PDDs from probabilistic tables In this section we outline how to construct the PDD for a given function. Assume that the given function is represented in form of a probabilistic table (e.g., Figure 1(iii)). The first step is to build a complete binary decision tree that describes the behavior of the function as in Figure 5(i). Notice that the same ordering (x before y) on decision variables should be maintained for all branches of tree (Third rule.) Next, each leaf is replaced by the terminal node followed by a weighted edge where the weight is the value of the leaf (see Figure 5(ii)). In Figure 5(ii) there are two nodes with decision variable y. The left node with decision variable y is eliminated according to the second rule (see Figure 5(iii)). The weights of the edges of the other node with decision variable y are modified according to the first rule resulting in the configuration in Figure 5(iv). z x y p p (i) z x p p 0 (iii) y 1p p 0 (iv) z x p y 1p p y p 0 (ii) z p p y 1 0 (v) x y 1 z x y 1p

from an underlying exact circuit from which the probabilistic circuit has been obtained. However the similarity of the two in this example shows that using PDDs we can describe the probabilistic behavior of circuit without adding significant complexity. Usually representing probabilistic information increases the complexity significantly. (see [10] where a NAND gate is represented by an ADD with 7 nodes. The PDD in Figure 5(v) can be modified to represent a probabilistic NAND gate by simply replacing p with 1p.) This example is evidence to the fact that, the proposed PDD is associated with minimal additional complexity compared to other methods. Before we continue to the next section, it is important to point out that the proposed PDDs are not normally intended to be built from the complete binary decision diagrams. Complete binary decision diagrams are of exponential complexity and we resort to this approach only when we are to build the PDD from a probablistic table; in which case the complexity of the corresponding complete binary decision diagrams is no greater than the provided probablistic table. We designed PDDs to be effectively constructed from a probabilistic circuit the details of which are outlined next. B. Extracting Output Probabilities from PDDs Given the PDD for a function f(x1,x2,,xn) the exact probability of the output can be obtained for any input state (x1,x2,,xn): Any specific input state (x1,x2,,xn) defines a path from the root edge to the terminal node. (Start from the root node and take the dashed edge if the corresponding decision variable is zero otherwise take the solid edge i.e., at a node with decision variable xi use the given value of xi to make the decision between dashed and solid edges.) Lets assume that the weights of the edges of this path are p1,p2,,pm. Then f ( x1 , x2 , , xn ) = p1 p2 pm . As an example for the PDD in Figure 5(v), f (1,1) = p 0 1 = 1 p . If needed, the probability table for a circuit can be extracted from the PDD by obtaining f ( x1 , x2 , , xn ) from the PDD for all input combinations.
Extracting other information from PDDs One of the great properties of PDDs is that information about output error probabilities can be extracted directly from PDDs (rather than from the probability table after being created from the PDD). For example given arbitrary probability distributions on inputs, the output error probability can be computed as follows. Assume that input probability distributions are given by qi =Prob(xi =1). The error probability of the output is computed by a one-time traversal (from bottom to top) of the PDD, from the terminal node to output (root) node. The error probability (EP) of the terminal node, EP(0) is considered to be zero. The EP for a node, f, with decision variable xi outgoing edges g and h (see Figure 2(i)) is computed by:

Figure 5. Process of Constructing a PDD.

The first rule is again applied to the node with decision variable x generating the final PDD in Figure 5(v). Notice the similarity of the PDD for the probabilistic AND gate Figure 5(v) with the ROBDD [15] of an accurate AND gate. The only difference is the weight p of the root edge. This similarity is not the case in general. For a general probabilistic function the PDD structure might be substantially different

EP ( f ) = (1 q i ) EP ( g ' ) + q i EP ( h ' ) The EP corresponding to an edge f with weight p and ending node f (see Figure 2(i)) is obtained by: EP ( f ' ) = min( p EP ( f ),1 p EP ( f )) These relations are used from bottom to top to obtain the PE for the output. This process is of linear complexity in size of PDD. If we are simply interested in the probability of output being one, PO, the following equation should be used: PO ( f ) = (1 q i ) PO ( g ' ) + q i PO ( h ' ) PO ( f ' ) = p PO ( f )
C. Constructing the PDD for a probabilistic circuit Analyzing the exact effect of probabilistic faults in the behavior of the circuit is a very important and complex task. One way is to resort to approximation methods to alleviate the computational complexity of exact analysis. An example is to ignore signal dependencies (correlations.) In this paper we address this problem by building the PDD for the probabilistic circuit. The PDD will describe the function of (not only the outputs but also) every node in the circuit. This process is done by first assigning levels to all nodes of the circuit. The level of each primary input is zero. Every other node in the circuit is the output of a gate. The level of a node is one plus the maximum of levels of inputs of its gate. The PDD structure is constructed by building PDDs for nodes of the circuit one level at a time starting from level zero (primary inputs.) The PDD of nodes at each level are obtained by composing PDDs of lower level nodes (in the immediate fanin of the node). In this part we discuss the composing process for two-input gates. This process can be easily extended for gates of more than two inputs. Consider a gate, F, with inputs g, h and output f. (Figure 6(i).) Given the probability table of the gate and PDDs for g and h the problem is how to obtain the PDD for f = F(g, h).

r = (1 p)(1 q) F00 + (1 p)qF01 + p(1 q) F10 + pqF 11

g
p

h
q

f = F(g, h)
r

0 (i)

0 (ii)

0 (iii)

Figure 7. Composing PDDs (terminal case).

g h

Input 00 01 10 11 (ii)

Output F00 F01 F10 F11

Now we consider the case in which g and h are associated with non-terminal nodes where the decision variables are the same (e.g., x.) as in Figure 8(i), (ii). The case that decision variables are different is discussed afterward. The weight p of the root edge of PDD of g is absorbed in the weights of outgoing edges as in Figure 8(iii) generating g'0 and g'1. Similar process on h, generates h'0 and h'1. (see Figure 8(iv).) Next, the compose algorithm is called recursively to achieve f0 and f1 in Figure 8(v): f0 = F ( g0 , h0 ) f1 = F ( g1 , h1) The resulting weights s and t are modified similar to the method in Figure 4 to comply with the first rule for PDDs described earlier. The final PDD node is shown in Figure 8(vi). If the decision variables are different (e.g., x and y) and x is before y in the ordering, then f0 and f1 are computed recursively using: f0 = F ( g0 , h) f1 = F ( g1 , h) (and resulting s and t weights are modified similar to before.) The opposite case (y before x) can be handled similarly. In this case, y will be the decision variable of the resulting node. The recursion ends when the terminal node (zero) is encountered for which we discussed how to obtain the result (see Figure 7). As an example for composing PDDs consider the circuit in Figure 9(i) where the PDDs for g and h are to be composed by gate F to produce f.

(i)

Figure 6. A gate and its probabilistic table.

The compose algorithm is implemented by a recursive traversal of the two PDD operands g and h. For each pair of nodes that are visited during the traversal, an internal node is added to the resultant PDD. The new node generated by compose algorithm depends on the corresponding decision variables. Several cases must be examined. First suppose that both g and h directly lead to the terminal node with edge weights p and q as in Figure 7(i),(ii). The resulting PDD, f = F(g, h) is shown in Figure 7(iii) where:

g p x
q r v

h
u

p x y x y
w

g F q (i) h f

Input 00 01 10 11 (ii)

Output r 1r 1r r

g0

g1

h0

h1 g h p x y 0 h'1
u*w

f q x y 1 0 (iv) 1 p*q*r x 1 y 1 0 (v)

(i) g

(ii) h

g'0
p*q

g'1
p*r

x h'0
u*v

(iii)

g0

g1

h0

h1

Figure 9. Example for composing PDDs.

(iii) f

(iv) f
s

V. EXPERIMENTAL RESULTS We used a number of the LGSynth91 benchmark circuits to evaluate the performance of the proposed method. Experiments were conducted on a machine with an AMD Opteron processor running at 1.8 Ghz with 2GB RAM. To investigate the effect of probabilistic errors, the gates in benchmark circuits were modified by adding a probabilistic inverter (as in Figure 1(i) with different values for p) to each gate. The probabilistic tables of gates were formed and the PDD for each circuit was constructed at each level by composing PDDs of lower level nodes (discussed in section IV.C). Some of the circuits have more than one output. Hence the PDDs for all outputs are created. Notice that the logic sharing between different outputs also results in node sharing in corresponding PDDs. The output error probabilities were computed (for uniform distribution on inputs) using the direct PDD based method described in the end of section IV.B. Table 1 summarizes the results of the proposed approach on a number of the LGSynth91 benchmark circuits. The 3rd column lists the runtimes (in milliseconds.) For each circuit, the reported runtimes are average times for three experiments. Column 4 is the runtimes reported in [10] for some of the benchmarks. We used a combination of small and large benchmarks while [10] reported the results only for small benchmarks. Columns 5 to 7 include the average output error probabilities for gate error probabilities p=0.001, p=0.01 and p=0.02 respectively. Circuit Gates Time Time Output Error Probabilities

f '0
s

f '1
t

x
t*-1s

f0

f1

f0

f1

(v)

(vi)

Figure 8. Composing PDDs (general case).

Figure 9(ii) shows the probability table for gate F and Figure 9(iii), (iv) show PDDs for g and h respectively. Details of the process are omitted for space limitations. The resulting final PDD for f is shown in Figure 9(v). As can be observed by this example, PDDs are capable of considering signal dependencies for accurate probability propagation. (g and h are correlated since both are dependent on x and y.) Another fact demonstrated by this example is the compactness of the final PDD (Figure 9(v)) generated for this circuit.

(ms) C17 z4ml mux x2 pcle count term1 ttt2 alu2 misex3 duke2 9symml alu4 x4 apex6 frg2 des 3 1 9 1 9 1 12 1 14 2 31 10 38 470 47 50 63 540 77 14640 80 14760 108 220 132 1049 136 60 142 460 233 6520 508 12500

[10] (ms) 76 2220 6130 35300 74900 1758000 -

p=0.001 p=0.01 0.0015 0.0083 0.0021 0.0025 0.0014 0.0016 0.0018 0.0020 0.0079 0.0054 0.0046 0.0106 0.0133 0.0014 0.0026 0.0024 0.0043 0.0149 0.0533 0.0208 0.0213 0.0140 0.0154 0.0177 0.0194 0.0682 0.0513 0.0436 0.0877 0.1031 0.0143 0.0249 0.0236 0.0397

p=0.02 0.0296 0.0986 0.0409 0.0415 0.0275 0.0303 0.0347 0.0382 0.1183 0.0968 0.0830 0.1405 0.1660 0.0283 0.0487 0.0457 0.0739

automated synthesis approach that creates a minimum cost reliable circuit. The synthesis algorithm revolves around a decomposition method which given a PDD, f, finds appropriate g and h and probabilistic gate F such that f=F(g,h) i.e., inverse of composition. This decomposition is used recursively to completely synthesize the circuit. The challenge is to meet the reliability threshold while minimizing cost. REFERENCES
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Table 1. Output error probabilities and runtimes

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Comparison of our approach with [10] which currently is considered to be the state of the art shows overwhelming advantage (several orders of magnitude improvement in performance) of our proposed technique over [10]. Benchmarks misex3, duke2 and des resulted in the highest runtimes. It can be observed that the runtimes are not increasing only with respect to the number of gates. Further inspection of circuits with highest runtimes revealed that reconvergent fanouts in circuits cause the runtimes to increase. The results show that the proposed model scales reasonably well as the size of the circuit and its complexity increases. VI. CONCLUSIONS AND ONGOING RESEARCH In this paper a novel framework for analysis of probabilistic circuits was presented. The proposed PDD provides a compact and exact representation which allows for fast manipulation algorithms such as composing PDDs. The output probability for individual input states can be obtained from PDDs. This information can be used to build the probability table for the circuit. However some probabilistic behavior of the circuit can be obtained by extracting the desired information directly from the PDD (as opposed to creating the probability table from the model and then extract the information from the table) which allows for fast probabilistic analysis of the circuit. Experimental results demonstrated the scalability and effectiveness of the proposed approach. Our current research involves using PDD as a platform for developing synthesis algorithms for probabilistic circuits i.e., synthesizing a reliable circuit (output error probability less than a desired level) from given probabilistic gates while minimizing the cost (e.g., area, delay, etc.) Traditional approaches are based on predefined configurations such as modular redundancy and NAND multiplexing. However we are working on developing an

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