ADVANCED MICROPROCESSORS

UNIT-1 Introduction to Microprocessor:

The Microprocessor is a program controlled semiconductor device, which fetches, decodes & executes instructions, it is used as CPU in computers. BUS: A bus is a group of conducting lines that carries data, address & control signals. Buses can be classified into data bus, address bus & control bus.

The group of conducting lines that carries data is called data bus. The group of conducting lines that carries address is called address bus. The group of conducting lines that carries control is called control bus. The groups of conducting lines that are directly connected to Microprocessor are called CPU bus. In CPU bus the singles are multiplexed i.e. more than one signals are passed through same line but at different timings. The group of conducting lines that carries data address & control signals in a Microprocessor system is called system bus. Clock: A clock is a square wave, which is used to synchronize various devices in the Microprocessor & in the system. Every Microprocessor system requires a clock for its functioning. The time taken for the Microprocessor & the system to execute an instruction or program is measured only in terms of time period of its clock. Tri-state logic: Almost all devices used in the Microprocessor based system uses tri-state logic. Three logic levels will be available & they are high state, low state, & high impedance state. The high &low are normal logic levels for data, address or control signals. The high impedance state is electrical open circuit condition. The high impedance state is provided to keep the device electrically isolated from

the system. The tri state devices will normally remain in high impedance state & their pins are physical connected in the system bus but electrically isolated. In high impedance state they cannot receives or send any signal or information's. These devices are provided with chip enable/chip select pins. When the signals at this pins is asserted (arrived) to the right level, they come out from high impedance state to normal levels. A system designed using a Microprocessor as its CPU is called a Microcomputer or single board microcomputer.

Block diagram of Microprocessor based system or organization of Microcomputer.

The block diagram of microprocessor-based system is shown in the fig. In this system the microprocessor is master & all other peripherals are slaves. The control bus controls all operations. The buses are group of lines that carries data, address or control

singles. The CPU interface is provided to demultiplex the multiplex lines. The system bus has separate lines for each signal. All the slaves in the system are connected to the same system bus. At any time instant communication takes place between the master & slaves. All the slaves have tri-state logic & hence normally remain in high impedance state. The processor selects a slave by sending an address. When slaves are selected, it comes to the normal logic & communicates with processor. The EPROM memory is used to store permanent programs & data. The RAM memory is used to store temporary PROGRAMMEs & data. The I/p devices are used to enter the program, data & to operate the system. The o/p devices are used for examining the results. Since the speed of the I/p devices does not match with the speed of microprocessor, an interface device is provided between system bus & I/O devices. Genarally I/O devices are slow device.

The microprocessor is the master, which control's all the activities of the system. Features of 8086: 1. It requires a single+5v power supply. 2. It provides a full 16 bit bi-directional (receiving and sending data on same pin) data bus. The term "16 bit means that its ALU, internal registers & most of its instructions are designed to work with 16 bit binary words.
3.

The 8086 has a 20-bit address bus, so it can directly access 2 20 or 1048576 memory locations (1Mega byte). It can generate 16-bit I/O address; hence it can access 216=65536 I/O ports.

4.

5. It provides fourteen 16-bit registers. 6. It has multiplexed address & data bus, which reduces the number of pins, needed, but does slow down the transfer of data (draw back).

7. It is possible to perform bit, byte and word & block operations on 8086. 8. An interesting feature of the 8086 is that it fetches up to 6-instruction byte from memory & queues them in order to speed up instruction execution. 9. It provides powerful instruction set with the following addressing modes: register, immediate, direct, indirect through an index or base & index register.

8086 INTERNAL ARCHITECTURE

The 8086 central processing unit is divided into two independent functional units. (1) BUS interface unit. (2) Execution unit (EU). BUS interface unit(BIU): BUS interface unit is responsible for transfer of instructions, address and data on the system to the execution unit. It handles the transfer of data b/w the processor memory and I/O devices. It includes instruction fetch, data fetch, address transfer and computation of Effective address of the memory.

Functional parts of the bus interface unit are: 1. Instruction queue (IQ) 2. Segment Registers (SR) 3. Instruction Pointer (IP)

8086 Microprocessor internal block

Instruction Queue: It is of six bytes in length & is used to speed up the execution of programs, by pre-fetching six instruction bytes in advance from the memory. , The pre-fetched instructions are stored in a group of high-speed registers known as the Instruction Queue. The BIU works in parallel with the EU; the BIU fetches the instruction while the EU is executing an instruction. The simultaneous operations of BIU & EU are possible only when the EU does not require the system bus. The process of fetching the next instruction in advance while the EU is

executing the current instruction is known as pipelining. Principle of operation of the queue is FIFO.

Segment Register: BIU contains four 16-bit segment registers. They are 1. 2. 3. 4. Code Segment (CS) Register Data Segment (DS) Register Stack Segment (SS) Register Extra Segment (ES) Register.

These registers are used to store 16 bit starting address of the four memory segments. BIU generates a 20-bit address using the segment and the components of an address. BIU can address the memory locations starting from 000000h to FFFFFFH Instruction pointer (IP): It always holds the address of memory location (offset) of the next instruction to be executed. As the instruction is executed, the IP is advanced to point to the next instruction in the memory. IP is also called program counter in other microprocessor. Execution unit (EU): EU informs the BIU the location at which the next instruction or data is to be fetched. The phases of execution of the instruction are fetch, decode, execute and write. The fetch phase performs fetching of the instruction from the instruction queue. The decode phase performs the decoding of the instruction. The execute phase performs real operations on the data and write phase performs the operations of storing the computed result at the destination.

Functional Parts of EU are:

1. 2. 3. 4. 5. 6.

Control system and Instruction decode ALU Flag register General purpose register Stack pointer register Pointer and Index register.

1) Control Circuitry and Instruction Decoder : The control circuits of the EU direct all the internal operations of the processor. The instruction in the EU translates the instructions fetched from the memory into a series of actions carried out by EU. 2) ALU: It performs 8 bit or 16 bit mathematical operation such as addition, SUB, MUL, DIV data conversion & logical operation like NOT, OR & AND. It also performs register increment, decrement, and shift operations. 3) Flag Register: The 8086 processor has nine 1-bit flag to reflect the states of the CPU. The 16-bit flag register of 8086 stores the information about the states of processor and the status of the instruction executed most recently.

4) General purpose register(GPR): 8086 processor has four 16-bit GPRs. They are AX, BX, CX & DX. Each of the 16 bit register can be considered as high and low order bytes. They are AH, AL, BH, BL, CH, CL & DH, DL. 5) Stack pointer register: The register SP points to the current top of the stack. While register BP is used as the stack pointer. The SI and DI register are the source and destination index register respectively, used for manipulating strings.

6) Pointer and Index Register: The 8086 has another pointer register known as base pointer (BP) in addition to the Stack Pointer (SP) register. The register BP can be used as a pointer to a Memory Location (ML), and is similar to the register's BX, SI & DI. These registers are used for accessing the parameters from the stack in the procedures. SI and DI is used as a pointer to a ML, it is suitable for accessing the elements of an array from the memory.

Working principle of 8086

The EU obtains instructions from the Instruction pre fetch Queue (IQ) maintained by BIU and executes the instruction using a 16-bit ALU. Execution of the instruction involves maintains of the CPU status, the central logic, & manipulations of segment and offset address within the 16 bit limits. The BIU is also responsible for pre-fetching instructions from the IQ whenever possible to keep the EU busy with pre-fetched instructions

GENERATION OF 20 BIT ADDRESS (Physical Address Generation):Let us see how 20-bit address is generated by the BIU using the 16 bit IP contents. The address put on the 20-bit address line is called physical address (PA). The segment group registers and BX, BP, SP, SI or DI are 16 bits wide, the extra 4 bits are obtained by adding the effective address to the contents of one of the segment register. Let us say IP content is 123CH. This is called OFFSET value, or effective address (EA). Let the content of CS be 2345H. This is called the segment base value. The content of the CS register is multiplied by 16D (10H) i.e., shifted by 4 positions to the left to generate 20 bit starting address of code segment, i.e., code segment starts at 23450H. Thus the BIU adds up 23450H and 123CH using the adder on the BIU, and sends Out the sum 2468CH as the physical address (PA) on the 20 address pins.

Flag Register: The Flag is a flip-flop which will be in the 1 state or '0' state. Flag is only a one bit of information. Flags are of two types. They are 1. Status flag 2. Control flag. A Flag is set to 1 or resets to 0 by 8086 to indicate to the programmer, some situation like whether the execution of an instruction produced a -ve, +ve, or Zero result etc. Such flags are called Status flags. Some flags are deliberately set to 1 or reset to '0' by the programmer to control the working of 8086. Such flags are called the Control flags. The flag register is a 16-bit register in the EU, but only 9 bits are meaningful. The other 7 bits do not contain any useful information (as working with 16 bits is convenient for 8086, the register is also 16 bits wide). There are six status flags, they are 1. Zero 2. S (sign) 3. P (parity) 4. C (carry) 5. A (Auxiliary carry) 6. O (overflow) flags. The remaining 3 are the control flags, they are 1. D (direction) 2. I (interrupt enable) 3. T (trap) flags. Carry Flag (CF):- Carry flag is set to ' 1' if a carry resulted in the overall addition of the two numbers, for example; 9126H+ 1265H=A38BH with a carry 0, Therefore C flag is reset to '0', In the case of a subtract operation the C flag is set to ' 1', if we had to borrow in the overall subtract operation. Auxiliary flag (AF): - A flag is set if a carry resulted during the addition of the LS hex digits (carry from Lower nibble to next nibble). For example, the addition of 4 & E in LS hex position resulted in a carry,

Therefore flag is now set to 1 8086 makes use of this flag in DAA.

15 0

14

13

12

11 OF

10 DF IF

9 TF

8 SF

7 2F

3 PF

1 OF

Cf, PF, AF, ZF, SF, OF Arithmetic Logic Operation

Auxiliary Flag TF, IF, DF Control Bit

Zero flag (ZF): - Z flag is set to 1; whenever the result stored in a register or a memory location is zero otherwise it is reset to 0. For example, If The result stored in the register BX is 9162H, which is non-zero. As such the Z flag is reset to 0. Sign flag (SF): - Positive numbers are represented in an 8086-based computer with a 0 In the MS bit position & the remaining bits provide its magnitude. Ex. +3 is represented using 16 bits as 0000 0000 0000 0011=0003H Negative numbers are represented in 2's compliment form -3 is represented as 1111 1111 1111 1101=FFFDH Note that negative number always start with 1 in the MS bit position. S flag is set to 1 if the MS bit of the result stored in a register or a memory location is a 1. In other words, S flag is set to 1 if the result is negative It is reset to 0 if the result is positive. This flag is meaningful only if we are working with signed numbers. In case if it is unsigned numbers just ignore this flag. Overflow flag (OF): - It is set if an addition produces carry out of the MSB. In subtraction operation, it is set when the MSB needs a borrow & there is no borrow available from the MSB. This is known as underflow certain conditional jump instruction can transfer control to the target location based on the status of the overflow flag. Or is set to 1 if it is a wrong answer or is reset to 0 is it is a correct answer.

Parity flag (PF): - It is set to 1 if result of byte operation or word operation contains even number of ones, otherwise it is cleared. (BL) 04H (CH) FCH (BL) OOH ADDBL, CH = 0000 0000

Carry is resulted in the overall addition CF is set to 1. Since there was a carry generated in the addition LS hex digits, the AC flag is also set to 1 8-bit result stored in BL is OOH. Z flag is set to 1. The S flag is reset to 0, as OOH starts with a 0 in the MSB position. PF is set to 1 as OOH has 0 number (an even number) F 1's The O flag is also reset to 0, as the answer is correct.

Control Flags: - These flags are used to control certain operation of the processor.

Trap flag: one way to debug a program is to run the program one instruction at a time & see the contents of used registers & memory variables after execution every instruction. This process is called "Single stepping" through a program; Trap flag is used for single stepping through a program. If set, Interrupt service routine is executed which displays various registers & memory variable contents on the display after execution of each instruction. Thus programmer can easily trace and correct errors in the program. Interrupt flag (IF): - It is used to allow/prohibit the interruption of a program. If set a certain type of interrupt (a maskable interrupt) can be recognized by the 8086, otherwise these interrupts are ignored. Direction Flag (DF):-It is used with string instructions. If DF=0, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address.

Explain purpose of having segment registers:

The physical address of the 8086 is 20 bits wide to access 1 Mega byte Register locations are just 16 bits wide. Hence uses memory segmentation. It treats the 1 Mega byte of memory as divided into segments, with a maximum size of a segment as 64Kilo bytes. Thus any location within the segment can be accessed using 16 bits. These segment registers are used to hold the upper 16 bits & starting addresses of the 4 memory segments, on which 8086 works at a particular time.

Functions of Segment Registers: The CS (code segment) Register holds the upper 16-bits of starting address of the segment from which the BIU is currently fetching the instruction code byte. The SS (Stack segment) Register is used for the upper 16-bits of starting address for the PROGRAMME stack. (All stack related instruction will operated on stack) ES (Extra Segment) register & DS (Data segment) register are used to hold the upper 16-bits of the starting address of the two memory segments, which are used for data.

Advantages of Segmentations: 1. It allows the memory addressing capacity to be 1 Mega byte even though the address associated with individual instruction is only 16-bit. 2. It allows instruction code, data, stack & portion of PROGRAMME to be more than 64kilo byte long by using more than one code, data, stack & extra segment. 3. It facilitates use of separate memory areas for PROGRAMME, data & stack. 4. It permits a PROGRAMME or its data to be put in different areas of memory, each time the T 1M is executed i.e.. PROGRAMME can be relocated which is very useful in multi programming.

INSTRUCTION FORMATS - MEMORY ADDRESSING MECHANISM:-

The 8086 instruction varies from 1 to 6 bytes. The general instruction format is shown in figure.

Op-code occupies six bits and it defines the operation to be carried out by the instruction the operation to be carried out by the instruction.

D [register direction bit] occupies one bit. It defines whether the register operand is the source or destination. D=1 specifies that register operand if destination operand. D=0 specifies that register operand if source operand. Data size bit (N) defines whether the operation to be performed in a 8 bit or 16 bit. W=0 W=l byte operation byte operation 8 bit. 16 bit. byte 4 3 21 0 3
LOW Disp Data

1 byte 7 21 0

2-byte 7 6 5

byte byte byte 4

HIGH Disp Data

5
LOW Data

6
HIGH Data

Opcode

MOD

REG

RIM

TO use in EA Register Operand / reg Calculation

Register operand / extension Of code Register Mode / Memory Mode with displacement Word / byte operation W=0 8 bit byte W=1 16 bit byte Direction is to register D=0 Source register D=1 Destination Register

Operation Code Second byte of instruction usually identifies whether one of the operands is in memory whether both of are in register.

This byte contains 3 fields register/memory (R/M) field.

MOD

(field),

Register

field

(reg)

and

MOD 00 - Memory code with no displacement. 01 Only low order displacement is present [memory code with 8 bit Displacement]. 10 Memory code with 16-bit displacement. 11 Register mode. REG field occupies 3 bits; it defines register for the first operand, which is specified as the source or destination by D bit. REG 000 001 010 011 100 101 110 111 W=0 AL CL DL BL AH CH DH BH W=1 AX CX DX BX SP BP SI Dl

R/M occupies 3 bits; R/M field along MOD field defines second operand. MOD II REG 000 001 010 011 100 101 110 111 w=o AL CL DL BL AH CH DH BH W=1 AX CX DX BX SP BP SI Dl

If MOD=11 R/M identifies the second register operand. If MOD selects memory mode, then R/M indicates how effective address is to be calculated. BYTE 3 to 6:If an instruction are optional fields, that normally contain the displacement value of an immediate constants operand. Ex: MOV CH, BL 2n d byte
st nd

2 Byte

1 b yte

6 bit opcode for the instruction = 1OOO1O(base)

MOD=11 D bit = source operand D=0 , w=0 -> 8 bit operation Reg field of 2nd byte BL -> defined. BL = 011, R/M =101 1000 / 1000 1000 / 1000 1101 1101 BYTE 1 88DD(HEX)=88DDH

Addressing Modes:
The different ways that a processor can access data are referred to as addressing modes. The various 8086 addressing modes can be classified as, Addressing modes for accessing immediate and register data. (Register & immediate modes)

Addressing modes for accessing data in memory. (Memory modes) Program memory Addressing modes Stack memory addressing modes 1. Addressing modes for accessing immediate & Register data (register & Immediate modes) : Register addressing mode: This mode specifies the source operand, destination operand, or both to be contained in an 8086 register. Ex: MOV BX, CX; Copies the 16-bit contents of CX into BX. MOV CL, BL; copies 8-bit contents of BL into CL. Immediate addressing mode: In an immediate mode, 8 or 16 bit data can be specified as a part of instruction. Ex: MOV BL, 26H; copies the 8 bit data 26H into BL. MOV CX, 4567H; copies the 16-bit data 4567H into CX.

2. Addressing modes for the accessing data in memory (Memory Modes) We know that EU has direct access to registers. However EU cannot directly access the memory operands. It must use the BIU segment registers to access memory operands. Ex: when the EU needs to access a ML, it sends an offset value to the BIU. This offset is also called the Effective address (EA) Note that EA is displacement of the desired location from the segment base. There are five ways to specify EA in the instruction 1. 2. 3. 4. 5. Direct addressing mode. Register indirect addressing mode. Register relative addressing mode. Based indexed addressing mode. Relative Based indexed addressing mode.

Direct addressing mode: In this mode the 16-bit effective address is taken directly from the displacement field of the instruction.

The displacement (unsigned 16-bit or sign-extended 8-bit number) is stored in the location following the instruction operation code. Ex: MOV CL, [9823M] ; This instruction will copy the contents of the memory location. ; At a displacement of 9823H from the data segment base. ; Into the CL register here 9823 H is the effective address. : Which is written directly in the instruction. Register Indirect Addressing mode: In this mode the EA is specified in other pointer register or an index register. The pointer register can be either base register BX or base pointer register BP. And index register can be either SI or DI register. The 20-bit physical address is computed using DS and EA. Ex: MOV [DI], BX; the instruction copies the 16-bit Contents of BX into a memory location offset by the value specified in DI, from, The current contents in DS. For EX: [DS]=7205H, [DI] =0030H, [BX] =8765H,then after MOV [DI], BX Content of [BX] =8765H is copied to memory location 72080H & 72081H. [DS]=> 72050H (Adds 0H to LSB) to produce the required 20-bit physical address. [DI] 0030H 16-bit register. Physical address [DS]+ [DI]= 72050H+0030H= 72080H Register Relative addressing mode. In this mode EA is obtained by adding a displacement value to the contents of the pointer register. The segment registers used are DS & SS. When memory is accessed, the 20-bit physical address is computed from Si, DI, BX & DS. On the other hand, when the stack is accessed, the 20-bit physical address is computed from BP & SS. Ex: MOVAL, LAST [BX] ; EA is obtained by adding the value of LAST & [BX] ; The 20-bit physical address is produced from DS & EA.

Based Indexed Addressing mode: In this mode the EA is computed by adding a base register (BX or BP) and an index register (SI or DI).

Ex: MOV [SI] [BX], CL; 8bit content of CL is copied to 20bit physical Address. If [BX] =1530H, [SI]=1000H, & [DS] =4000H. = 42530H; DS+SI+BX

Relative Based Indexed Addressing mode: In this mode the EA is computed by adding a base register (BX or BP) and an index register (SI or DI), and a displacement. Ex: MOV TOT [SI] [BX], CL; 8bit content of CL is copied to 20bit physical Address. If [BX] =1530H, TOT-08H [SI]=1000H, & [DS] =4000H. = 42538H; DS+SI+BX+TOT.

3.

Program Memory Addressing modes : This is used with the JUMP and CALL instructions. It is classified as a) Direct program memory addressing mode Here store the address in the instruction itself EX: JMP 0000h b) Indirect program memory addressing mode Here address is stored in some other register EX: JMP BX c) Relative program memory addressing mode Here the relative address is added to the IP to get the final address. EX: JMP [2]

4.

Stack memory addressing modes: The stack memory is maintained by SP and SS. PUSH and POP instructions are available.

Assembler Directives
Directives are pseudo instructions and they assist the assembler in the assembly process and these statements are not translated into machine language. Directives are non-executable instructions used to pre-assign values, reserve storage, assign names to constants, form data structures, terminate a compilation etc. The assembler directives are classified into the following categories based on the functions performed by them are 1. 2. 3. 4. 5. 6. 7. 8. 9. Data definition & storage allocation directives. PROGRAMME organization directives. Alignment directives. PROGRAMME end directive. Value returning attributes directives. Procedure definition directives. Macro definition directives. Data control directives. Header files inclusion directives.

Data definition & storage allocation directives: Data definition directives are used to define the PROGRAMME variables & allocate specified amount of memory to them. The variables are building blocks of a program. They are of type BYTE, WORD, DWORD, Q WORD & TBYTE & there sizes in bytes are 1,2,4,8 & 10 respectively. The definition directives are DB, DW, DD, DQ, DT, and STRUCT & RECORD. DB (Define Byte): It is used to define a byte type variable. It can be used to define single or multiple byte variables. The range of values that can be stored in a byte is 0-255 for unsigned numbers. General form: Name of variable DB initialization value (S). Examples: a) TOTAL DB 0 The above statement informs the assembler to reserve one byte of memory for a variable named TOTAL & initialize with value zero during execution of the PROGRAMME.

b) TOTAL DB ? It informs the assembler to reserve one byte of memory for a variable TOTAL. Use of *?' in data definition informs the assembler that the value is unknown hence the variable TOTAL is not initialized. c) A CODE DB 'A' A CODE DB "A" It informs the assembler to reserve one byte of consecutive memory for a variable named A CODE & initialize with ASCII equivalent of a letter A. ASCII character should be enclosed within single or double quotes. d) TABLE DB 83, 100, 200, 55, 255 It reserves 5 bytes of consecutive memory location for variable TABLE & initializes them to 83, 100, 200, 55, 255. MSG DB ' HELLO WORLD' MSGDB 'H', 'E', L L, '0', 4 W', O, R, L,D, The above statement defines a variable MSG & reserves 12 bytes of consecutive memory location & initialize with the string 'Hello world' during execution of the PROGRAMME. CITYNAME DB 100 DUP ('_') CONT_NAME DB 50 DUP (?) The first statement defines a variable CITYNAME & reserves 100 bytes of consecutive memory location & initializes with the ASCII equivalent character '_'. In the second case, 50 bytes are allocated to the variable & they are not initialized. These definitions are similar to the array definition. BLIST DB 3, 2, 5, 5 dup (99), 88, 89 The above statement reserves 10 bytes of consecutive memory location & initializes them to 3, 2, 5, 99, 99, 99, 99, 99, 88, and 89. MATRIX DB 10 DUP (3 DUP (0), 1, 2, 3) The above statement reserves 60 bytes (6*10) of consecutive memory location & initializes them with sequence 0, 0,0, 1,2,3 & the sequence is repeated ten times. This statement is similar to defining a matrix of size 10*6 (char matrix

[10] [6]). With DUP, it is possible to reserve large constants because the assembler does not permit the statement to continue onto more than one line. DW: Define Word DW is used to define a word type 2 bytes variable. It can be used to define signal or multiple word variables. General form: Name of variable DW Initialization value (S) Ex: a) TWONUM DW "84" The above statement informs the assembler to reserve 2 bytes of consecutive memory for a variable named TWONUM & the first byte is initialized with the ASCII equivalent of '8' (38H) & hence the word contains the value 3834H. b) DW cannot be used to define a variable consisting sequences of more than two ASCII characters hence the statement NUM DW "123" causes an error "value out of range" c) In the statement NUM1 DW1 The first byte is initialized with ASCII equivalent of the decimal digit 1 (31H) & the second byte with zero, hence the word contains 003 1 H. d) TABLE DW 83, 100, 200, 55, 9255 It reserves 1 0 bytes of consecutive memory location for the variable TABLE & initializes them to those values.

e) BLIST DW 1003, 22, 5445, 5 DUP (99), 488, 6589 It reserves 20 bytes of consecutive memory location (5+5=10*2) & initializes them to those values. f) A, DW 100 DUP (0) It reserves 200 bytes of consecutive memory location & initializes all locations with zeros. g) MATRIX DW 10 DUP (5 DUP (0)) The above statement reserves 100 bytes [ 5*10=50*2 byte] of consecutive memory location & initializes with zeros.

h) PROCPTR DW HEX2ASC The above statement reserves 2 bytes of memory & initializes with a pointer to a procedure name HEX2ASC, which is useful in an indirect procedure call. DD: Define Double Word: It is used to define a double word type 4 bytes variable. It can be used to define a single or multiple double variables. General Form: Name of variable DD Initialization value (S) a) TWONUM DD "84" The above statement informs he assembler to reserve 4 bytes of memory location for a variable named TWONUM & the first byte is initialized with ASCII equivalent of'4', the second byte is initialized with the ASCII equivalent of 8', other bytes will be initialized & DD cannot be used to define a variable more than 2 ASCII characters. b) ADD 100 DUP (0) The above statement reserves 400 bytes of consecutive memory location & initializes all the word locations with zeros. DQ: Define Quad word: DQ is used to define an 8 bytes type variable. It can be used to define single or multiple quad word variables. General Form: Name of variable DQ initialization value (S) a) TWONUM DQ 84 It informs the assembler to reserve 8 bytes of consecutive memory location for a variable named TWONUM. It contains the value 00 00 00 00 00 00 38 34H. DQ cannot be used to define a variable consisting sequence of more than two ASCII characters. b) ADQ 100 DUP (0) It reserves 800 bytes of consecutive memory location & initializes all the word locations with zeros.

DT: Define Ten Bytes; DT is used to define ten bytes. The DT type variables are useful in math coprocessor instructions where large numbers are used in competition. General Form: Name of variable DT Initialization value (S) Ex: a) ADT 100 DUP (O) It reserves 1000 bytes of memory locations & initializes all the word locations with zeros. The first element array is at location 0, second is at location 10, third is location 20 etc. each element requires 10 bytes.

STRUCT: Structure Declaration: The directive STRUCT is used to declare the data type, which is a collection of primary data types (DB, DW and DD). The structure declaration allows the user to define a variable, which has more than one data type, General Form of structure declaration: Structure name STRUCT ; Sequence of DB, DW, DD directives for declaring fields. Structure Name ENDS; Structure Variable Definition: Structure declarations do not allocate memory space, but merely defines a pattern. Storage space is allocated only when structure variable is defined. General Form is Variable Structure name <Initializations> Accessing Structure Variable Fields: The structure variable fields can be accessed by using dot (*.') operator known as the structure access operator. It is placed between the structure variable and the field, which has to be accessed. Structure variable. Field name.

RECORD: The directive RECORD is used to define a bit pattern within a byte or a word. The record definition helps in encoding or decoding of bits for which some meaning assigned. General Form: Record Name Record Field specification 1... Field specification, where each field specification is of the form. Field Name: Length [= Initialization] where initialization field is optional.

Program Organization Directives:

8086 programs are collection of logical Segments. The directives used to organize the program segments are SEGMENT, ENDS, ASSUME etc. the segments can close program data, code or both. SEGMENT: The directive segment is used to indicate the beginning of a logical Segment. General Form: Segment Name SEGMENT [word/PUBLIC] The use of type specified WORD indicates that the segment has to be located at the next available word address, otherwise, the segment will be located at the next available paragraph. The type specific PUBLIC indicates that the given segment will be combined with other segments which have the same name. Ex: a) _DATA SEGMENT It is used with the name of the segment as follows __DATA SEGMENT ; Program data definition here _DATA ENDS MYCODE SEGMENT ; Program code here MYCODE ENDS

b) MYCODE SEGMENT PUBLIC

The above statement informs the assembler to combine the other segment, whose name is also MYCODE, ENDS: END OF SEGMENT The directive ENDS informs the assembler the end of the segment. The directives ENDS and SEGMENT must enclose the segment data or code of the program. General Form: Segment Name ENDS Ex: _DATA ENDS It is used with the name of the segment as follows. _DATA SEGMENT; Program data definition shuts here _DATA ENDS MYCODE SEGMENT ' program code shuts here

MYCODE ENDS ASSUME: The directive assumes informs the assembler the name of the logical segment that should be used for a specified segment. When program is loaded, the processor segment registers should point to the respective logical segments. General Form: ASSUME Seg Reg: Seg Name Where ASSUME is an assembler directive Seg Reg is any of the segment Register (CS, DS, SS & ES) Seg Name is the name of a user-defined segment. [Seg Name can be any valid symbol except the reserved keywords. The Symbols such as _CODE, _DATA etc are used as segments names. The symbols MY_CODE, PROSCODE, DATASEG, DATA_SEGMENT, MY_SEG, MYSTACK, _CODESEG1, FIRST_SEG etc are valid names of the SEGMENT.] Ex: a) ASSUME CS: _CODE In the above statement register, & symbol _CODE is an user defined segment name. ;

The directives ASSUME informs the assembler that instructions of the program are stored in the user defined logical segment _CODE. b) ASSUME DS: _DATA [DS is a data segment register] The directives ASSUME informs the assembler that the data of a program are stored in the used defined logical segment. c) ASSUME SS: _STACK [SS is a stack segment register] The directive ASSUME informs the assembler that the program's stack operations such as PUSH, POP etc references the user defined logical segment _STACK. d) ASSUME ES: _EXTRA [ES is the extra segment Register] It is the additional segment in which the program's data can be placed.

ALIGNMENT DIRECTIVES:
The alignment directives are used to control the location counter used by the assembler during machine code generation. They include EVEN and ORG. EVEN: Align as even memory address. The directive EVEN is used to uniform the assembler to increment the location counter to the next even memory address. If the location counter is already pointing to even memory address, it should not be incremented. ORG: Originate The directive ORG assigns the location counter with the value specified in directive. It helps in placing the machine code in specified location while translating the instructions into machine codes by the assembler. General Form: ORG [$+] Numeric value. The symbol indicates the current value of the location counter & it is optional. Example:1] ORG 100H: -The above statement informs the assembler to initialize the location counter to 100h.

The computer executable program next start at 00h location which can be done by using the statement ORG 100H in the beginning of program.

PROGRAM END DIRECTIVE

The program termination directive is used to inform the assembler the physical end of the program. It is performed using the directive END. END: - End of the program. The directive END informs the assembler that it is the physical end of the program Module. The assembler will ignore the statement after the directive END. The last Statement of every program must be an END directive. General form 1) END - It indicates END of the program. 2) END label - It informs not only the end of the program but also indicates that the execution program begins from the specified label 1.

VALUE RETURNING ATTRIBUTE DIRECTIVES

The task of programming can be made easier by assigning the assembler to compute the size of the data items. 1] LENGTH: - It informs the assembler above the number of elements in a data item such as an array. General form LENGTH variable Name. SIZE: - The directive size is same as LENSTH except that it returns the number of bytes allocated to the data item instead of number of elements in it. SIZE Variable Name. OFFSET: -The directive OFFSET informs the assembler to determine the displacement

of the specified variable with respect to the base of segment. It is usually used to load the OFFSET of a variable into the register. General form OFFSET Variable Name S EG: - Segment The directive SEG is used to determine the segment in which the specified data item is defined. General form SEG Variable Name TYPE:- It directive TYPE is used to determine the TYPE of data item. It determines the number of bytes allocated to the data type. Assembler allocates one byte to DB, two bytes to DW, and four bytes to DD type. General TYPE Variable Name. form

PROCEDURE DEFINATION DIRECTIVE

This directive is used to define subroutines. It offers modular programming constructs like PROC and ENDP. PORC: - Procedure The directive PROC indicates the beginning of a procedure. The directive PROC follows the name of a procedure. The term NEAR or FAR follows the PROC INDICATING the type of a procedure. If this term is discarded, then the assembler assumes NEAR as the type specifier. The directive PROC is used with the directive ENDP to enclose the procedure code. General form: - Procedure Name PROC {NEAR/FAR] Ex:a) HEX2ASC - PROC NEAR

The above statement defines the procedure HEX2ASC as NEAR type. It can be only be called within a segment. b) IF AT PROC FAR

The above statement defines the procedure IFAT as FAR type. It can be called from any segment. ENDP: - End of procedure The directive ENDP informs the assembler the end of a program. The directive ENDP and PROC must enclose the procedure code. General form Procedure Name

ENDP

Ex: - HEX2ASC ENDP It is used with the name of a procedure as follows. HEX2ASC PROC Do all procedure code stuff here RET ENDP HEX2ASC

MACRO DEFINITION DIRECTIVES

These are used to define macro constant and macro functions. The directives EQU, MACRO, and ENDM are used in the definition of a macro. EQU:- the directive EQU is used to declare the symbols to which some constant value is assigned. Such symbols are called as macro symbols. Macro assembler will replace every occurrence of the symbol in a program by its value. EQU Equate macro constant. General form Symbol Name EQU expression Ex: - a) NUM EQU 100 The above statement declares the symbol NUM with value 100. The assembler

will replace every occurrence of the symbol NUM by 100. MOV AX, NUM ^ Macro assemble MOV AX, 100

MACRO:- The directive macro informs the assembler the beginning of a macro. It consists of the name of a macro followed by the keyword MACRO and macro arguments if any. The directives MACRO and ENDM must enclose the definitions. General form MACRO Name Macro [argument 1.................argument N] Ex; - Print string macro message Code ENDM: - End of macro The directive ENDM informs the assembler the end of the macro. The directives MACRO and ENDM enclose the definitions, declarations or a small part of the code which have to substitute at the invocation of a macro. General form: - ENDM Ex: - Refer to the explanation of the directive MACRO.

DATA CONTROL DIRECTIVE

The data control directives are used to declare the variables and in command of information b/w the program modules. PUBLIC: The directive PUBLIC informs the assembler that the specified variable or segment can be accessed from the specified variable or segment can be accessed from other program modules by sharing the global variables or procedures. The variables and procedures to be shared must be declared as PUBLIC in a module in which it physically exists. General form: PUBLIC variable 1...variable N

Ex: - a) PUBLIC EXTRN: - EXTERNAL

XMAX, YMAX.

The directive EXTRN informs the assembler that the data items or label following be directive will be used in a program modules. General form Variable reference EXTRN Variable Name: Reference type... Variable Name: Reference type, PTR:- Pointer The directive PTR is used to indicate the type of memory access (BYTE/WORD/DWORD), for instance, if the assembler encounters the instruction like INC[SI], it will not be able to divide whether to code for byte increment are word increment. It can be resolved by using PTR directive with the instruction as INC BYTE PTR [SI] Ex: - a) INC BYTE [DI] The above statement increments the byte location pointed by DI BRANCH DISPLACEMENT DIRECTIVES There are used to control the branches displacement branch displacement. The branch directives are SHORT and LABEL SHORT:- The directive SHORT informs the assembler that one byte displacement is code a jump instruction. Normally two bytes are reserved to store the target address in the jump instruction. However the use of SHORT with jump will reverse one byte of memory there by saving the other byte of memory. Ex: - JMP SHORT SKIP

LABEL: - The directive LABEL assigns a name to the current value in the location counter. If the label is used as a designation in the jump or call instruction, the label must be specified as a near or far type when the label is used to reference the data item, the label must be specified as type byte, word or double word.

General form: LABEL Label Name Ex: a) LABEL A

Label Type A-REF DW WORD 100

The label A-REF can be used as a reference to the variable A.

Assembler instruction format:

A format for a typical line for assembly language PROGRAMME can be given as Label; Mnemonic operand 1, operand 2; comment The first field, which is optional, is the label field, used to specify symbolic labels. A label is an identifier that is assigned to the address of the first byte of the instruction in which it appears. The presence of a label is optional, but if present the label provides a symbolic name that can be used in branch instructions to branch to the instructions. The second field is mnemonic; all instruction must contain a mnemonic. The third & following fields are operands. The presence of the operands depends on the instruction. Some instructions have no operand, some have one, & some have two. If there are two operands, they are separated & continue to the end of line. They tell us what the program is trying to accomplish. The following example shows a typical 8086 assembly language instruction. AGAIN: ADD AX, price [BX]; add price of item to AX Here, label- AGAIN Mnemonic-> ADD Destination operand -> AX Source operand->BX Comment-> Add price of items to AX.

Rules for variable names: 1. Variables can have any characteristics. A-Z, a-z, _ (underscore), @, 0-9 of the following

2. A variable name must start with a letter (alphabet) or an underscore. The length of a variable name depends on the assembler. Normally the maximum length is 32 characters.
3.

There is no distinction between the upper & lower case letters. Variable names are case insensitive in 8086 assembly language.
4.

Examples of valid variables: Interest, city, data, number, num1, num2, total, next, big, India, and, total marks, average marks etc. Girl, GIRL, girl; assembler assumes all these as the same variable. Examples for invalid variables: $num1: variable name cannot start with a special symbol. $; It is reserved for indicating the address of the current instruction. $Num; Variable cannot start with a special symbol. Numeric constants: Numeric constants can be represented as binary or hexadecimal Integers. The number, which does not end with either the letter 'D', 'B', or H' is treated as a decimal number. A valid binary constant can have only digits 0 or 1 known as binary digits (bits). Hexadecimal numbers can have both digits (0-9) & characters (A-F). Ex: valid constants: 1010 decimal constants. 1010D decimal constants. 1010B Binary constant- 10 in decimal.

101 OH Hexadecimal constant. 923AH Hexadecimal constant. OF1H Hexadecimal constant. Invalid constants: 1021B Binary number must have 0 or 1 bit. OF1 hexadecimal number must end with the letter 'H' F1H treated as a symbol (therefore it must start with digits AO->symbol) 10DD v decimal number can have only digits between 0 & 9.

Instruction set
DATA TRANSFER INSTRUCTIONS Data transfer instruction generally involves two operations, the source and destination. The source can be a register or a memory location or an immediate data. The destination can be a register or a memory location. Both the source and destination cannot refer to memory locations in the same Instruction. They must be of the same data - type i.e., either of the type byte or type word. Data transfer instruction does not affect the CPU flags. MOV: Move Syntax: MOV designation, source immediate to register /memory Destination source

transfer data from register/memory

MOV AX, CX; copy contents of CX to AX MOV AH, AL ; copy contents of AL to AH MOV DS, AX ; copy contents of AX to SDS MOV AX, 100H ; copy immediate value 100H to AX MOV BX, [539BH] ; copy 16 - bit data from the M.L 530BH to BX register. MOV DL, [BX]; copy 8 - bit contents of M.L pointed to by the address Stored in BX to DL.

MOV BP, SS ;

copy contents of SS to BP.

XCHG: - Exchange Syntax: XCNG designation, source Exchange the contents of source and designation. Destination source Description: the instruction XCHG snaps (exchange) the contents of a source register or memory. The symbol AMOUNT used in the explanation of the following examples is considered as an array of type word with size 100 a follows. AMOUNT DB 10 dup (0)

Ex:1) XCHG AX, CX; Exchange the contents of AX and CX 2) XCHG AL, AMOUNT [BX]; Exchange (8 - bit) AL and memory AMOUNT [BX] 3) XCHG BL, AH; Exchange BL and AH IN: - input from port Syntax: IN accumulator, port (or DX); Input to AL (or AX) from I/O Port ; Byte AL [port] ; Word AL [port], AH [port] Description:The instruction IN reads data from the port and copies into the accumulator. An 8 - bit access to the port will place the data in AL register, while a 16 bit access to port will place data in AX register. The instruction IN has two formats. 1) Fixed port 2) Variable port. Each of then can again be classified into an 8 - bit or a 16 - bit access. FIXED PORT FORMAT:-

The address of a port is directly specified in the instruction. EX: - IN AL, OD8H; input a byte port OD8H to AL IN AX, 09AH; input a word port 09AH to AX ; let PIC_ port EQU 20H IN AX, PIC_ PORT; input a word from port PIC J>ORT to AX.

VARIABLE FORMAT:The address of a port is stored in the DX register before the instruction IN is executed. The advantage of the variable format IN instruction is the port address can be loaded dynamically during the execution of a program. Ex: - MOV DX, OF90H; Initialize DX with the port address OF70H. IN AL, DX; read 8 - bit value from port pointed by DX in AL IN AX, DX; read 16 - bit value from port pointed by DX in AX XLAT/XLATB: - Translate a Byte Syntax: XLAT/XLATB Translate AL into a value in a translation table at BX

Description: The instruction XLAT / XLATB replaces a byte in the AL register with a byte from the lookup table. Before execution of the XLAT instruction, BX should be loaded with the offset address of lookup table in the data segment (DS) and AL with the code to be converted. When XLAT is executed, the byte pointed to by (BX + AL) is transferred to the AL register. Ex: - MOV AL, CODE; initialize AL with the code to be converted. MOV BX, 2400H; initialize BX with the offset of the lookup table. XLAT ; replace AL with new code AL <r [BX + (AL)] LEA: - Load Effective Address Syntax LEA registers 16, source . .

load effective address into a register.

Description:The instruction LEA determines offset of a variable or NUL indicated as a

source address and places the offset in the specified 16 - bit register. The source operand must be a memory variable and the destination must be a 16 - bit general register. PUSH: - PUSH register or memory to stack Syntax PUSH source SP

SP - 2; SS: [SP]

source

Description:The instruction PUSH decrements the stack pointer (SP) by two and loads a word from the source to the location pointed to by SP. The source word can be a general purpose register (GPR), a segment register, a pointer, or a memory location. The SS and SP should be initialized before the use of PUSH instruction to the stack memory, this instruction is used to save data onto the stack for preserving the data and for passing parameter (S) to the procedure. Ex:PUSH AX; decrement SP by 2 and copy the contents of AX to the stack PUSH DX; decrement SP by 2 and copy the contents of DX to the stack POP: POP register or memory Syntax POP destination transfer to register 16 or R/W 16 forms the stack. destination SS:[SP]: Sp- Sp+2 Description: the instruction POP copies a WORD from the stack location to a specified WORD register or a word memory location and then SP is incremented by two. SHIFT AND ROTATE INSTRUCTIONS SHL: Shift Logical Left [(SAL) it is another mnemonic for the instruction SHL details is same as SHL] Syntax SHL destination, COUNT; the destination byte or a word is shifted left by the number of bits specified in the COUNT. ALL Flags are affected

Description: Zeros are shifted into the right most bit [LSB]. MSB bits are shifted out of the left most bit and placed in the CF. CF will contain the bit shifted in from the MSB. Bit stored in the CF previously will be lost. SHR: Shift Logical Right SHR destination, COUNT ; This instruction shift each bit in the specified destination to the right and zero is stored in the MSB position. The LSB is shifted into the carry flag. The destination can be a byte or a word. It can be in a register or in a memory location. The number of shifts is indicated by COUNT. The number of shifts required is 1, you can place 1 in the count position. But it the number of shifts are greater than one then shift count must be loaded in CL register and CL must be placed in the COUNT position.

All Flags are affected SAR instruction: SAR destination, COUNT The instruction SAR shifts the signed destination byte or a word right by the number of the bits specified in the count. As the destination operand bits are shifted right, the bit value in MSB [sign bit] is retained [preserved] so that the sign bit will not change. LSB bits are shifted out of the right most bit and placed in the CF. CF will contain the bit shifted in from the LSB. Bit stored in CF previously will be lost. All flags are affected.

ROTATE instructions

ROL instruction: ROL destination, COUNT This instruction rotates all bits in a specified byte or word to the left some number of bits positions. MSB is placed as a new LSB and a new CF. ROL CX,1; word in CX one bit position left, MSB to LSB and CF

MOL CL, 03H ; load desired number of bits to rotate in CL. ROL BL, CL ; rotate BL 3 positions. ROR ins1truction; ROR destination, COUNT This instruction rotates all bits in a specified byte or word to the right some number of bit positions. LSB is placed as a new MSB and a new CF,

RCL instruction: RCL destination, COUNT This instruction rotates all of the bits in a specified word or byte some number of bit positions to the left along with the carry flag. MSB is placed as a new carry and previous carry is placed as a new LSB. The destination can be a byte or word. It can be in a register or in a memory location. The numbers of shifts are indicated by count. If number of shifts required is one, you can place 1 in the count position. If numbers of shifts are greater than 1 then shift count must be loaded in CL register & CL must be placed in the count position. Ex:RCL CX, l; Rotated word in CX 1 bit left, MSB to CF, CR to LSB MOV CL, 04H; Load number of bit positions to rotate in CL. RCL AL, CL; Rotate L 4 bits left.

RCR Instruction: RCR destination, count. This instruction rotates all of the bits in a specified word or byte some number of bit positions to the left along with the carry flag LSB is placed as a new carry and previous carry is placed as a new MSB.

ARITHMETIC INSTRUCTION ADD/ADC Instruction: ADD destination, source these instructions add a number from source to a number destination and put

the result in destination. The ADC instruction also adds the status and carries flag into the result. ADD AL, OFOH; add immediate number OFOH to contents of AL ADC DX, BX; add contents of BX to contents of DX with carry and store result in DX i.e., DX = DX+ BX +CY. INC instruction: Increment destination. The INC instruction adds 1 to the specified destination The destination may be register or memory location. The AF, OF, PF, SF and ZF flags are affected. EX: - INC AL; add 1 to contents of AL INC BX; add 1 to contents of BX AAA: - ASCII adjust for addition The numbers from 0-9 are represented as 30-39 in ASCII code. When we want to add two decimal digits, which are represented in ASCII code, it is necessary to mask upper nibble (3) from the code before addition. But 8086 allows you to the ASCII codes for two decimal digits without masking off the "3" in the upper nibble of each digit. The AAA instruction can be used after addition to get current results in unpacked BCD form, the AAA instruction only work on the AL register. DAA instruction: - decimal adjust accumulator. This instruction is to make sure the result of adding two-packed BCD number is adjusted to be a legal BCD number. DAA only works for AL. SUB/SBB instruction: SUB destination/source SBB destination/source These instructions subtract the number in the source from the number in the destination and put result in the destination. Flags affected AF, CF, OF, PF, SF AND ZF. EX: - SUB AL, OFOH; subtract immediate number OFOH from contents of AL store result in AL. SBB DL, CL; subtract contents of CL and status of carry Flag from the contents of DL and store result In DL. I.e., DLDL-CL-CY

DEC instruction: - decrement destination the DEC instruction subtracts 1 from the specified destination. EX: - DEC AL; sub 1 from contents of AL DEC BX; sub 1 from contents of BX

NEG: From 2,s compliment This instruction replaces the number in a destination with the 2's compliment of that number. NEG AL; AL=0011 0101 35H. ; Replace number in AL with 2's compliment ; AL= 1100 1011=CBH. CMP: CMP destination, source This instruction compares a byte/word from the specified source with a byte/word from the specified destination. Subtracting the source byte or word does the comparison. But the result is not stored in the destination; source and destination remain unchanged only flags are updated. EX. CMP BL, 01H; compare immediate number 01H with byte in BL. CMP CX, BX; compare word in BX with word in CX. AAS instruction: ASCII adjusts after subtraction. The AAS instruction can be used after subtraction to get the current result in unpacked BCD form. DAS instruction: Decimal adjusts after subtraction. This instruction is used after subtracting two packed BCD numbers to make sure the result is correct packed BCD. MUL instruction: This instruction multiplies an unsigned byte from source and unsigned byte in AL register or in AX register. When a word is multiplied by the contents of AX, the most significant word of result is stored in AX. EX. MUL BL; AL*BH, result in AX. MUL BX; AL*BX, result high word in DX low word in AX. IMUL instruction: This instruction multiplies a signed byte from some and a signed byte in AL or signed word in AX. When a signed word is multiplexed by AX, the high-order word of the signal

result is put in AX. AAM instruction: BCD adjusts after multiply. After the two unpacked BCD digits are multiplexed the AAM instruction in used to adjust the product to two unpacked BCD digits in AX. DIV instruction: This instruction is used to divide an unsigned word by a byte or to divide an unsigned double word by a word. EX. DIV BL; AX/BH, result in AX, ie. AL=Q & AH=R. DIV BX; DX:AX/BX, result in AX=Q & DX=R.

IDIV instruction: This instruction is used to divide a signed word by a signed byte or to divide a signed double word by a signed word. AAD instruction: Binary adjusts before division. AAD converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before division.

Bit Manipulation Instruction (Logical instructions): NOT: NOT destination The NOT instruction invert each bit of a byte or a word. The destination can be register or a memory location, EX. NOT AL; AL=01101100 ; AL=10010011. AND instruction: This instruction logically Ands each bit of the source byte or a word with the corresponding bit in the destination and stores result in destination. AND destination, source AND BL, AL; AND byte in AL with byte in BL.

Loop control instruction: These instructions are used to execute a series of instructions some number of times. The number is specified in the CX register. The CX register is automatically decremented by one each time after execution of loop instruction. Until CX =0, execution will jump to destination specified by a label in the instruction. Instruction code 1 Loop 2 Loop E/Loop Z 3 Loop NE/loop NZ Description Condition for exit

Loop through a sequence of CX-0 instructions Loop through a sequence of CX=0 OR ZF=0 instructions " Loop through a sequence of CX=OORZF=1 instructions

Processor control instructions: STC: This instruction sets the carry flag; STC does not affect any other flag. CLC: this instruction resets the carry flag to zero. CLC does not affect any other flag. CMC: This instruction compliments the carry flag. CMC does not affect any other flag. STD: This instruction is used to set direction flag to one so that SI &/or DI can be decremented automatically after execution of string instructions. CLD: this instruction is used to reset the direction flag to zero, so that SI/DI can be incremented automatically after execution of string instructions, CLD does not affect any other flag. STI: This instruction sets the interrupt flag to one this enables INTR interrupt of the 8086. STI does not affect any other flag.

STRING: REP/REPE/REPZ/REPNE/REPNZ instruction REP is a prefix, which is written before one of the string instruction.

These instructions repeat until specified condition exit.

Instruction code REP REPE/REPZ REPNE/REPNZ

Condition for exit cx=o CX=0 OR ZF=0 CX=OORZF=1

MOVS/MOVSB/MOVSW instruction: This instruction copies a byte or word from allocation in the data segment to allocation in the extra segment. CMPS/CMPSB/CMPSW instruction: A string is a series of the same type of data items in sequential memory locations. The CMPS instruction can be used to compare byte in one string with a byte in another string. SCAS/SCASB/SCASW INSTRUCTION: SCAS compare a string byte with a byte in AL or a string word with word in AX. LODS/LQDSB/LODSW instruction: This instruction copies a byte from a string location pointed by SI to AL, LODS does not affect any flags. STQS/STOSB/STOSW: Store string instructions.

Pin Details of 8086

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

VCC

AD15

40 39 38 37 36 35

AD15 AD16 / S3 AD 17 / S4 AD 18 / S5 AD19 / S6 BHE / S7 MN / MX RD HOLD HLDA WR M / IO DT / R DEN ALE INTA TEST READY RESET

8 0 8 6

34 33 32 31 30 29 28 27 26 25 24 23 22 21

Ready: 8086 generally needs 4 clock cycles for writing/reading information to from memory/i/o ports. These 4 clock cycles in which the microprocessor performs a read or write operation is called a machine cycle. AD15-AD0: As 8086 is a 16-bit microprocessor; it has 16 data pins, D15-D0, which are bi-directional. 8086 receives 16 bits of information on these pins from memory m I/O ports, manipulates the information internally, & then

sends out 16-bit result to memory or I/O ports on the same pins. If it is desired, 8086 can also work on 8-bit information. The pins AD15-AD0, Which are used for data as well as LS 16 bits of address .1 word=16bit=2byte. A19-16/s6-3: Pins A19-A16 provides the most significant (MS) 4-bits of memory address during the first clock cycle. RD: The RD pin is an active low o/p pin. Whenever the microprocessor needs to get information from a memory location or an I/O port, it activates the RD pin. BHE/S7: During the first clock cycle TI of a machine cycle the microprocessor uses this pin to send out Bus high enable. NMI & INTR: In a microcomputer system whenever an I/O port wants to communicate with the microprocessor urgently, it interrupts the microprocessor. In such a case microprocessor completes the instruction it is presently executing. Then it saves the address of the next instruction on the stack top, & branches to an ISS (Interrupt Service Subroutine) to service the interrupting I/O port. After completing the ISS, 8086 returns to the original PROGRAMME, by making use of the address that was saved on the stack top. 8086 have two interrupt pins (1) NMI (2) INTR. INTR: Interrupts is an input pin to 8086, & is an active high signal. Whenever an external device activates this pin, the microprocessor will be interrupted only if the interrupts are enabled using a STI (Set Interrupt Flag) instruction. It interrupts are disabled using CLI instruction, the microprocessor will not get interrupted even if INTR line gets activated by an external device. In other words, INTR can be masked; INTR is a non-vectored interrupt. This means, the 8086 does not know where to branch, to service the interrupt. NMI: Stands for Non Mask able interrupt, it is an I/p pins to the 8086 & is active high signal. Whenever an external device activates this pin, the microprocessor will be interrupted. CLI & STI instructions have no effect on NMI. In other words, this signal cannot be masked. NMI is a vectored interrupt, this means, 8086 knows where to branch, to service the NMI Interrupt. If both NMI & INTR are obtained at the same time. NMI will be serviced first. Thus NMI has a higher priority than INTR Reset: When a 1 sent into 8086 on the reset pin, for at least 4 clock cycles, the 8086 microprocessor gets reset. That is it starts from a clearly defined initial state Only. NMI can interrupt the 8086 after a reset. When the reset button on the microcomputer is momentarily pressed & then released the reset pin activated for a few clock cycles.

MN/MX: In simple systems with a single microprocessor, all the control signals needed in the microcomputer system can be directly generated by the 8086. But in more complex systems, especially those containing arithmetic co-processor like Intel 8087, I/O processors like Intel 8089, & multiple processors more number of control signals are required to be generated for proper interaction among them. However 8086 has only 40 pins. This problem is solved by allowing 8Q86_to work in 2 different modes called the maximum and minimum modes. This is indicated by the input pin MN/MX. In a simple system, where 8086 is the only processor, we connect MN/MX pin to +5 volts. In such a case 8086 directly generates all the control signals needed in the system. In complex systems, we connect MN/MX pin to ground. In this case pins 24 to 31; a total of 8 pins will have different functions in min & max modes. Functions of pins 24 to 31 in minimum mode: WR: The WR pin is an active low output pin. Whenever the Microprocessor needs to write information to a M.L or to an I/O port, it activates the WR pin. M/IQ: it is an output pin, whenever the Microprocessor wants to communicate with memory; the Microprocessor outputs a 1 on this pin. If the Microprocessor wants to communicate with I/O ports it outputs a '0' on this pin. ALE: ALE stands for Address Latch Enable. This is an output pin. The 8086 send out a 1 on this pin during T1 clock cycle of a machine cycle. INTA: Interrupt Acknowledge, this pin is related to non vectored interrupt INTR. Whenever INTR input pin is activated by an I/O port, if interrupts are enabled,& NMI is not active at the same time the Microprocessor finishes the instruction it is executing & gives out a '0' on INTA. HOLD and HLDA: In 8086 there are no instructions to transfer data directly b/w memory and I/O port have to communicate via the processor. Ex: - If data has to be moved from memory to an I/O port, it has to be first moved from memory to the Microprocessor and then from Microprocessor to I/O port. This kind of data transfer involving the Microprocessor is called programmed data transfer. The process of an I/O port accessing memory directly, without passing data

through the Microprocessor is called Direct Memory Access or DMA. DMA data transfer is essential when large amount of data has to be transferred between a fast peripheral, like disk controller and memory. A DMA controller like Intel 8237 can be used for programming DMA data transfer in a microcomputer system. The DMA controller activates the HOLD input of 8086, whenever DMA data transfer is requested by an I/O port. When the 8086 finds that the HOLD pin is active, it tri-states the address bus, data bus & the control signals & enters the HOLD state, where the condition of the microprocessor is frozen, i.e. the contents of the various registers inside the microprocessor remains the same for the duration of the HOLD state. The microprocessor indicates the DMA controller that it has entered the HOLD state, by sending out HLDA signal. DT/DEN: Most of the devices like EPROM, RAM, & I/O ports which are connected to the buses have MOS inputs, so they do not draw current from the power supply. However each device added to the system adds a few Pico farads of capacitance b/w a signal line & ground. In order to change the signal level from a '0' to T all this added capacitance must be charged. Similarly, to change from T to '0' on a signal line, all this capacitance must be discharged. If we connect more than a few devices on the data bus, the 8086 outputs are not capable of supplying enough current drive for performing this charging and discharging at a fast rate. Then bi-directional buffers, also called transceivers like Intel 8286 are used on the data bus to increase the current driving ability. DT/R: The DT/R is an output pin of 8086, which is activated in T1 of a machine cycle. If the 8086 outputs a ' 1' on this pin, it means the buffers are used to transmit the data from the 8086. If the 8086 outputs a '0' on this pin, the buffers are set up so that the 8086 receives the data from the buffers. When 8086 outputs a '0' on DEN, a little while after ALE is made '0' so that the data on the data pins are settled, the buffer O/P is placed on the data bus.

Test: Let us say, the 8086 is used in maximum mode & is required to wait for some result from the co-processor 8087 before proceeding with the next instruction. Then we can make the 8086 execute the wait instruction. Then

the 8086 enter in to an idle state, where it is not performing any processing. The 8086 will stay in this idle state till Test input of 8086 is made '0' by the coprocessor, indicating has finished its computation. Thus the Test signal is used for synchronizing the 8086 with external H/W such as co-processor. Minimum Mode for 8086 Microprocessor

WR: -The WR pin is an active low o/p pin. Whenever the microprocessor needs to write information to a memory location or to an I/p port, it activates the WR pin. M/IO: - it is used to differentiate memory access & I/O access. For in & out instruction it is low. For memory reference instructions it is high. ALE:-It is to duplex the address & data lines using External latches. AD0 AD15

RD MN/MX = VCC HOLD HLDA

A16 A19/ S3-S6 BHE / S7

INTR NMI CLK

WR

8086 MINIMUM MODE

M/IO DT/R DEN ALE INTA

VCC GND TEST READY

INTA: - The 8086 o/p is low on this line to acknowledge when the interrupt request is accepted by the processor, when INTR I/p pin is RESET activated by an I/p port, it interrupt are enabled, & NMI is not active, at the same time the microprocessor finishes the instruction it is executing & gives out a '0' on INTA.

HOLD:-It is an I/p signal to the processor for other bus wasters as a request to grant the control of the bus .It is usually used by DMA controller to get the control of the bus. HLDA: -when the 8086 finds that hold pin is active it tri-states the address bus, data bus & the control signals & enter the HOLD state, where the condition of the microprocessor is frozen, i.e. the content of the microprocessor remains the same for the duration of the HOLD state. The microprocessor indicates the DMA controller that it has entered the HOLD state by sending out HOLD signal. DEN :-( Data enable) it is an o/p signal from the data transceivers. Most of the devices like EPROM; RAM & I/O ports, which are connected to the buses, have MOS (Metal Oxide Semiconductor) I/p so they do not draw current from the power supply.

However each device added to the system adds a few pico-fareds of capacitance between a signal line & ground. In order to change the signal level from a '0' &' 1' all the added capacitance must be charged similarly, to change from T to '0' on a single line, all this capacitance must be discharged. If we connect more then a few devices on the data bus, the 8086 o/p's are not capable of supplying enough current drive for performing this charging & discharging at a fast rate. The bi-directional buffer also called transceivers Like Intel 8286 & are used on the data bus to increase the current driving ability. DI/R: - it is an o/p signal from the processor to control the direction of data flow through the data transceivers.

Explain the function of test pin in 8086? Let us say, the 8086 is used in maximum mode & is required to wait for some result from the co- processor 8087 before proceeding with the next instruction. Then we can make the 8086 execute the wait instruction. Then 8086 enter a state where it is not performing any processing. The 8086 will stay in this mode still test i/p of 8086 is made '0' by the co-processor, indicating it has finished its computation, thus the test signal is used for synchronizing the 8086 with external hard ware such as co- processor. Maximum Mode for 8086 Microprocessor

The 8086 based system can be made to work in maximum mode by grounding the MN/MX pin. In maximum mode the pins 24-31 are redefined as follows.

SO, S1, S2: -These are status & they are used by the 8288 bus controller to generate bus timing & control signals. RQ/GTO :-( Bus request /bus grant) these requests are used by the other local bus nearest to force the processor to release the local bus at the end of the processor's current bus cycle. These pins are bidirectional. The request on GTO will have higher priority than GT1.

AD0 AD10 RD A16 A19/ S3-S6 BHE / S7 MN/MX = 0V

/ GT1
RQ /GT0

RQ

INTR NMI CLK

LOCK

8086 MAXIMUM MODE

S2 S1 S0 QS1 QS0

VCC TEST GND READY RESET

LOCK:

-it is an o/p signal, activated by the lock prefix instruction & remains active until the completion of instruction lock. The 8086 o/p low on the lock pin while executing an instruction by lock to prevent other bus master from gaining control of the system bus.

QS1-QS0: -The processor provides the states of the queue on these lines. The queue status can be used by external device to track the internal status of the queue in 8086.the qs0 & qs0 are valid during the elk period following any queue operation. The o/p on QS1&QS0 can be interrupted as shown in the table. Queue QS1 0 0 1 1 Status QSO 0 1 0 1 No operation First byte of an opcode from queue Empty the queue Subsequent byte from queue Queue operation

INTERRUPTS AND VECTOR TABLE An interrupt is a signal that informs the CPU to temporarily halt its current activates and transfers control to a program called interrupt. When a microprocessor is interrupted, it stops executing its current program and calls a special routine, which its current program and calls a special routine, which "services" the interrupt. The event that causes the interruption is called interrupt and e special routine, which is executed, is called interrupt service routine. After completing IRS the microprocessor returns to the original program by making use of the return address that was saved on the stack top. Normal program can be interrupted by three ways. 1) By external signal 2) By a special instruction in the program 3) By the occurrence of some condition. An interrupt caused by an external signal is referred as hardware interrupt. Conditional interrupts or interrupts caused by special instructions are called software interrupts. Based on the source of the interrupt, 8086

interrupts are classified as 1) Hardware interrupt 2) Software interrupt 3) Exception interrupt HARDWARE INTERRUPTS:These are generated from an external signal applied to the non mask able interrupt (NMI) or interrupt input (INTR) of the 8086. the INTR can be disabled by clearing interrupt flag in the flag register. I.e., if is cleared CPU does not respond to the signal on the INTR line. Hence INTR is called as maskable interrupt. INTR is nonvectored input; this means the 8086 does not know where to branch to service the interrupt. The 8086 has to be told by an external device like PIC (programmable interrupt controller) regarding the branch to be made. NMI is a vectored interrupt. That means the 8086 knows where to branch to service the NMI input. NMI has higher priority than INTR. For NMI interrupt type no is 2.

SOFTWARE INTERUPT Besides b/w interrupts, the processor can also handle special instruction known as software interrupt instruction. Software interrupts are never disabled. The software interrupts do not acknowledge other chips in the computer system. The software interrupt in the 8086 family is called INT and is given an interrupt no (N). And it given by INT N. Where N is the type of number ranges from 00 to FFH. For each interrupt two words are needed to indicate the IP and CS values. The first word always represents the value for IP and second word for CS for each interrupt. The interrupt vector for interrupt type 0 is at location OOOOOH, for interrupt type 1 is at location 00004H etc., In general the interrupt vector for interrupt type N is at location N x 4. EXCEPTION INTERRUPT ACTIONS:-

Exception interrupt is a signal from some condition generated in the 8086 by the execution of an introduction. Divided by 0 interrupt is an example of exceptional interrupt. An attempt to perform division by 0 will automatically interrupt the execution of the program. Single step interrupt is another example of an exception interrupt. Here the processor executes an instruction and waits for the user to respond. The trap flag in conjunction wit type 1 interrupt will enable the user to implement the single step execution if useful in examining the contents if the registers and ml after the execution of each instruction. INTERRUPT ACTIONS At the end of each instruction cycle 8086 checks to see if there is any interrupt request. If so 8086 responds to the interrupt by performing serves of actions. The 8086 interrupt response is as shown in figure. If decrements stack pointer by 2 and pushes the flag register on the stack. It disables the INTR interrupt input by clearing the interrupt flag in the register. It resets the trap flag in the flag register. CS value of the return address is pushed on to the stack. IP value of the return address is pushed on to the stack. IP is loaded from the contents of word location N x 4. CS is loaded from the content of next word location N x4 +2. An INTR instruction at the end of interrupt service procedure returns execution to the main program.

The following actions taken place when the return instruction in the subroutine is executed. It retrieves the top of the stack to IP. It retrieves the next word of the stack to CS. It retrieves the next word of the stack to flag register. 8086 interrupt vector table

33FFH 3FCH Available Interrupt Pointer (224)

Type -225 Available

Pointer

084H 080H

Type - 33 pointer Available Type - 32 pointer Available Type -31 pointer Available

Reserved Interrrupt Pointer ( 27)

07FH

014H 010H Dedicated Interrupt Pointer

Type - 5 pointer ( reserved ) Type -4 pointer Over Flow Type -3 byte pointer Over Flow INS Instruction Type -2 Pointer Non-Maskable Type 1 Pointer SINGLE STEP Type -0 Pointer DIVIDED ERROR

006H 008H 004H 000H

8086 gets the new values of CS and IP register from 4 memory addresses.

When it responds to an interrupt, the 8086 goes to memory location to get the CS and IP values for the start of interrupt service routine. In an 8086 system, the first 1 KB of memory from OOOOOH to 003FFH is reserved for storing the starting address of interrupt service routines.

This block of memory is often called the interrupt vector table or the interrupt pointer table. Since 4 bytes are required to store the CS and IP values for each interrupt service procedure, the table can hold the starting addresses for 256 interrupt service routines. The above figure shows how the 256-interrupt pointers are arranged in the memory table. Each interrupt type is given a number b/w 0 to 255 and the address of each interrupt is multiplying the type by 4(N x 4)] Ex:- For type 11, interrupt address is 11 x 4 = 44(decimal) = 0002CH. For type 2, 2 x 4 - 8 - 008H. Only first five type have explicit definitions such as divide by 0, NMI The next 27 interrupt types, from 5 to 31 are reserved by Intel for use in further microprocessors the upper 224 interrupt types, from 32 to 255, are available for user for hardware or software interrupt, when the 8086 responds to an interrupt, it automatically goes to me specified location in the interrupt vector table to get the starting address of interrupt service routine. So user has to load these starting addresses for different routines at the starting of program.

Comparison between 8086 & 8088:

SN.No Microprocessor 8088 Microprocessor 8086 1 It has only 8 data lines therefore, it It has 16data lines therefore it has ADO-AD7 & A8-A15 signals was ADO-AD15 signals. 2 As data bus is 8-bit wide, it doesn't It has BHE signal to access have BHE signal higher byte. In minimum mode assigned to IO/M its 28 pin In Minimum mode its 28 pin is assigned to signal M/IO

3 4

It has 4-byte instruction queue, due It has 6-byte instruction queue. to 8-bit data bus. Instruction fetching is slow & 4 bytes are sufficient for queue. Its pin number 34 is SSO, It acts as SO in the minimum mode. In minimum mode .In minimum mode should be used to mode, SSO pin is always 'high' Its pin number 34 is BHE/ S7 during Tl BHE should be used to enable data on to the most Significant byte of the data bus. During T2, T3 & in the status of this pin is logic ' 0'. In maximum mode, 8087 Monitors this pin to identify CPU as an 8088 or 8086.

BASIC FEATURES OF 8087 CO - PROCESSOR 1) It can operate on data of the integer, decimal, and real types with lengths ranging from 2 to 10 bytes. 2) Its instruction set not only includes various forms of addition and subtraction, but also provides many useful functions such as square root, exponential, tangent and soon. 3) It is high performance numeric data processor.

4) It can multiply two 64-bit real numbers in about 27 microseconds and calculate square root in about 36 microseconds. 5) It is multi bus compatible. 8086 does not provide any intrinsic support for operations on floating point numbers. If it is possible using 8086 it takes a long time and it will be a slow computation. But if speed becomes important, it is necessary to use the dedicated numeric co -processor Intel 8087, to speed up the matters. 8087 is also variously termed as arithmetic co - processor, math co processor, numeric processor extension, numeric data processor, floating point processor etc., We can have a microcomputer with 8086 as the only CPU. But we cannot have a microcomputer with only 8087 as the CPU. Thus the 8087 is termed a co - processor rather than a processor. The 8087 maths co -processor or designed to specifically work with 8086 and 8088 processors. 8087 is fabricated using HMOS III technology and packed in a 40-pin dual in line package. 8087 has its own internal registers. Information is always stored inside 8087 using floating-point notation. Its instruction set includes simple floating point operations like add, divide etc., as well as more complex operation like logarithm of a number etc. there are no instructions in the instruction set of 8086 or 8087 to perform data transfer directly b/w the register of 8086 and 8087.