Fpga Implementation of Fir Filter

FPGA IMPLEMENTATION OF FIR FILTER
A PROJECT REPORT
Submitted by
Milind Kumar Agrawal 0801214220
Debashis Kar 0801214225
Abhisek Mishra 0801214226
Sudhir Kumar Sharma 0801214235

Under the Guidance of
Ms. Priyanka Subudhi
(Professor, Electronics & Telecommunication Engineering)
In partial fulfillment for the award of the degree
Of
BACHELOR OF TECHNOLOGY
IN
Electronics &Telecommunication Engineering

KONARK INSTITUTE OF SCIENCE AND TECHNOLOGY,
BHUBANESWAR
BIJU PATTNAIK UNIVERSITY OF TECHNOLOGY,
ROURKELA
DECEMBER 2011
CERTIFICATE

This is to certify that the thesis entitled FPGA Implementation of FIR
Filter submitted by Milind Kumar Agrawal, Debashis Kar, Abhisek
Mishra, and Sudhir Kumar Sharma in partial fulfillment of
requirement of B-Tech degree in Electronics and Telecommunication
Engineering at Konark Institute of Science and Technology is an
authentic work carried out by him under my supervision and
guidance.

Date: Ms. Priyanka Subudhi
Place: (Professor)

ACKNOWLEDGEMENT
This thesis would not have been possible without the inimitable
support and guidance of many individuals. Even though mere words
cannot quality the help that they have given us, we shall yet attempt
to thank them in this feeble manner.
The invaluable advice and support given by Ms. Priyanka
Subudhi has inspired us to broaden our horizon and accomplish tasks
that we never thought were possible. She believed in us even when
we did not believe in ourselves.
Our sincere thanks to Head of the Department, for his constant
encouragement and support in our endeavor to understand our area
of project, he taught by example and we have learnt a tremendous
amount with our interactions with him.

Milind Kumar Agrawal
Debashis kar
Abhisek Mishra
Sudhir Kumar Sharma

ABSTRACT

Finite impulse response filter (FIR) filter is key functional block in the field of
digital signal processing. A number of implementations can be found in the
public literature either by software or hardware solution. In the VLSI
implementation, the hardware complexity of the FIR filter is directly
proportional to the tap length and bit width of i/p signal. Implementing
hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable
task. There is more than one way to implement the digital FIR filter. Based on
the design specification, careful choice of implementation method and tools can
save a lot of time and work. Matlab is an excellent tool to design filters. In this
project Matlab is used to find the co-efficient of FIR filter as well as frequency
response to satisfy the design specification. Time can be spent evaluating
different implementation alternatives. Proper choice of the computation
algorithms can help the FPGA architecture to make it efficient in terms of speed
and/or area.

1 INTRODUCTION

1.1 Why implement the digital filter?

Digital filters are used extensively in all areas of electronic
industry. This is because Digital filters have the potential to attain much
better signal to noise ratios than analog filters and at each intermediate
stage the analog filter adds more noise to the signal, the digital filter
performs noiseless mathematical operations at each intermediate step in
the transform. As the digital filters have emerged as a strong option for
removing noise, shaping spectrum, and minimizing inter-symbol
interference in communication architectures. These filters have become
popular because their precise reproducibility allows design engineers to
achieve performance levels that are difficult to obtain with analog filters.
FIR and IIR filters are the two common filter forms. A drawback of
IIR filters is that the closed-form IIR designs are preliminary limited to
low pass, band pass, and high pass filters, etc. Furthermore, these
designs generally disregard the phase response of the filter. For
example, with a relatively simple computational procedure we may
obtain excellent amplitude response characteristics with an elliptic low
pass filter while the phase response will be very nonlinear. In designing
filters and other signal-processing system that pass some portion of the
frequency band undistorted, it is desirable to have approximately
constant frequency response magnitude and zero phases in that band.
For casual systems, zero phases are not attainable, and consequently,
some phase distortion must be allowed. As the effect of linear phase
with integer slope is a simple time shift. A nonlinear phase, on the other
hand, can have a major effect on the shape of a signal, even when the
frequency-response magnitude is constant. Thus, in many situations it is
particularly desirable to design systems to have exactly or approximately
linear phase.
Compare to IIR filers, FIR filters can have precise linear phase.
Also, in the case of FIR filters, closed-form design equations do not
exist. While the window Method can be applied in a straightforward
manner, some iteration may be necessary to meet a prescribed
specification. The window method and most algorithmic methods afford
the possibility of approximating more arbitrary frequency response
Characteristics with little more difficulty than is encountered in the design
of low pass filters. Also, it appears that the design problem for FIR filters
is much more under control than the IIR design problem because there
is an optimality theorem for FIR filters that is meaningful in a wide range
of practical situations.

The magnitude and phase plots provide an estimate of how the
filter will perform; however, to determine the true response, the filter
must be simulated in a system model using either calculated or recorded
input data. The creation and analysis of representative data can be a
complex task. Most of the filter algorithms require multiplication and
addition in real-time. The unit carrying out this function is called MAC
(multiply accumulate). Depends on how good the MAC is, the better
MAC the better performance can be obtained. Once a correct filter
response has been determined and a coefficient table has been
generated, the second step is to design the hardware architecture. The
hardware designer must choose between area, performance,
quantization, architecture, and response.

1.2 Design and implementation of digital FIR filter

MATLAB combines the high-level, mathematical language with an
extensive set of pre-defined functions to assist in the creation and
analysis of filter data. Toolbox are available for designing filter response
and generating coefficient tables, each with varying levels of
sophistication. Graphical filter design tools provide selections for
specifying pass band, filter order, and design methods, as well as
provide plots of the response of the filter to various standard forms of
inputs. FDA tool from The Math Works, which can generate a behavioral
model and coefficient tables. Once a correct filter response has been
determined and hardware architecture has been defined, the
implementation can be carried out. Three choices of technology exist for
the implementation of filter algorithms. These are: a Programmable DSP
chip, ASICs and FPGAs At the heart of the filter algorithm is the multiply-
accumulate operation; Programmable DSP chips typically have only one
MAC unit that can perform one MAC in less than a clock cycle. DSP
processors or programmable DSP chips are flexible, but they might not
be fast enough. The reason is that the DSP processor is general
purpose and has architecture that constantly requires instructions to be
fetched, decoded and executed. ASICs can have multiple dedicated
MACs that perform DSP functions in parallel. But, they have high cost for
low volume production and the inability to make design modifications
after production makes them less attractive. FPGAs have been praised
for their ability to implement filters since the introduction of DSP savvy
architectures. Which can be efficiently realized using dedicated DSP
resources on these devices. More than 500 dedicated multiply-
accumulate blocks are now available, making them exceptionally well
suited for high-performance, high-order filtering applications that benefit
from a parallel, non-resource shared hardware architecture. In this
particular project, FPGA has been chosen as the implementation tool. To
program FPGA, hardware description language is needed.VHDL
synthesis offers an easy way to target a model towards different
implementation.

2. FIR Digital Filters

2.1 Digital filters
Digital filters are typically used to modify or alter the attributes of a
signal in the time or frequency domain. The most common digital filter is
the linear time invariant (LTI) filter. An LTI interacts with its input signal
through a process called linear convolution, denoted by y= h*x where h
is the filters impulse response , x is the input signal , and y is the
convolved output. The linear convolution process is formally defined by;
Y[n]= x[n]*h[n] = [ ] [ ]
k
x k h n k
= [ ] [ ]
k
h k x n k
(2.1)
LTI digital filters are generally classified as being finite impulse
response (FIR) ,or infinite impulse response (IIR). As the name, an FIR
filter consists of a finite number of sample values , reducing the above
convolution sum to a finite sum per output sample instant . An IIR filter
however , requires that an infinite sum be performed.
The motivation for studying digital filters is found in their growing
popularity as a primary dsp operation . Digital filters are rapidly replacing
classic analog filters , which were implemented using RLC components
and operational amplifiers. Analog filters were mathematically modeled
using ordinary differential equations of laplace transforms. Analog
prototypes are now only used in IIR design, while FIR are typically
designed using direct computer specifications and algorithms.

Z
-1
Z
-1

Z
-1

+ +
+
h[0] h[1]
h[2]
h[N-1]
X[n]
y[n]
Fig.2.1. Direct form FIR filter
2.2 FIR Theory
An FIR with constant coefficient s is an LTI digital filter. The output
of an FIR filter of order or length N , to an input time series x[n] , is
given by a finite version of the convolution sum given in (2.1) namely;
y[n] = x[n]*h[n]=
1
0
[ ] [ ]
N
k
h k x n k
( 2.2)
where h(0) through f[N-1] 0are the filters N coefficients. They also
correspond to the FIRs impulse response. For LTI systems it is some
times more convenient to express (2.2) in the z-domain with
Y(z)=H(z)X(z) (2.3)
Where H(z) is the FIRs transfer function defined in the z-domain by
H(z) =
1
0
[ ]
N
k
k
h k z
(2
.4)
The N
th
order LTI FIR filter is graphically interpreted in fig.2.1. It can
be seen to consist of a collection of a tapped delay line adders , and
multipliers. One of the operands presented to each multiplier is an FIR
coefficient, often referred to as a tap weight for obvious reasons.
The roots of polynomial H(z) in (2.4) define the zeros of the
filter.The presence of only zeros is the reason that FIRs are sometimes
called all zero filters. We note that nonrecursive filters are always FIR,
but recursive can be either FIR or IIR.
2.2.1 FIR filter with Transposed structure
A variation of the direct FIR model is called the transposed FIR filter.It
can be constructed by FIR filter in fig.2.1 by :
Exchanging the input and output.
Inverting the direction of signal flow.
Substituting an adder by adder fork, and vice versa.
A transposed FIR filter is shown in Fig . 2.2 and is in general,the
perfected implementation of a FIR filter. The benefits of this filter is
that we do not need an extra shift register for x[n], and there is no need
for a extra pipeline stage for the adder (tree) of the products to achieve
high throughput.

2.2.2 Symmetry in FIR filters
The center of an FIRs impulse response is an important point of
symmetry. It is sometimes convenient to define this point as the 0
th

sample instant. Such filter descriptions are a-causal. For an odd length
FIR the a-causal filter model is given by;
H(z) =
( 1) / 2
( 1) / 2
[ ]
N
k
k N
h k z
(2.5)
The FIRs frequency response can be computed by evaluating
the filters transfer function about the periphery of the unity , circle by
setting z=e
jwT
. It then follows that:
H(w)= H(e
jwT
)=
jwkT
[ ]e
k
h k
(2.6)

We then denote with ( ) F w the filters magnitude frequency response and
| (w) denotes the phase response and satisfies:
| (w)=arctan
( ( ))
( ( ))
H w
H w
| |
|
9
\ .
(2.7)
Z
-1
Z
-1

+ + +
h[0]
h[N-2] h[N-3]
h[N-1]
X[n]
y[n]
Fig. 2.2 FIR filter in the transposed structure
Digital filters are more often charecterised by phase and magnitude
than by z-domain transfer function or the complex frequency trans form.
Table2.1. Four possible linearphase FIR filters H(z) = [ ]
k
k
h k z

Symmetry h[n]=h[-n] h[n]= h[-n] h[n]= -h[-n] h[n]= -h[-n]
N odd even odd even

Example

Zeros at 120
0
90
0,
180
0
0
0,
180
0
0
0 ,
2x 180
0

2.2.3Linearphase FIR FILTER

Maintaining phase integrity across a range of frequencies is a desired
system attribute in many applications such as communications and
image processing. As a result, designing filters that establish linear-
phase versus frequency is often mandatory. The standard measure of
the phase linearity of a system is the group delay defined by :
t (w)=-
( ) d w
dw
|
(2.8)
A perfectly linear phase filter has a group delay that is constant
over a range of frequencies. It can be shown that linear-phase is
achieved if the filter is symmetric or anti-symmetric, and it is therefore
preferable to use the a-causal framework. It can be seen that a constant
0
1
-1
1 0 -1
1
0 0 0
1 1
-1 -1 -1
-2 -1 -2 0 0 2 1 0 2
n n n n
group delay can only be achieved if the frequency response H(w) is a
purely real or imaginary function . This implies that the filters impulse
response possesses even or odd symmetry. That is :
h[n]=h[-n] or h[n]=-h[-n]. (2.9)
An oddorder evensymmetry FIR filter would have a frequency
response given by :
H(w)=h(0)+
0
[ ]
jkwT
k
h k e
>
+h[-k]e
jkwt
(2.10)
=h[0] + 2
0
[ ]cos( )
k
h k kwT
>
, (2.11)
Which is seen to be a purely real function of frequency. Table 2.1
summarizes the four possible choices of symmetry , antisymmetry, even
order and odd order. In addition Table 2.1 graphically displays an
example of each class of linear phase FIR.

Z
-1
Z
-1

Z
-1

+ +

+

h[0] h[1]
h[N-2]
h[N-1]
X[n]
y[n]
Fig.2.3. Linear-phase FIR filter
Z
-1
Z
-1
Z
-1
Z
-1
+ +
+
+
2.3 Designing FIR Filters

Modern digital FIR filters are designed using computer-aided
engineering (CAE) tools. The filters used here are designed using the
MATLAB signal processing toolbox. The tool box includes an Ineractive
low pass filter design demo example that covers many typical digital
filter designs including:

Equiripple FIR design , which uses the parks McClellan and
Remez exchange methods for designing a linear phase
(symmetric) equiripple FIR.
Kaiser window design using the inverse DFT method weighted by
a Kaiser window.
Least square FIR method ,This filter design also has ripple in the
passband and stopband , but the mean least square error is
minimized.
Four IIR filter design methods are Butterworth ,Chebyshev I and II
, and elliptic.
2.3.1 Direct Window Design Method
The discrete Fourier transform(DFT) establishes a direct
connection between the frequency and time domains. Since the
frequency domain is the domain of filter definition, the DFT can be used
to calculate a set of FIR filter coefficients that produce a filter that
approximates the frequency response of target filter. A filter designed in
this manner is called a direct FIR filter.
A direct FIR filter is defined by;
h(n)=IDFT(H[k])=
2 /
[ ]
j kn L
k
H k e
t
(2.12)
The effects of ringing can only be suppressed with the use of a data
window that tapers smoothly to zero on both sides. Data windows
overlay the FIRs impulse response , resulting in a smoother magnitude
frequency response with an attendant widening of the transition band. If ,
for instance , a Kaiser window is applied to the FIR , the Gibbs ringing
can be reduced. Other classic window functions are summarized in table
2.2. They differ in terms of their ability to make trade offs between
ringing and transition bandwidth extension. The most common
windows, denoted w[n], are:
Rectangular : w[n]= 1
Bartlett(triangular ) : w[n]=2n/N
Hanning: w[n]= 0.5(1-cos(2t n/L)
Hamming: w[n] = 0.54-0.46cos(2t n/L)
Blackmann: w[n] = 0.42-0.5cos(2t n/L)+0.08cos(4t n/L)
Kaiser: w[n] = I
0
( )
2 2
1 ( / 2) /( / 2) n L L |
Table 2.2 shows the most important parameters of these winows. The
3-dB bandwidth shown in table 2.2 is the bandwith wh ere the transfer
function is decreased from DC by 3dB or ~ 1/ 2 . Data windows also
generate sidelobes , to various degrees away from the 0
th
harmonic.
Table 2.2. Parameters of commonly used window functions

Name 3-dB
bandwidth
First zero Maximum
sidelobe
Sidelobe
decrease per
octave
Equivalent
Kaiser
|
Rectangular 0.89/T 1/T -13 dB -6 dB 0
Bartlett 1.28/T 2/T -27 dB -12 dB 1.33
Hanning 1.44/T 2/T -32 dB -18 dB 3.86
Hamming 1.33/T 2/T -42 dB -6 dB 4.86
Blackmann 1.79/T 3/T -74 dB -6 dB 7.04
Kaiser 1.44/T 2/T -38 dB -18 dB 3

2.3.2 Equiripple Design Method
A typical filter specification not only includes the specification of
passband w
p
and stopband w
s
frequencies and ideal gains, but also the
allowed deviation (or ripple ) from the desired transfer function. The
transition band is most often assumed to be arbitrary in terms ripples. A
special class of FIR filter that is particularly effective in meeting such
specifications called the equiripple FIR. An equiripple design protocol
minimizes the maximal deviations (ripple error ) from the ideal transfer
function.
The equiripple or min-max algorithm is normally implemented
using the Parks McClellan itararive method. The Parks-McClellan
method is used to produce a equiripple or minimax data fit in the
frequency domain. It is based on the alternation theorem that says that
there is exactly one polynomial, a chebyshev polynomial with minimum
length, that fits into a given tolerance scheme. The length of the
polynomial , and therefore the filter can be estimated for a lowpass with

L=
10
10log ( ) 13
1
2.324( )
p s
s p
w w
c c
+
(2.15)
Where
p
c is the passband and
s
c the stopband ripple.

2.4 Constant Coefficient FIR Design
There are only a few applications ( e.g., adaptive filters) where
we need a general programmable filter architecture . In many
appllicatlion, the filters are LTI(i.e., linear time invariant) and the
coefficients do not change over time . In this case the hardware effort
can essentially be reduced by exploiting the multiplier and adder (trees)
needed to implement the FIR filter arithmetic.
With available digital filter design software the production of FIR
coefficient is a straightforward process . The challenge remains to map
the FIR design into a suitable architecture. The direct or transposed
forms are preferred for maximum speed and lowest resource utilization.
Lattice filters are used in adaptive filters because the filters can be
enlarged by one section, without the need for recomputation of the
previous lattice sections. But this feature only applies to PDSPs and is
less applicable to FPGAs. We will therefore focus our attention on the
direct and transposed implementations.

2.4.1 Direct FIR Design

The direct FIR filter can be implemented in VHDL using
(sequential) PROCESS statements or by component instantiations of
the adders and multipliers. A PROCESS design provides more freedom
to the synthesizer, while component instantiations gives full control to
the designer.
In a practical situation, the FIR coefficients are obtained from a
computer design tool and presented to the designer as floating point
numbers .The performance of a fixed point FIR, based on floating point
coefficient , needs to be verified using simulation or algebraic analysis
to ensure that design specifications remain satisfied.
Another issue that must be addressed when working with fixed-
points designs is protecting the system from dynamic range overflow
.Fortunately, the worst-case dynamic range growth G of N
th
order FIR is
to compute and it is:
1
2
0
log [ ]
N
k
G h k
=
| |
s
|
\ .
(2.17)
The total bit width is then the sum of the input bit width and the bit
growth G.

3. Design specification of FIR filters

Low-pass FIR filter has been implemented with

Response type: Low pass;

Design method: Constant coefficient FIR design

Filter order: order 5;

Hardware architecture: Direct form;

Sampling frequency: 5000Hz;

Cut-off frequency: 850Hz;

Input data length: 12 bits;

Output data length: 13 bits;

4.MATLAB CODING
4.1.MATLAB CODING FOR FREQUENCY RESPONSE AND TIME
DOMAIN RESPONSE(firfinal.m)

% Design of a lowpass 5-tap fir filter with passband gain of unity,
% fc=850Hz,fs=5000Hz .
clc;clear all;close all;
fc=850;fs=5000;
wc=2*pi*fc/fs;
t=0:1/fs:1;
x1=sin(2*pi*1000*t);
x2=sin(2*pi*600*t);
x3=sin(2*pi*850*t);

x11=x1(1:50);
x22=x2(1:50);
x33=x3(1:50);
N=5;
pd=(N-1)/2;eps=.0001;
n=0:1:N-1;
hd=sin(wc*(n-pd+eps))./(pi*(n-pd+eps));
wr=boxcar(N);
hn=hd.*wr';
%y=filter(hn,1,x);
%y=gnsfilter(hn,x);
y1=gnsfir(hn,x11);
y2=gnsfir(hn,x22);
y3=gnsfir(hn,x33);

w=0:.01:pi;
h=freqz(hn,1,w);
subplot (4,2,1)
plot (w/pi,abs(h),'r');grid;
ylabel('Magnitude ');
xlabel('Normalized frequency ');
title('Frequency response of a 5-taplowpass FIR filter');
subplot(4,2,3);
plot(t(1:50),x1(1:50));
xlabel('Time') ;
title('Magnitude response of x1=sin(2*pi*1000*t)') ;

subplot(4,2,4);
plot(t(1:50),y1(1:50));
xlabel('Time');
title('Magnitude response y1=gnsfir(hn,x11)');

subplot(4,2,5);
plot(t(1:50),x2(1:50));
xlabel('Time') ;
subplot(4,2,6);
plot(t(1:50),y2(1:50));
xlabel('Time');
title('Magnitude response y2=gnsfir(hn,x22)');
subplot(4,2,7);
plot(t(1:50),x3(1:50));
xlabel('Time') ;

subplot(4,2,8);
plot(t(1:50),y3(1:50));
xlabel('Time');
title('Magnitude response y=gnsfir(hn,x33)');
4.2.MATLAB CODING FOR O/P( gnsfir.m )
function [y]=gnsfir(hn,x)
m=length(x)
p=length(hn)
n=m+p-1
x=[x,zeros(1,p-1)];
z=zeros(1,p);
for i=1:n

z1=z(1:p-1)
z=[zeros(1,1),z1]
z(1)=x(i)
y(i)=z*hn'
end

5.Matlab simulation Result

5.1. Frequency response

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
M
a
g
n
i
t
u
d
e
normalized frequency
X: 0.3406
Y: 0.4629

Figure 5.1 Low pass 5-tap FIR filter with f
c
= 850 Hz, f
s
=5KHz
hn =[ 0.1344 0.2789 0.3400 0.2789 0.1344 ]

5.2.Response in Time domain

0 0.5 1
0
1
2
M
a
g
n
i
t
u
d
e

Normalized frequency
Frequency response of a 5-taplowpass FIR filter
X: 0.3374
Y: 0.4724
0 0.005 0.01
-1
0
1
Time
M
a
g
n
i
t
u
d
e

Magnitude response of x1=sin(2*pi*1000*t)
0 0.005 0.01
-0.5
0
0.5
X: 0.0036
Y: 0.2805
Time
M
a
g
n
i
t
u
d
e

Magnitude response y1=gnsfir(hn,x11)
0 0.005 0.01
-1
0
1
Time
M
a
g
n
i
t
u
d
e

0 0.005 0.01
-1
0
1
X: 0.0042
Y: 0.75
Time
M
a
g
n
i
t
u
d
e

Magnitude response y2=gnsfir(hn,x22)
0 0.005 0.01
-1
0
1
Time
M
a
g
n
i
t
u
d
e

0 0.005 0.01
-1
0
1
X: 0.0066
Y: 0.4611
Time
M
a
g
n
i
t
u
d
e

Magnitude response y=gnsfir(hn,x33)

Figure 5.2 Response in time domain.

25- tap Low-pass FIR Filter
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
M
a
g
n
i
t
u
d
e
normalized frequency
X: 0.3406
Y: 0.492

Figure 5.3 Frequency response of 25-tap low pass Filter
fc=850Hz and fs=2500Hz .

INTRODUCTION

VIRTEX II PRO PROTOBOARD(MODEL MXV2P4/7FP-000-RKPC-001)
Virtex-II Pro Protoboard is a complete Embedded VLSI development board
having on board
XC2VP4 or XC2VP7 FPGA
4 different Clock Sources
High speed ADC
DAC
Asynchronous SRAM
Flash PROM
RS-232 Serial port
RS-422 Transceivers
16*2 LCD
4 * 3 Key Board Interface
8 DIP switches
8 output LEDs
DCI supported Single ended as well as differential digital IOs.

- The Protoboard is suitable for implementing embedded processor based
applications with extreme flexibility using IP cores and customized modules.
- As powerful RocketIO Multi Gigabit Transceivers (MGT) is provided on the
board; protoboard is useful in developing high-speed serial Transceiver
applications (Ethernet applications).
- Digital IOs provided on the board are useful for external device interfacing.
- One bank (bank-6) of digital IOs on FPGA is user configurable to select DCI IO
standards (e.g. LVDCI_33 etc) or differential LVDS IO standards (e.g.
LVDS_25).

TECHNICAL Specifications
FPGA - XC2VP4 or XC2VP7 with on chip PowerPC-405 Processor
ADC - 14 bit, 10MSPS analog input channel is available using AD9240
DAC - One channel, using 12-bit DAC.AD7541
Digital I/O 98/120 DCI digital I/Os.(While using P4 98 user ios are available)
- High Speed IOs
Two Rocket IO channels if XC2VP4 is used.
Four Rocket IO channels if XC2VP7 is used
Data Memory
Up to 4MX16 onboard memory
Code Memory
Up to 2MX16 onboard memory
- Serial Interface
16 Channel RS422 transmitters.
16 Channel RS422 receivers.
Two RS232 full duplex channels.
- 4 * 3 Key Board Interface connector..
- 16*2 LCD Interface connector.
- 8 LEDs for output indication.
- 8 DIPswitches for inputs.

Supported IO Standards
LVTTL
LVCMOS
LVDCI_33
LVDS_25 (differential)
Harwdare description
FPGA
Device XC2VP4 or XC2VP75 in FF672 package with one power PC &
Embedded RocketIO Multi-Gigabit Transceiver (MGT).
Virtex-II Pro devices are user-programmable gate arrays with various
configurable elements and embedded blocks optimized for high density and
high-performance system designs.
Virtex-II Pro devices implement the following functionality:
Embedded high-speed serial transceivers enable data bit rate up to 1.25
Gb /s per channel (Gigabit Ethernet).
Embedded IBM PowerPC 405 RISC processor blocks provide performance of
300+ MHz.
PowerPC 405 Processor
The PPC405 RISC CPU can execute instructions at a sustained rate of one
instruction per cycle. On-chip instruction and data cache reduce design
complexity and improve system throughput.
Within the Processor Block, there are four components:

1) Embedded IBM PowerPC 405-D5 RISC CPU core
Embedded PowerPC 405 (PPC405) core operating at 300+ MHz maintains low
power consumption.
Specially designed interface logic integrates the core with the surrounding
CLBs; block RAMs, and general routing resources.
Embedded PowerPC 405 core consists of the following functional blocks
- Instruction & Data Cache units
- Memory Management unit
- Fetch & Decode unit
- Execution unit
- Timers
- Debug logic unit

2) On-Chip Memory (OCM) controllers and interfaces
The OCM controllers (DSOCM & ISOCM) serve as dedicated interfaces between
the block RAMs in the FPGA fabric and OCM signals available on the embedded
PPC405 core.
ISOCM controller provides an interface to the 64-bit Instruction-Side Block
RAM (ISBRAM) while
DSOCM controller provides an interface to the 32-bit Data-Side Block RAM
(DSBRAM).

3) Clock / control interface logic
The clock / control interface logic provides proper initialization and
connections for PPC405 clock/power management, resets, PLB cycle control,
and OCM interfaces. It also couples user signals between the FPGA fabric and
the embedded PPC405 CPU core.
Processor clock source can come from DCM, CLB, or user package pin.

4) CPU-FPGA Interfaces
Processor Block user pins link up with the general routing resources of FPGA
through the CPU-FPGA interface. Therefore processor signals have the same
routability as other non-Processor Block user signals.
Different CPU-FPGA Interfaces are
Processor Local Bus (PLB) Interfaces
Device Control Register (DCR) Bus Interface
On-Chip Memory (OCM) Interfaces
External Interrupt Controller (EIC) Interface
Clock/Power Management (CPM) Interface
Reset Interface
Debug Interface

RocketIO Multi-Gigabit Transceivers
The RocketIO Multi-Gigabit Transceiver, based on Mindspeeds SkyRail
technology, is a flexible parallel-to-serial and serial-to-parallel-embedded
transceiver used for high-bandwidth interconnection between buses, back
planes, or other subsystems.

ADC
Device - AD9240 of Analog Device.
Resolution - 14 bit
Sampling rate - 10MSP
Input type - single ended
Input range - 0 5V.
ADC input is buffered by using Rail-to-Rail amplifier AD8052.AD9240 is useful
in various applications such as imaging, communications, medical and data
acquisition systems.
DAC
Device - AD7541A of Analog Device.
Resolution 12 bit
Conversion time 100 ns
Settling time 600 ns
Analog o/p range 0-5V
Analog input & output are provided using SMA connectors.

Clock-Source
Different clock sources are available on the protoboard which provide
reference clock for FPGA, PowerPC, RocketIO transceiver
Four clock sources provided on the board are-
40 MHz clock source as a system clock
125MHz clock source as system clock (optional).
SMA connectors for Differential clock input
125MHz LVDS Clock for MGT (optional).
These clock sources are connected at global clock inputs of FPGA.
The 125 MHz on-board LVDS oscillator and a pair of differential SMA
connectors provide the reference clock input to the Rocket I/O transceivers.
An on-board 40 MHz/125MHz oscillator provides the system clock input to the
FPGA & processor section of it. This, 40 Mhz/125 MHz, clock can be used by
the Virtex-II Pro Digital Clock Managers (DCMs) to generate various clocks.
Any one out of these clock sources can be used for RocketIO Transceivers.
Data Memory
Device Asynchronous SRAM uPD4416016 by NEC
Capacity/device 1M by 16 bit
Max No. of devices 4.
Total Capacity 4M by 16bit

Code Memory
Device Flash PROM LH28F800 by Hitachi
Capacity/Device 512K by 16 bit
Max No. of Devices 4
Total Capacity 2M by 16bit.
In system Programming & erasing of all Flash PROM devices is possible.
This memory can also be used as program memory for PowerPC processor

Serial Interface
RS422 serial interface 16 RS422 channels are provided.
RS-422 transmits channels using DS34LV87.
RS-422 receives channels using DS34LV86.
Differential outputs & inputs of all Transmitters & Receivers are provided on
separate 34 pin Headers.

RS-232 Serial Interface 2 full duplex RS-232 Serial channels
are provided using MAX2332.

LCD Interface
Protoboard provides interface for 16 characters by 2 lines LCD module.
Operating at 3.3V or 5V.

- Output LEDs
8 digital outputs with led indication are provided on the protoboard.

- Keyboard
Keyboard matrix (4 * 3) of 12 keys is provided on the Protoboard.
4 rows of keyboard matrix form return lines while 3-column form scan lines.

- Switches
1) Reset Switch
Push-button reset switch is provided to reset the entire system.
2) Configuration reset
Protoboard is provided with a push button switch input to reinitiate the
FPGA configuration process.
3) DIP Switches
8 digital I/Os are routed through DIPswitches. While in off position
switch sets its respective input at logic zero and in on position input is
set at logic 1
- Digital I/O 120 / 98 true bi-directional I/Os
22 single ended IOs provided on 26 pins FRC connector (available with
XC2VP7 only).
44 single ended IOs provided on 50 pins FRC connector.
Note - These 66 IOs are 5 V tolerant.
27 LVDS I/Os provided on 60 pins FRC.
Note - LVDS IOs may also be used as 54 single ended IOs.
These are 3.3 V tolerant.

- Jumper Setting

MODE SELECTION TABLE:
Configuration
Mode
M2 (JP8) M1 (JP6) M0 (JP5)
Master Serial
Mode
0 0 0
Boundary Scan
Mode
1 0 1

JP3
Hot Swap Enable
While FPGA is getting configured, its user IOs can be pulled up using
hot swap enable feature. By setting jumper JP3 as shown in JUMPER
SETTING TABLE, hot swap can be enabled or disabled.

JP4
Selection of VCCO for bank 6-
Setting of Jumper JP4 will select either 3.3V or 2.5V as VCCO of Bank-6.
IOs taken from Bank-6 of FPGA, are provided on a 60 pin I/O FRC Connector
J9.
Depending upon VCCO selection, these IOs will be configured for different IO
standards.
When VCCO selected is 3.3V then IOs will support LVTTL, LVCMOS_33 &
LVDCI_33 IO standards
When VCCO selected is 2.5V then IOs will support LVDS_25 IO standard.

Jumper Selection Table
Sr.
no.
Jumper Description Settings Function

1 2
3

1.
JP8
JP6
JP5

Selection of
Configuration
Mode

Boundary
scan mode
2.
JP8
JP6
JP5

Selection of
Configuration
Mode

Master
serial mode

3.
JP3

Hot Swap Enable

Hot swap
enabled.
4.

JP3

Hot Swap Enable

Hot swap
disabled.
5.

JP4

VCCO for bank6

VCCO =
3.3V
6. JP4

VCCO for bank6

VCCO =
2.5V
7. JP7 D0 Selection
During
Master
Serial
Config.
Mode

Preset Details:-
PR1 LCD Brightness adjustment
PR3
Offset Adjustment of Analog
Out (DAC)
PR2
Reference Voltage Adjust for
DAC

Note:-
- PR2 & PR3 Presets, are factory configured, do not change settings.
- If the settings are changed, the Analog output range will change
- Reference voltage of DAC is 2.5 V

Header / Connector Description
For an easy interface with the external devices Board is equipped with all
necessary Connectors & Headers.
Various Headers required for different applications are listed below.

J1 9 pin JTAG Header
J2
34 pin RS-422 Transmitter
Header
J3 16 pin LCD Header
J4 26 pin Digital IO Header
J5 10 pin Serial RS-232 Header
J6
34 pin RS-422 Receiver
Header
J11 4 pin Supply Connector
J12 20 pin CPU Trace Header
J14 16 pin CPU Debug Header

JTAG Header
Provided to configure on board Configuration PROM & configure Virtex-II Pro
FPGA.
Pin assignment is as shown below

TCK GND
TDO
TMS
3.3V
TDI -
JTAG
GND
1 2
3 4
5 6
7 8
9 10
J1
JTAG
Header

CPU Trace Header
Protoboard provides a CPU Trace port for tracing the instruction stream
executed by the PowerPC processor.
Pin assignment for CPU Trace Header is as shown below
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
TRACE_CLK
TRACE_TS20
GND
J12 - CPU TRACE
Header
19 20
TRACE_TS2E
TRACE_TS4
TRACE_TS6
TRACE_TS5
TRACE_TS3
TRACE_TS1E
TRACE_TS10

CPU Debug Header
Protoboard is provided with a CPU JTAG/DEBUG Header to download code into
the Virtex-II Pro integrated PowerPC processor or to debug the PowerPC
processor code.

1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
CPU_HALT_N
GND
J14 - CPU DEBUG
Header
CPU_TMS
CPU_TCK
CPU_TDI
CPU_TDO
CPU_TRST
CPU_VCC

LCD Header
A 16 * 2 LCD is provided on Board. 8-bit interface to FPGA is through
Level Translator.
16 pin LCD Header carries all signals to LCD. Either 3.3V or 5V LCD can
be interfaced.
Pin assignment of LCD Header is as follows
GND
LCDV
GND
J3
LCD
Header
RS
R/W\
E
+5V
Level
Translator
VSS
VDD
VO
RS
R/W
E
D0
D1
D2
D3
D4
D5
D6
D7
V+
V-
LCDV
GND

Supply connector
Virtex-II Pro Protoboard is powered externally using separate power supply.
Supply header pin assignment is as follows
J11
Supply
Connector
GND
-12V
+12V
+5V

Serial RS232 Header
Protoboard is having Serial RS232 interface.For external serial interface
a header is provided on board.
1
3
5
7
9
2
4
6
8
10
GND
TXD
RXD TXD1_1
RXD1_1
J5
RS232 Header

- RS-422 Transmitter
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
TXOD1+
TXOC1+
TXOB1+
TXOA1+
TXOD1-
TXOD2+
TXOC2+
TXOB2+
TXOA2+
TXOD3+
TXOC3+
TXOB3+
TXOA3+
TXOD4+
TXOC4+
TXOB4+
TXOA4+
TXOC1-
TXOB1-
TXOA1-
TXOD2-
TXOC2-
TXOB2-
TXOA2-
TXOD3-
TXOC3-
TXOB3-
TXOA3-
TXOD4-
TXOC4-
TXOB4-
TXOA4-
J2
RS-422 XMITTER

- RS-422 Receiver
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
RXID1+
RXIC1+
RXIB1+
RXIA1+
RXID1-
RXID2+
RXIC2+
RXIB2+
RXIA2+
RXID3+
RXIC3+
RXIB3+
RXIA3+
RXID4+
RXIC4+
RXIB4+
RXIA4+
RXIC1-
RXIB1-
RXIA1-
RXID2-
RXIC2-
RXIB2-
RXIA2-
RXID3-
RXIC3-
RXIB3-
RXIA3-
RXID4-
RXIC4-
RXIB4-
RXIA4-
J6
RS-422 RECEIVER

Note- RXD*+ should be connected to the TXD*+ and RXD*- to TXD*-

- SMA Connector Description
1) Analog I/O Connector
Analog interface to the Board is given through SMA connectors as listed below

J7 Analog I/P to ADC
J8 Analog O/P from DAC

2) Rocket IO Receiver
J15 RXN16
J16 RXP16
J17 RXN18
J18 RXP18
J19 RXN19
J20 RXP19
J21 RXN21
J22 RXP21

3) Rocket IO Transmitter
J23 TXP16
J24 TXN16
J25 TXP18
J26 TXN18
J27 TXP19
J28 TXN19
J29 TXP21
J30 TXN21

4) External Clock
J31 External Clock (SMA+)
J32 External Clock (SMA-)

- Pin Assignment ADC Interface
Function FPGA Function FPGA
ADC0 Y4 ADC7 W6
ADC1 Y5 ADC8 W5
ADC2 Y6 ADC9 V2
ADC3 W2 ADC10 V1
ADC4 W1 ADC11 V4
ADC5 W4 ADC12 V6
ADC6 W3 ADC13 V3

ADC CLK AND OUT OF RANGE PORTS
ADCCLK Y3 OTR V5

DAC Interface
DAC1-D0 AF2 DAC1-D6 Y1
DAC1-D1 AD4 DAC1-D7 AA1
DAC1-D2 AE1 DAC1-D8 AB3
DAC1-D3 AD2 DAC1-D9 AB4
DAC1-D4 AD1 DAC1-D10 AC1
DAC1-D5 AC3 DAC1-D11 AC2

SRAM DATA LINES
D1-R1 U7 D9-R1 L2
D2-R1 U6 D10-R1 M3
D3-R1 U4 D11-R1 M5
D4-R1 F1 D12-R1 M7
D5-R1 V7 D13-R1 M2
D6-R1 U3 D14-R1 M6
D7-R1 U5 D15-R1 M4
D8-R1 T7 D16-R1 L1

SRAM ADDRESS LINES
A0-R1 N7 A10-R1 G1
A1-R1 N5 A11-R1 T3
A2-R1 N3 A12-R1 T5
A3-R1 P7 A13-R1 H1
A4-R1 P5 A14-R1 J2
A5-R1 R4 A15-R1 P4
A6-R1 R3 A16-R1 P6
A7-R1 T6 A17-R1 K1
A8-R1 T4 A18-R1 N4
A9-R1 H2 A19-R1 N6
SRAM CHIP SELECT, WRITE EN , OUT EN
WE-SRAM R5 CS-R2 R7
OE-R1 R6 CS-R3 P3
CS-R1 J1 CS-R4 A2

FLASH DATA LINES
D0-F1 L5 D2-F1 K4
D10-F1 K5 D3-F1 K6
D11-F1 K7 D4-F1 J3
D12-F1 J4 D5-F1 J5
D13-F1 J6 D6-F1 J7
D14-F1 H3 D7-F1 H4
D15-F1 H5 D8-F1 L6
D1-F1 L7 D9-F1 K3

FLASH ADDR LINES
A0-F1 L3 A1-F1 H6
A10-F1 D7 A20-NC H14
A11-F1 C2 A2-F1 C1
A12-F1 B1 A3-F1 G3
A13-F1 D6 A4-F1 G4
A14-F1 C6 A5-F1 G5
A15-F1 E7 A6-F1 G6
A16-F1 A8 A7-F1 E1
A17-F1 E2 A8-F1 D2
A18-F1 E3 A9-F1 F8
A19-NC H13
FLASH WRITE , OUTPUT ENABLE ,RY/BY & CHIP SELECT
\OE\-F1 L4 \CE\-F1 B8
\WE\-F1 D1 \CE\-F2 C8
RY/BY-F1 E4 \CE\-F3 D8
\CE\-F4 E8

LCD INTERFACE SIGNALS
LCD-D0 U1 LCD-D6 N2
LCD-D1 T2 LCD-D7 M1
LCD-D2 T1 E F9
LCD-D3 R2 RS E9
LCD-D4 R1 R/W G9
LCD-D5 P2

RS422 TX AND RX
RXA1 E20 TXA1 F12
RXA2 B26 TXA2 D15
RXA3 D26 TXA3 F15
RXA4 E26 TXA4 G18
RXB1 F19 TXB1 D12
RXB2 D21 TXB2 F13
RXB3 C26 TXB3 E18
RXB4 E24 TXB4 B19
RXC1 D20 TXC1 E12
RXC2 A25 TXC2 G13
RXC3 D25 TXC3 E15
RXC4 E25 TXC4 A19
RXD1 D19 TXD1 C12
RXD2 C21 TXD2 C15
RXD3 C25 TXD3 F18
RXD4 E23 TXD4 C19

RS232 TX AND RX
TXD-F G26 RXD-F F26;
TXD-F1 M19 RXD-F1 P19;

I/P SWITCHES
IL0 AB12 IL4 AA9;
IL1 AC12 IL5 Y8;
IL2 AD12 IL6 AC8;
IL3 Y9 IL7 AD8;

O/P LEDS
OL0 AC19 OL4 AA15
OL1 AD19 OL5 AB15
OL2 Y19 OL6 AC15
OL3 Y18 OL7 AD15

KEYBOARD INTERFACE
SL0 AA18 RL0 AA14
SL1 W14 RL1 AA13
SL2 Y14 RL2 Y13
RL3 AA12

RKTIO CHANNELS
TXN16_SEC AF7 RXN16_SEC1 AF4
TXP16_SEC AF6 RXP16_SEC1 AF5
TXN18_PRI AF12 RXN18_PRI1 AF9
TXP18_PRI AF11 RXP18_PRI1 AF10
TXN19_PRI AF18 RXN19_PRI1 AF15
TXP19_PRI AF17 RXP19_PRI1 AF16
TXN21_SEC AF23 RXN21_SEC1 AF20
TXP21_SEC AF22 RXP21_SEC1 AF21

RKTIO CHANNEL SUPPLY PINS
Function
FPGA
Function FPGA
AVCCAUXTX16 AE6 AVCCAUXRX16 AE4
VTTX16 AE7 VTRX16 AE5
Function
FPGA
Function FPGA
GNDA16 AD5 GNDA19 AD16
GNDA18 AD11 GNDA21 AD22

AVCCAUXTX4 B22 AVCCAUXRX4 B20
VTTX4 B23 VTRX4 B21
GNDA4 C22

VTTX6 B18 VTRX6 B16
GNDA6 C16

VTTX7 B12 VTRX7 B10
GNDA7 C11

Function
FPGA
Function FPGA
VTTX9 B7 VTRX9 B5
GNDA9 C5

CPU JTAG CONNECTOR
CPU_HALT_N AA11 CPU_TDO Y15
CPU_TCK Y11 CPU_TMS Y10
CPU_TDI Y16 CPU_TRST Y12

CPU TRACE CONNECTOR
TRACE_CLK AD18 TRACE_TS3 AC17
TRACE_TS10 Y17 TRACE_TS4 AB16
TRACE_TS1E AC18 TRACE_TS5 AB17
TRACE_TS20 AA17 TRACE_TS6 AC16
TRACE_TS2E AA16

CLK & RST SIGNALS FOR FPGA
GCLK1_40M D13 SMA- AC13
GCLK2_120M E14 SMA+ AB13
CLK AB14 POWERON-RESET N19
NCLK AC14

SINGLE ENDED IOs
IO1 IO23 K26
IO2 IO24 L20
IO3 IO25 L21
IO4 IO26 L22
IO5 IO27 L23
IO6 IO28 L24
IO7 IO29 L25
IO8 IO30 L26
IO9 IO31 M20
IO10 IO32 M21
IO11 IO33 M22
IO12 IO34 M23
IO13 IO35 M24
IO14 IO36 M25
IO15 IO37 M26
IO16 IO38 N20
IO17 IO39 N21
IO18 IO40 N22
IO19 IO41 N23
IO20 IO42 N24
IO21 IO43 N25
IO22

SINGLE ENDED NC IOs (Available only with XC2SP7)
NCIO1 C9 NCIO20 F17
NCIO10 G11 NCIO21 G15
NCIO11 G12 NCIO22 G16
NCIO13 C18 NCIO23 G17
NCIO14 D16 NCIO3 D10
NCIO15 D17 NCIO4 D11
NCIO16 D18 NCIO5 E10
NCIO17 E16 NCIO6 E11
NCIO18 E17 NCIO7 F10
NCIO19 F16 NCIO8 F11
NCIO2 D9 NCIO9 G10

DIFFERENTIAL IOs
IO1- P25 IO14- V25
IO1+ P24 IO14+ V24
IO2- P23 IO15- V23
IO2+ P22 IO15+ V22
IO3- P21 IO16- V21
IO3+ P20 IO16+ V20
IO4- R25 IO17- W25
IO4+ R26 IO17+ W26
IO5- R24 IO18- W23
IO5+ R23 IO18+ W24
IO6- R22 IO19- W22
IO6+ R21 IO19+ W21
IO7- T25 IO20- AA26
IO7+ T26 IO20+ Y26
IO8- T24 IO21- Y24
IO8+ T23 IO21+ Y23
IO9- T22 IO22- Y22
IO9+ T21 IO22+ Y21
IO10- R20 IO23- AB24
IO10+ T20 IO23+ AB23
IO11- V26 IO24- AC25
IO11+ U26 IO24+ AC26
IO12- U24 IO25- AD25
IO12+ U23 IO25+ AD26
IO13- U22 IO26- AF25
IO13+ U21 IO26+ AE26
IO27- AC24
IO27+ AD23

FPGA Configuration
Configuration is the process of loading design specific programming data into
one or more FPGAs. It is to define the functional operation of the internal
blocks and their interconnections. The bit-stream of a design as generated by
the Xilinx development software, is loaded into the internal configuration
memory of the FPGA.

FPGA can be configured in one of the following modes:-
1) Through JTAG port (Boundary Scan Mode)
2) Through PROM (Master Serial Mode)

Configuration mode Selection
Configuration modes M2
(JP8)
M1
(JP6)
M0
(JP5)
Boundary Scan 1 0 1
Master Serial 0 0 0

Downloading procedure
1) BOUNDARY SCAN MODE (CONFIGURE FPGA ONLY)
Set the jumpers JP8, JP6, JP5 for boundary scan mode as depicted in jumper
setting table
After jumper setting is done, follow the procedure to download bit stream in
FPGA
Right click on Generate Programming File -> Properties -> Start-up
Options -> Start-up Clock = JTAG Clock.
Right click on Configure Device (iMPACT) -> Properties -> Configuration
Mode = Boundary Scan Mode
Double click on Configure Device (iMPACT).
Select the device (FPGA)
Program.

2) MASTER SERIAL MODE
Set the jumpers JP8, JP6, JP5 for master serial mode as depicted in jumper
setting table
Set the jumpers JP7 for master serial mode as depicted in jumper setting table
With this jumper setting at power on FPGA will get configured through PROM.

3) DOWNLOADING IN PROMS
Set the jumpers JP8, JP6, JP5 for boundary scan mode as depicted in jumper
setting table
Follow the instructions to download data in PROM
Right click on Generate Programming File Properties Startup
Options Start-up Clock = CCLK.
Double click on Generate PROM File.
Select Prepare Configuration File PROM Properties ->
o PROM File Format = MCS-86
o Type = Serial
o PROM File = Single PROM
o Select PROM device
o Fill Value to calculate checksum = FF (default)
o Click FINISH
Select File -> Select -> Create PROM.
Close Xilinx PROM File Formatter window.
Right click on Generate Programming File -> Properties -> Start-up
Options -> Start-up Clock = JTAG Clock.
Right click on Configure Device (iMPACT) -> Properties -> Configuration
Mode = Boundary Scan Mode
Double click on Configure Device (iMPACT).
Right click in the iMPACT window and select Initialize Chain
Select only *.mcs file for programming. Right click on it & select Program.
Switch off the power supply & set jumpers JP8, JP6, JP5 in master serial
mode. Then turn the supply on. This time the programming will be done
through PROM if successful the done LED will glow &the display will be
seen.

VHDL CODING FOR TOP MODULE OF 5-TAP FIR FILTER

-----------------------------------------------------------------------
-----------
-- Company:
-- Engineer:
--
-- Create Date: 02:41:43 09/12/2009
-- Design Name:
-- Module Name: top1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top1 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
data_dac : out STD_LOGIC_VECTOR (11 downto 0);
s : IN std_logic;
data : IN std_logic_vector(13 downto 0);
otr : IN std_logic;
otr_out : OUT std_logic;
adcclk : OUT std_logic;
dout : OUT std_logic_vector(11 downto 0)

);
end top1;

architecture Behavioral of top1 is

signal dout_sig : std_logic_vector(11 downto 0);

COMPONENT adc1
PORT(
clk : in std_logic;
rst : in std_logic;
s : in std_logic;
data : in std_logic_vector(13 downto 0);
otr : in std_logic;
otr_out : out std_logic;
adcclk : out std_logic;
dout : out std_logic_vector(11 downto 0)
);
END COMPONENT;

COMPONENT tapfirdf
PORT(
clk:in std_logic;
rst:in std_logic;
x:in std_logic_vector(11 downto 0) ;
doutf : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;

begin

Inst_adc1: adc1 PORT MAP(
clk =>clk ,
rst =>rst ,
s => s,
data =>data ,
otr =>otr ,
otr_out =>otr_out ,
adcclk =>adcclk ,
dout =>dout_sig
);

Inst_tapfirdf: tapfirdf PORT MAP(
clk =>clk,
x =>dout_sig ,
doutf=>data_dac,
rst=>rst
);

end Behavioral;

VHDL CODING FOR ADC MODULE
library IEEE;

entity adc1 is
port ( clk : in std_logic;
rst : in std_logic;
s : in std_logic;
data : in std_logic_vector(13 downto 0);
otr : in std_logic;
otr_out : out std_logic;
adcclk : out std_logic;
dout : out std_logic_vector(11 downto 0)
);
end adc1;

architecture Behavioral of adc1 is

signal divider : std_logic_vector(12 downto 0);
signal clk_div : std_logic;
signal data_s : std_logic_vector(13 downto 0);
signal count : std_logic_vector(11 downto 0);

type state is (start,wait1,wait2,wait3,rd_data);
signal ps,ns : state;

begin

-- divide 40 Mhz to 5khz
process(rst,clk)
begin
if(rst = '1') then
divider <= (others => '0');
elsif(clk'event and clk = '1') then
if (divider = "1111100111111") then
divider<= "0000000000000" ;
else divider <= divider + 1;
end if;
end if ;
end process;
clk_div <= divider(12); -- 500 Khz clk

process(rst,clk_div)
begin
if(rst = '1') then
count <= (others => '0');
elsif(clk_div'event and clk_div = '1') then
count <= count + '1';
end if;
end process;

--next state decoder
process(ps,s)
begin
case ps is
when start =>
if(s = '1') then
ns <= wait1;
else
ns <= start;
end if;
when wait1 =>
if(s = '1') then
ns <= wait2;
else
ns <= start;
end if;
when wait2 =>
if(s = '1') then
ns <= wait3;
else
ns <= start;
end if;
when wait3 =>
if(s = '1') then
ns <= rd_data;
else
ns <= start;
end if;
when rd_data =>
if(s = '1') then
ns <= rd_data;
else
ns <= start;
end if;
when others =>
ns <= start;
end case;
end process;

--output decoder
process(ps)
begin
case ps is
when start =>
adcclk <= '0';
data_s <= (others => '0');
when wait1 =>
adcclk <= clk_div;
when wait2 =>
adcclk <= clk_div;
when wait3 =>
adcclk <= clk_div;
when rd_data =>
adcclk <= clk_div;
data_s <= data;
when others =>
adcclk <= '0';
data_s <= (others=>'0');
end case;
end process;

process(rst,clk_div)
begin
if(rst = '1') then
ps <= start;
elsif(clk_div'event and clk_div = '1') then
ps <= ns;
end if;
end process;

dout <= data_s(13 downto 2);--count;
otr_out <= otr;

end Behavioral;

VHDL CODING FOR 5-TAP FIR MODULE

-----------------------------------------------------------------------
-----------
-- Company:
-- Engineer:
--
-- Create Date: 05:44:56 08/09/2009
-- Design Name:
-- Module Name: 5tapfirdf - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-----------

package sixteen_bit_int is
subtype byte is integer range -128 to 127 ;
subtype bits12 is integer range -2**11 to 2**11-1;
type array_bits12 is array(0 to 4) of bits12;
end sixteen_bit_int;
library work;
use work.sixteen_bit_int.all;

library IEEE;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tapfirdf is
port ( clk:in std_logic;
rst:in std_logic;
x:in std_logic_vector(11 downto 0) ;
y:out bits13 ;
doutf : OUT std_logic_vector(11 downto 0)

);

end tapfirdf;

architecture Behavioral of tapfirdf is
signal divider1 : std_logic_vector(12 downto 0);
signal clk_div1 : std_logic;
signal z:array_bits12:=(0,0,0,0,0);
signal y_sig:bits13;
signal y13_sig:std_logic_vector(12 downto 0);
signal doutf_sig :std_logic_vector(11 downto 0);
begin
-- 40 Mhz to 5 Khz
process(rst,clk)
begin
if(rst = '1') then
divider1 <= (others => '0');
elsif(clk'event and clk = '1') then
if (divider1 = "1111100111111") then
divider1<= "0000000000000" ;
else divider1 <= divider1 + '1';
end if;
end if ;
end process;
clk_div1 <= divider1(12); -- 5 Khz clk
p1:process(clk_div1,rst)
begin
if(rst = '1') then
y_sig <=0;
elsif(clk_div1'event and clk_div1 = '1') then
--wait until clk='1';

y_sig<= z(0)/8+z(0)/128+z(0)/1024+z(0)/2048+
z(1)/4+z(1)/64+z(1)/128+z(1)/256+z(1)/1024+z(1)/2048+
z(2)/4+z(2)/16+z(2)/64+z(2)/128+z(2)/256+
z(3)/4+z(3)/64+z(3)/128+z(3)/256+z(3)/1024+z(3)/2048+
z(4)/8+z(4)/128+z(4)/1024+z(4)/2048 ;
for i in 4 downto 1 loop
z(i)<=z(i-1);
end loop ;
z(0)<=bits12(conv_integer(signed( x)));
end if;
end process ;
y13_sig<=conv_std_logic_vector(y_sig,13)(12 downto 0);
doutf<=y13_sig(12 downto 1);
y<=y_sig;
end Behavioral;

USER CONSTRAINT FILE

net "data_dac<7>" loc = "ad1"; net "clk" loc = "d13";
net "rst" loc = "n19";
net "s" loc = "ab12";
#net "data<0>" loc = "y4";
#net "data<1>" loc = "y5";
net "data<2>" loc = "y6";
net "data<3>" loc = "w2";

net "data<9>" loc = "v2";

net "data_dac<11>" loc = "af2";
net "data_dac<10>" loc = "ad4";
net "data_dac<9>" loc = "ae1";
net "data_dac<8>" loc = "ad2";

net "data_dac<6>" loc = "ac3";
net "data_dac<5>" loc = "y1";
net "data_dac<4>" loc = "aa1";
net "data_dac<3>" loc = "ab3";
net "data_dac<2>" loc = "ab4";
net "otr" loc = "v5";
net "adcclk" loc = "y3";
net "otr_out" loc = "ac19";

4.1. SCHEMATIC OF TOP MODULE 5-TAP FIR

Figure 4.1 schematic of top module

4.2.INTERFACING OF ADC MODULE WITH FIR MODULE

Figure 4.2. ADC module interfacing with FIR module

Matlab Result-1
y =[ 4.3008 8.9248 10.8800 8.9248 4.3008]
VHDL simulation Result

Test bench output-1

Test bench input-1

Matlab Result-2
y = [4.3008 17.5264 33.0304 41.7600 38.5680 25.1976 11.4832 4.3816 1.0752]

VHDL simulation Result

Test bench output-2

Test bench input-2

Conclusion
In terms of high speed architecture the direct form approach is preferred for
design; the architecture is successfully implemented in FPGA. Fast time to
market, low cost for small production volume and reprogram ability make
FPGA devices an ideal solution for military and university research. The high
speed capability and register rich architecture of FPGA an ideal implementation
of dsp algorithm.
The design implementation entailed the employment of Xilinx ISE8.2i
software tool.
Implementing the design on a vertex-II chip and hardware testing and
verification of the filter could be done. Finally simulation and synthesis with
Xilinx xst tool and RTL schematic of filter chip obtained.

REFERENCES
E. Swartzlander: Computer Arithmetic, Vol. II (IEEE Computer Society Press, Stroudsburg,
Pennsylvania, 1990)
N. Takagi, H. Yasuura, S. Yajima: High Speed VLSI multiplication algorithm with a redundant
binary addition tree, IEEE Transactions on Computers 34 (2) (1985)
A. Dempster, M. Macleod: Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters,
IEEE Transactions on Circuits and Systems II 42, 569577 (1995)
Peter Wilson Design Recipes for FPGAs first edition Elsevier publication 2007.
S Salivahanan, A Vallavaraj , C Gnanapriya Digital Signal Processing TMH fourth reprint
2005.
John o. Attia Electronics and Circuit Analysis using MATLAB CRC Press 1999.
Alan V. Oppenheim, Ronald w. Schafer, John R. Buck Discrete Time Signal Processing
second edition Prentice Hall , 1998.
Charles H. Roth,Jr. Digital System Design using VHDL Thomson eighth reprint 2006.
Stefan sjoholm, Lennart Lindth VHDL for Designers Prentice Hall ist edition 1997.

Fpga Implementation of Fir Filter

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FPGA IMPLEMENTATION OF FIR FILTER

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