Combinatorial circuits (arithmetic)

Some combinational circuits are very comment and it is worth looking at them in more detail. One particular class of very useful circuits are arithmetic circuits; i.e., those circuits used for performing operations such as: addition, subtraction, multiplication, etc. of binary numbers.

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Binary half-adder circuit

Basic definition of addition is to take two bits, and add them, producing a sum and a carry out. The circuit that produces these two outputs is called a binary halfadder.

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Binary half-adder implementation

We can draw different implementations of a binary half-adder (depends on availability of XOR gates):

!x y x !y x y sum

x y

sum

cout

cout

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Binary full-adders
Most commonly, we are interested in adding n-bit numbers. Therefore, we need to be able to also handle a carry in signal. The circuit implementing these two functions is known as a binary fulladder.

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Binary full-adder implementation

We can draw different implementations of binary full adders.

x sum cin x y

sum

cout cin

cout

Note that the 2-nd implementation uses 2 half-adders to implement the full-adder.

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Ripple adders for n-bit addition

Can build n-bit adders to add A = (an-1 an-2 a1 a0) and B = (bn-1 bn-2 b1 b0) simply by linking 1-bit full adders together.

FA

FA

FA

FA

We might want to think about the performance (delay) of this adder circuit

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Ripple adder performance (1)

Recall that we spoke about combinational logic gates having some delay (i.e., a change in an input does not cause the output to change immediately) Assume that a logic gate has delay of 1 unit. Assume that each of our full-adders is built from half-adders. We can therefore trace/identify the longest combinatorial path in the circuit. This is the path that determines the performance of the circuit;

The delay of the longest path tells us the minimum amount of time that we need to wait for the output to be correct.
x y

sum

FA
cout cin

FA

FA

FA

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Ripple adder performance (2)

For the ripple adder, it is possible that a change in the LSB of A or B (i.e., a0 or b0) will cause a change in the carry out of the MSB (i.e., cn) We can identify the longest path:

x y

sum

FA

FA

FA

FA
cout cin

We can compute the longest path for an n-bit ripple adder as follows:

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Carry look-ahead adders

Ripple adders can be very slow for large numbers of bits. If we can calculate the carry ins faster, then we can build a faster adder. Consider the i-th bit of the adder, and identify two signals, namely the propagate pi and generate gi:
x(i) y(i) p(i) s(i)

c(i+1) c(i) g(i)

Write the carry out ci+1 in terms of the pi and gi signals instead.

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Carries written as functions of the propagates and generates

We can consider writing all the carry outs in terms of the pi and gi signals, but substitute previously calculated carries as we go

We have written the carries in terms of values all computed when the inputs are applied to the circuit: All pi and gi are computed after 1 gate delay. All ci are then computed after 2 more gate delays, since the are 2-level SOP in terms of pi and gi.

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Carry look-ahead performance

If we use carry lookahead to generate all of the carries, then our adder will have a delay of 3 units of gate delay to get cn. What is the penalty to be paid? The carry lookahead circuit is 2-level logic (SOP) and we should see that higher numbered carries require more AND gates as well as AND/OR gates with a large number of inputs. It becomes impractical (cant get AND/OR gates with large numbers of inputs). It becomes expensive in terms of the number of logic gates required. So, we get better performance, but we pay for it in terms of area and cost of the circuit implementation.

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Combinations of ripple and carry look-ahead circuits

We can get something better than a ripple adder, but not as good as full carry lookahead by cascading smaller carry lookahead adders E.g., consider a 16-bit adder composed of 4, 4-bit carry lookahead adders.

4-CLA

4-CLA

4-CLA

4-CLA

Performance will be 3+2+2+2 = 9 units of gate delay to get c16 (notice a ripple adder would have required 2(16)+1 = 33 units of delay.

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Trade-off area vs. delay

Demonstration of Area vs. Delay for different ways of making an 8-bit adder. Note: delay is assumed to be time to generate c8 Note: cost is calculated as #gates+#gate inputs. Note: max gate means #inputs to the largest gate required

8-bit adder design type ripple (8, 1-bit FA) 4, 2-bit CLA 2, 4-bit CLA 1, 8-bit CLA delay 17 gates 7 gates 5 gates 3 gates cost 120 140 188 316 max gate 2 3 5 9

350 300 250 200 150 100 50 0 ripple (8, 1-bit FA) 4, 2-bit CLA 2, 4-bit CLA 1, 8-bit CLA Delay Area

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Practical comments
There is another point in generating carry look-ahead for high numbers of bits

If we dont have a large enough gate, we might have to decompose the gate into smaller gates; e.g., say we need a 5-input AND gate, but only have 2-input AND gate
We might need to do something like:

And what we thought required 1 gate delay is actually 3 gate delays.

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Binary adders/subtractors and an ALU symbol

Subtraction is fairly straightforward if we assume the numbers are 2s complement. Recall: subtraction is performed by taking the 2s complement of the subtrahend and performing addition. Take any adder circuit. We can make it a combination adder and subtraction circuit by adding XOR gates and a add/sub control signal.

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Overflow detection
When two n-bit binary numbers A and B are added together and the sum requires (n+1) bits, we say an overflow has occurred. True to either signed or unsigned arithmetic. Overflow is a problem for digital computation since we are limited in the number of bits available to represent a number. Detection of overflow depends on whether the numbers are signed or unsigned.

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Overflow detection unsigned numbers

When adding unsigned numbers, an overflow is detected if there is a carry out from the MSB.

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Overflow detection signed numbers (1)

When adding unsigned numbers, an overflow is detected if there is a carry out from the MSB. No possibility of overflow if numbers are opposite in sign, since result will be smaller than the larger of the two numbers.

Examples of overflow: assume 8-bits available (-128 to +127); carry into and out of the MSB shown.

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Overflow detection signed numbers (2)

Notice that in both of the previous cases, the sign bit (the MSB) indicates a negative result when it should have been a positive result. We can detect the overflow by examining the carry in and carry out of the MSB. If not equal, then there is overflow: The circuit: If numbers are unsigned C=1 means overflow, otherwise result good. If numbers are signed, then V=1 means overflow, otherwise result good.

C V

FA (MSB)

FA

FA

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Binary multipliers
Multiplication of binary numbers works exactly like in decimal:

Since numbers are binary, the multiplication of a_i (multiplier bit) with B can be done with AND. When a_i = 0, we add 0 to the partial product. When a_i = 1, we add the multiplicand to the partial product. To multiply 2, n-bit numbers we need 2n-bit output.

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Example of binary multiplication

Simple example ; 7 x 6 = 42

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Circuit for a binary array multiplier

Since multiplication is just ANDs and addition, we can make an array multiplier with AND gates and 1-bit FAs. Example: An array multiplier for 4-bit numbers (8-bit output):
b3 b2 b1 b0 a0 0 a1 0 a2 0 a3 0

ppi bi aj

FA

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