Index

S. no
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

TOPIC
Write a VHDL Program to implement a 3 :8 decoder. Write a VHDL Program to implement a 8:1 multiplexer using behavioral modeling. Write a VHDL Program to implement a 1 :8 demultiplexer using behavioral modeling. Write a VHDL Program to implement 4 bit comparator Write a program to perform serial to parallel transfer of 4 bit binary number. Write a program to perform parallel to serial transfer of 4 bit binary number. Write a VHDL Program to generate Mod10 up counter. Write a VHDL program to implement half adder. Write a VHDL program to implement full adder. Write a VHDL program to implement full subtractor.

DATE SIGN

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PROGRAM:- 1

AIM:- VHDL Program to implement a 3 :8 decoder. SOFTWARE USED:- Modelsim. PROGRAM:Library ieee; Use ieee.std_logic_1164.all; Entity decoder is port(a,b,c:in bit; z:out bit_vector(0 to 7)); end decoder; architecture decoder_concurrent of decoder is signal abar,bbar,cbar,enable:bit; begin z (0)<= not(abar and bbar and cbar and enable); z (1)<= not(abar and bbar and c and enable); z (2)<= not(abar and b and c and enable); z (3)<= not(a and b and c and enable); z (4)<= not(a and bbar and cbar and enable); z (5)<= not(a and b and cbar and enable); z (6)<= not(abar and b and cbar and enable); z (7)<= not(a and b and cbar and enable); abar<= not a; bbar<= not b; cbar<= not c; end decoder_concurrent;

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PROGRAM:- 2
AIM:- VHDL Program to implement a 8:1 multiplexer using behavioral modeling. SOFTWARE USED:- Modelsim. PROGRAM:Library ieee; Use ieee.std_logic_1164.all; entity mux is port(s0,s1,s2:in bit; a:in bit_vector(0 to 7); z:out bit); end mux; architecture mux1_behavioural of mux is begin process(s0,s1,s2,a(0),a(1),a(2),a(3),a(4),a(5),a(6),a(7)) begin if s0='0' and s1='0' and s2='0' then z<=a(0); elsif s0='0' and s1='0' and s2='1' then z<=a(1); elsif s0='0' and s1='1' and s2='0' then z<=a(2); elsif s0='0' and s1='1' and s2='1' then z<=a(3); elsif s0='1' and s1='0' and s2='0' then z<=a(4); elsif s0='1' and s1='0' and s2='1' then z<=a(5); elsif s0='1' and s1='1' and s2='0' then z<=a(6); else
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z<=a(7); end if; end process; end mux1_behavioural;

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PROGRAM:- 3
AIM:- VHDL Program to implement a 1 :8 demultiplexer using behavioral modeling. SOFTWARE USED:- Modelsim. PROGRAM:Library ieee; Use ieee.std_logic_1164.all; entity demux is port(s0,s1,s2:in bit; a:in bit; q:out bit_vector(0 to 7)); end demux; architecture demux1_behavioural of demux is begin process(a,s0,s1,s2) begin if s0=0 and s1=0 and s2=0 then y<= q0; elsif s0=0 and s1=0 and s2=1 then y<= q1; elsif s0=0 and s1=1 and s2=0 then y<= q2; elsif s0=0 and s1=1 and s2=1 then y<= q3; elsif s0=1 and s1=0 and s2=0 then y<= q4; elsif s0=1 and s1=0 and s2=1 then

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y<= q5; els if s0=1 and s1=1 and s2=0 then y<= q6; else y<= q7; end if; end process; end architecture demux1_behavioural;

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PROGRAM:- 4
AIM:- VHDL Program to implement 4 bit comparator. SOFTWARE USED:- Modelsim. PROGRAM:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity comp is port (A,B: in bit_vector(0 to 3); AgtB, AeqB, AltB: out bit); end comp; architecture comp_beh of comp is begin process(A,B) begin if (A>B) then Agt<='1'; Aeq<='1'; Alt<='1'; elsif (A>B) then Alt<= '1'; Aeq<= '0'; Alt<= '0'; else A=B Aeq<='1'; Agt<='0'; Alt<='0'; end if; end process; end comp_beh;
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PROGRAM:- 5
AIM:- VHDL program to perform serial to parallel transfer of 4 bit binary number. SOFTWARE USED:- Modelsim. PROGRAM:Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; entity spaft_reg is port (din, clk, clr,pr, in bit; y : out bit_vector (0 to 3)); end spaft_reg; architecture spaft_regbeh of spaft_reg is begin process (clk, clr, pr) begin if (clr = '1' and pr = '1' and clk = '0' and clk'event) then y(0) <= din; y(1) <= y(0); y(2) <= y(1); y(3) <= y(2); elsif(clr = '1' and pr = '0') then y(0) <= '1'; y(1) <= '1'; y(2) <= '1';
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y(3) <= '1'; elsif(clr = '0' and pr = '1') then y(0) <= '0'; y(1) <= '0'; y(2) <= '0'; y(3) <= '0'; end if; end process; end spaft_regbeh;

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PROGRAM:- 6
AIM:- VHDL program to perform parallel to serial transfer of 4 bit binary number. SOFTWARE USED:- Modelsim. PROGRAM:Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; entity paft_reg is port (din ; in bit_vector (0 to 3); clk, clr, pr ; in bit; y ; out bit_vector (0 to 3)); end part_reg; architecture paft_regbeh of paft_reg is begin process (clk, clr, pr) begin if (clr = '1' and pr = '1' and clk = '0' and clk'event) then y <= din; elsif (clr = '1' and pr = '0') then y <= '1111'; elsif (clr = '0' and pr = '1') then
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y <= '0000'; end if; end process; end paft_regbeh;

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PROGRAM:- 7

AIM:- VHDL Program to generate Mod- 10 up counter. SOFTWARE USED:- Modelsim. PROGRAM:Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith..all; Entity upcount is Port (clk, sload, clr: in bit; Q: out bit_vector(3 downto 0)); End upcount; Architecture up_behav of upcount is Signal Tmp: bit _vector(3 downto 0); Begin Process (clk) Begin If (clk event and clk =1) then If clr = 1 then Tmp <= 0000; Elsif sload = 1 then If Tmp = 1010 then Tmp<= 0000; Else Tmp <= Tmp + 1; End if; End process; Q<= Tmp;
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End up_behav;
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PROGRAM:- 8 AIM:- VHDL Program to implement half adder.

SOFTWARE USED:- Modelsim. PROGRAM:library ieee; use ieee.std_logic_1164.all; entity HA is Port(A,B:in bit; sum, carry:out bit): end HA; architecture struct of HA is component XOR2 port(L,M: in bit; N: out bit); component AND2 port(X,Y: in bit; Z: out bit); end component; begin X1:XOR2 portmap(A,B,sum); A1:AND2 portmap(A,B:carry); end struct;

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PROGRAM:- 9
AIM:VHDL Program to implement full adder. SOFTWARE USED:- Modelsim. PROGRAM:library ieee; use ieee.std_logic_1164.all; entity FA is Port(A,B,CIN:in bit; s, cout:out bit): end FA; architecture STRUCTURE of FA is component XOR_2 port (A, B : in BIT; Z : out BIT); end component; component AND_2 port (A, B : in BIT; Z : out BIT); end component; component OR_2 port (A, B : in BIT; Z : out BIT); end component; begin X1 : XOR_2 port map (A => A_IN, B => B_IN, Z => S1);
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X2 : XOR_2 port map (A => S1, B => C_IN, Z => S); A1 : AND_2 port map (A => S1, B => C_IN, Z => S2); A2 : AND_2 port map (A => A_IN, B => B_IN, Z => S3); O1 : OR_2 port map (A => S2, B => S3, Z => COUT); End STRUCTURE;

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PROGRAM:- 10
AIM:- Write a VHDL program to implement full subtractor. SOFTWARE USED:- Modelsim. PROGRAM:Library ieee; Use ieee.std_logic_1164.all; Entity fullsub is Port(a,b, bin:in bit;
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diff,borout: out bit); end fullsub; architecture fa_dataflow of fullsub is signal m,n,o: bit; begin m<= not a; n<= not b; o<= not bin; diff<= (a xor b) xor c; borout<= (m and b) or (m and bin) or (b and bin); end fa_dataflow;

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Vill. Golpura, Teh. Barwala Distt. Panchkula (HR).

PRACTICAL FILE OF VHDL

Submitted To: Er. SHIKHA (Lecturer) ECE DEPTT.

Submitted by: MAYANK GUPTA 5509092 6TH SEMESTER Electronics and communication

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