ELECTRICAL INTERFACE CONTROL DRAWING

Wi.Freestar Module

905 Messenger Lane Moore, OK 73160 405-794-7730 2004 Radiotronix Inc, all rights reserved

Design Report v0.6

TABLE OF CONTENTS 1 2 3 4 5 6 SCOPE ..........................................................................................................3 REVISION CONTROL ...................................................................................3 APPLICABLE DOCUMENTS.........................................................................3 TOP LEVEL BLOCK DIAGRAM ....................................................................4 PIN DEFINTIONS ..........................................................................................4 CONNECTOR CONFIGURATION.................................................................6

Design Report v0.6

SCOPE
THIS DRAWING DESCRIBES THE ELECTRICAL INTERFACES ASSOCIATED WITH THE WI.FREESTAR MODULE.

REVISION CONTROL
DATE 05/13/05 5/13/05 8/15/05 10/19/05 CHANGES INITIAL DRAFT INITIAL DRAFT CORRECTIONS CHANGE PORT A PIN 7 DESCRIPTION FOR WAKE UP ON INTERRUPT CORRECT RXD AND TXD I/O DESCRIPTION REVISION 0.0 0.1 0.2 0.3

APPLICABLE DOCUMENTS

NO REFERENCED DOCUMENTS

Design Report v0.6

TOP LEVEL BLOCK DIAGRAM

TO BE DRAWN

5
PIN ANT2 TPRF1 1 2 3 4 5

PIN DEFINTIONS
TYPE AO/AI AO/AI GND GND GND GND DI/DO SIGNAL NAME ANT2 TPRF1 GND GND GND GND PTD3 ELECTRICAL DESCRIPTION INTEGRATED PBC F-ANTENNA COAXIAL RF TEST POINT 50 OHMS GROUND GROUND GROUND GROUND GENERAL PURPOSE DIGITAL I/O FIRMWARE CONFIGURABLE, PORT D , BIT 3 GENERAL PURPOSE DIGITAL I/O FIRMWARE CONFIGURABLE, PORT D , BIT 4 ANALOG TO DIGITAL CONVERTER INPUT, PORT B , INPUT 0 ANALOG TO DIGITAL CONVERTER INPUT, PORT B , INPUT 1 PRIMARY POWER INPUT: VCC = 2.7 TO 3.6 VDC, TBD mA MAX. GROUND FCC / PRODUCTION TEST MODE INPUT WORD, BIT 0 FCC / PRODUCTION TEST MODE INPUT WORD, BIT 1 FCC / PRODUCTION TEST MODE INPUT WORD, BIT 2 GENERAL PURPOSE DIGITAL I/O FIRMWARE CONFIGURABLE PORT A, BIT 4, KBI1P4 (KEYBOARD INTERRUPT) GENERAL PURPOSE DIGITAL I/O FIRMWARE CONFIGURABLE PORT A, BIT 5, KBI1P5 (KEYBOARD INTERRUPT)

DI/DO

PTD4

AI

PTB0

AI

PTB1

PI

VCC

10 11 12 13 14

GND DI DI DI DI/DO

GND MODE0 MODE1 MODE2 PTA4

15

DI/DO

PTA5

Design Report v0.6

PIN 16

TYPE DI/DO

SIGNAL NAME PTA6

ELECTRICAL DESCRIPTION GENERAL PURPOSE DIGITAL I/O FIRMWARE CONFIGURABLE PORT A, BIT 6, KBI1P6 (KEYBOARD INTERRUPT) DIGITAL INPUT CONFIGURED TO INTERRUPT ON RISING EDGE OF SIGNAL TO WAKE UP MODULE FROM SLEEP MODE. PORT A, BIT 7, KBI1P7 (KEYBOARD INTERRUPT) PORT G, BIT 0, BKGD/MS (BACKGROUND/MODE SELECT, FOR PROGRAMMING AND FIRMWARE DEBUG MASTER RESET, ACTIVE LOW GENERAL PURPOSE DIGITAL I/O FIRMWARE CONFIGURABLE PORT C, BIT 0, SCI2 TXD2 (SERIAL COMMUNICATION INTERFACE 2, TRANSMIT DATA) GENERAL PURPOSE DIGITAL I/O FIRMWARE CONFIGURABLE PORT C, BIT 1, SCI2 RXD2 (SERIAL COMMUNICATION INTERFACE 2, RECEIVE DATA) RESERVED

17

DI

PTA7

18

DI/DO

PTGO

19 20

DI DI/DO

/RESET PTC0

21

DI/DO

PTC1

22

DI/DO

PTC5

23 24 25 26 27 28 29 30

DO DI GND GND GND GND GND GND

TXD RXD GND GND GND GND GND GND

APPLICATION TRANSMIT DATA OUTPUT (SCI1, TXD1) APPLICATION RECEIVE DATA INPUT (SCI1, RXD1) GROUND GROUND GROUND GROUND GROUND GROUND

LEGEND: DI = DIGITAL INPUT DO=DIGITAL OUTPUT AI=ANALOG INPUT AO = ANALOG OUTPUT PI = POWER INPUT GND = GROUND LOGIC INPUT HIGH: LOGIC INPUT LOW: LOGIC OUTPUT HIGH: LOGIC OUTPUT LOW: 0.8 (VCC) < VIH < (VCC) 0 < VIL < 0.2 (VCC) (VCC 0.4) < VOH < VCC 0 < VOH < 0.4

Design Report v0.6

CONNECTOR CONFIGURATION

Note that PIN Numbering begins at top left-hand side with pin number 1 and follows counter-clockwise about the perimeter of the module.

Design Report v0.6