VLSI Interview Questions

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VLSI Interview Questions -------------------------------------------------------------------------For Any answers you may contact Aviral Mittal at avimit@yahoo.com CopyRight (C) Aviral Mittal -------------------------------------------------------------------------1(a). What you would use in RTL a 'boolean' type or a 'std_logic' type and why. 1(b). What are/may be the implications of using an 'integer' type in RTL. 2). What you would use a RAM or a regle discuss: RAM: Low Power, Low Area REGFILE: better timing. 3). A timing path fails: what are your options? Ans: a). Look for parallelism in RTL. b). Look for small RAMs which might be synthesized c). Look for better placement d). Look for Pipelining opportunity e). Look for moving logic before the Reg f). Look for replicating the drivers to reduce load if the delay is caused by loading g). '< or >' are better than -, when comparators are used in RTL h). Look for if..elsif..elseif..elsif i). Use One Hot instead of Binary coded State Registers 4). Any example you can provide in which verilog might be a prob 5). What are VHDL structures, give an example to exploit them 6). What is grey coding, any example where they are used 7). Discuss Async interfaces 8). Metastability 9). Synopsys unwanted latch 10). Verilog blocking vs non-blocking 11). VHDL variables: example where you have to use them 12). What is pipelining and how it may improve the performance 13). What are multicycle paths. 14). What are false paths 15). What are Async counters, what are advantages of using these over sync counters. and what are the disadvantages 16). q_in : IN std_logic variable q0 : std_logic variable q1 : std_logic variable q2 : std_logic q_out : OUT std_logic; if(rising_edge(clk)) then q0 := q_in; q1 := q0; q2 := q1; q_out <= q2;
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VLSI Interview Questions

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endif; what will be the result. 17). Sensitivity List: How does it matter.What will happen if you dont include a signal in the sensitivity list and use/read it inside the process 18). process(a_sig,b_sig) begin if(a_sig = '1' and b_sig = '0') then sig_out <= '1'; else sig_out <= '0'; end if; end process process(c_sig,d_sig) begin if(c_sig = '1' and d_sig = '0') then sig_out <= '1'; else sig_out <= '0'; end if; end process Any thing wrong with the above code Ans: Same signal being driven in two dierent processes 19). While writing a state machine in RTL it is generally recommended that the seq and combi logics should be written in dierent processes Even if its not a state machine, it is recommended that seq and combi logics should be written in dierent processes Any example you may give to support this recommendation Ans: Sometime its desired to use the 'next_RegValue' which can only be accessed in recommended method, not in the method where you combine seq and combi parts into one seq process. 20). Following are two methods to determine if 'a_sig' is greater than 'b_sig' Which one would you use and why? signal a_sig : std_logic_vector(n downto 0); signal b_sig : std_logic_vector(n downto 0);

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VLSI Interview Questions

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process(a_sig,bsig) variable c_sig : std_logic_vector(n downto 0); begin c_sig := a_sig-bsig; a_is_smaller <= c_sig(c_sig'high); end process; process(a_sig,bsig) variable c_sig : std_logic_vector(n downto 0); begin if(asig < bsig) then a_is_smaller <= '1'; else a_is_smaller <= '0'; end if; end process; 21). How you will implement a C language pointer in VHDL 22). A certain chip(silicon) fails hold test and another fails a setup test. Which one MAY still be used how and why 23). What is Design For Test and why it is done. 24). What is clock gating? How and why it is done. 25). Low Power: discuss how it may be done Ans : a) Clock Gating b) Reducing the frequency of operation using pipelining c) Shutting the power down d) Dierent voltage domains e) Reducing number of transitions, eg. using grey coding f) Bus Invert coding: invert bus if hamming distance is greater than 1/2 word size g) Async design techniques 26). Discuss disadvantages/challenges of shrinking technology Ans : Leakage Power 27). Simulation Problem. Register going 'X' even when RTL has reset pin dening the state of register at power up reset. And such a reset has been applied in simulation. 28). Generally dc_shell tries to optimise the path with worst violation. Is there any thing that you can do to make it work on more paths parallely Ans :Use group_path may be with 'critical_range' on that group 29). What is pipelining, how may it aect the performance of a design 30). What is the dierence between transport delays and inertial delays in VHDL

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VLSI Interview Questions

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31). What determines the max frequency a digital design may work on. Why thold(hold time) is not included in the calculation for the above. 32). What will happen if output of an inverter is shorted to its input 33). What is noise margin. 34). Why are p-mos larger than n-mos in CMOS design 35). Draw DC curve of inverter and Re-Draw it if pmos and nmos are equal 36). What is Latch-up 37). How can an Inverter work as an amplier 38). Design a state machine to implement a edge detector That is. The output of this state machine is a pulse of logic '1' of duration one clock when ever there is a negative edge on an input signal. Given that the frequency at which the negative edge is appearing on the input signal is low as compared to the clock of the state machine 39). Design a state machine which divides the input frequency of a clock by 3. Given that the phase change in the output due to propogation delay in of the ip op is acceptable up to a delay oered by a single ip op only. 40). Why does a pass gate requires two transistors(1 N and 1 P type) Can we use a single transistor N or P type in a pass gate? If not why? and if yes then in what conditions? 41). Why CMOS why not N-MOS or P-MOS logic, when we know that the number of gates required in CMOS are grater than in n-mos or p-mos logic. 42). How much is the max fan out of a typical CMOS gate. Or alternatively, discuss the limiting factors. 43). What are dynamic logic gates? What are their advantages over conventional logic gates 44). Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles 45). What is the relation between binary encoding and grey(or gray) encoding. 46). Write a vhdl function to implement a length independent grey code counter. alternatively, discuss the logic to do that. 47). How you will constraint a combinational logic path through your design in dc_shell. 48). Make a T Flip Flop using a D Flip Flop

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49). How you will make a Nand Gate function like an inverter. 50). Design a state machine to detect a '1101' pattern in a stream. Detect both, overlapping and non overlapping patterns. 51). From a CMOS logic gate IC, the 40xx series, Take an inverter IC, power it up, and leave the input of the inverter oating. Comment upon the ouput of this inverter. Similarly take a TTL logic gate IC, the 74xx series. Take an inverter IC, power it up, and leave the input of the inverter oating. Comment upon the output of this inverter. 52). What are LFSRs, example usage? 53). What are MISRs, example usage?

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