INTERCONNECT STRATEGIES

Length Matching for High-Speed Differential Pairs

Loops and serpentines can add length to eliminate imbalance in your differential pairs.

shows the orientation of differential pins in a side-by-side nificance of length matching for highfashion that simplifies length matching. Another orientation speed differential pairs and how to for differential pair component pins is adjacent configuraachieve it. When routing high-speed diftion, for which one of the traces is normally shorter. FIGURE ferential pairs two important considera6 depicts two ways of achieving length balance for such tions include1: cases. 1. Maintaining constant separation FIGURE 6a indicates where additional length may be between traces (for impedance effectively inserted, and FIGURE 6b illustrates how to incorABE RIAZI control). porate bends for length increase. Bends are also frequently applied towards length equality when the differential pins 2. Achieving length matching (for optiare oriented diagonally, as depicted in FIGURE 7. mum timing margins, preventing common-mode signals and EMI). Another consideration is the role of etch on pads, Whenever the above conditions cannot be satisfied demonstrated by FIGURE 8. The symmetry rule as applied simultaneously, meeting condition 2 is more critical than 1; to etch on pads is depicted by FIGURE 8a. The size of etch subsequently, cases arise in which one trace length is increased to satisfy length matching at the expense of violating equal Because signal velocity is FASTER FOR OUTER LAYER separation. TRACES THAN FOR INNER LAYER TRACES, One case that necessitates adding lengths to eliminate length imbalance is propagation delay is smaller for the outer layer. shown below. In FIGURE 1, the receiver package trace for Sig- is shorter than that of Sig+ (i.e., LR2<LR1), within a given pad is electrically part of the pad, but many forcing the lengthening of the Sig- trace (i.e., L2_PCB). It is PCB CAD tools count this length as part of the total trace. marked that a suitable place to add length is in the proximiHowever, if the amount of routing into each pad (or pin) of ty of the receiver pin (near the source of length imbalance). the pair is identical, then automatic measurement may be This may prove useful for mode shift reduction2. applied. Subsequently, for accurate length matching, it is advantageous to route the differential pair in a way that FIGURE 2 illustrates length inequality caused by bends. maintains symmetry for the etch within the pad as illustratCompensation for length difference should be performed ed in Figure 8a rather than asymmetrically as shown by close to the mismatch location. Two ways of adding length are demonstrated by FIGURE 3. FIGURE 8b. The use of a single loop for adding length is shown by Many circumstances, such as when quantifying effects of length adjustments, necessitate converting a change in FIGURE 3a, while in FIGURE 3b trace length is increased trace length Y to a change in propagation time ( T), govusing small serpentines. Here it is desirable3 for D>3W and erned by: S2<2S1. When there are multiple bends present, length matching may result without additional adjustments. FIGY = V * T (Equation 1) URE 4 depicts length equality accomplished for segments spanning P1 to P2 by virtue of an even number of U-turns. The component pins for connecting inverting and noninverting pins are usually next to each other. FIGURE 5

THIS COLUMN WILL DISCUSS the sig-

FIGURE 1. A topology with unequal receiver package lengths requires a PCB trace length adjustment.
FEBRUARY 2005

FIGURE 2. Here the inner bend trace is shorter than the outer one.

FIGURE 3. Adding length by: a) a single loop and b) small serpentines.

FIGURE 4. The differential pair trace lengths from P1 to p2 are equal due to an even number of U-turns.
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INTERCONNECT STRATEGIES
The signal velocity is faster for outer layer traces (microstrip) than for inner layer (stripline) traces. Therefore, propagation delay is smaller for the outer layer. For example, an FR-4 substrate for microstrip Tpd can assume 150160 ps/in (= 1.8 1.92 ns/ft), and for stripline Tpd spans 170-180 ps/in (= 2.04 2.16 ns/ft). A typical approximation used for for an FR-4 PCBs velocity4 is V=6.0 in/ns (~ 0.5 vacuum speed of light), corresponding to Tpd = 2.0 ns/ft (or 0.167 ps/mil). Subsequently, a Y of .025 translates to T of ~ 4.2 ps, and a length difference of .010 allows controlling time within ~ 1.7 ps. PCD&M
ABE (ABBAS) RIAZI is a senior signal integrity engineer with ServerWorks in Santa Clara, CA; ariazi@serverworks.com

FIGURE 5. Side-by-side orientation of differential pairs offers natural length matching.

FIGURE 7. The use of bends in diagonal orientation for length equality.

FIGURE 6. Length balance for adjacent configuration by: a) adding length and b) incorporating bends.

FIGURE 8. Etch located within pad a) symmetrically and b) asymmetrically.

The author would like to thank David Gee, Peter Arnold, Jeremy Plunkett and Dean Gonzales for valuable comments.

In Eq. 1, V represents signal velocity. Sometimes, it is preferable to utilize the propagation delay Tpd in formulations (rather than V). The Tpd parameter is simply the reciprocal of V (i.e., Tpd = 1/V). Hence, Eq. 1 can be rewritten as: Y = T/Tpd Also, T = Tpd * Y (Equation 2)

REFERENCES
1. Abe Riazi, Differential Signals Routing Requirements, Printed Circuit Design & Manufacture, February 2004, pp. 22-23. 2. Douglas Brooks, Adjusting Signal Timing (Part 1), available at www.ultracad.com 3. Scott Gardiner, Cliff Lee, PCI Express Desktop System Board and Add-in Card Design Guidelines, Intel Corp., September 2003. 4. Lee W. Ritchey, Right the FirstTime: A Practical Handbook on High-Speed PCB and System Design, Volume 1, Speeding Edge, summer 2003, p. 34.

(Equation 3)

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