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HDL LAB (ECL68)-SYLLABUS

EXPT.NO. Name of Experiment Software Experiments Basic gates 8:1 /4:1Multiplexer 1:8/1:4 De Multiplexer 8:3 Encoder With Priority 8:3 Encoder Without Priority 2:4 Decoder 4 bit Comparator 4 bit Binary to Gray conversion 4 bit Gray to Binary conversion 8 bit ALU Full Adder(3 Different Modeling styles) D Flip Flop T Flip Flop SR Flip Flop JK Flip Flop BCD Counter(Synchronous and Asynchronous) Binary Counter(Synchronous and Asynchronous) Hardware interfacing Experiments Basic gates Control speed and direction of Stepper motor Control external lights using relays Generation of different waveforms using DAC i. Sine waveform ii. Square waveform iii. Triangle waveform iv. Ramp waveform Control speed and direction of DC motor

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

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1. Write HDL code to implement all Basic gates and verify. AIM: To design all the logic gates using dataflow modeling style and verifies the functionalities along with their synthesis and simulation reports. Truth Table: A B 0 0 0 1 1 0 1 1

y_not 1 1 0 0

y_or 0 1 1 1

y_and 0 0 0 1

y_nor 1 0 0 0

y_nand 1 1 1 0

y_xor 0 1 1 0

y_xnor 1 0 0 1

VHDL Code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity all_gates is Port ( A,B : in std_logic; y_not : out std_logic; y_or : out std_logic; y_and : out std_logic; y_nor : out std_logic; y_nand : out std_logic; y_xor : out std_logic; y_xnor : out std_logic); end all_gates; architecture Behavioral of all_gates is begin y_not <= not A; y_or <= A or B; y_and <= A and B; y_nor <= A nor B; y_nand <= A nand B; y_xor <= A xor B; y_xnor <= A xnor B; end Behavioral;

VERILOG Code:
module all_gate(a,b, y_not, y_or, y_and, y_nor, y_nand, y_xor,y_xnor); 2

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input a; input b; output Y_not, y_or, y_and, y_nor, y_nand, y_xor,y_xnor; assign y_or = a | b; assign y_and = a & b; assign Y_not = ~ a; assign y_nand = ~( a & b ) ; assign y_nor = ~ (a | b); assign y_xor = a ^ b ; assign y_xnor = ~ (a ^ b); endmodule

SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

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Output Waveform:

CONCLUSION/RESULT: Basic logic gates NOT, AND, OR, NOR, NAND, XOR, XNOR are designed in dataflow model and outputs are verified using test bench.

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2. Write HDL code to implement 8:1Multiplexer and verify.

AIM: To design a 8:1 multiplexer using behavioral model and verify its functionality using the

test bench. Truth Table: SEL2

0 0 0 0 1 1 1 1 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Mux8_1 is port ( SEL: in STD_LOGIC_VECTOR(2 downto 0); A,B,C,D,E,F,G,H :in STD_LOGIC; MUX_OUT: out STD_LOGIC); end Mux8_1;

SEL1
0 0 1 1 0 0 1 1

SEL1
0 1 0 1 0 1 0 1

MUX_OUT A B C D E F G H

architecture behavioural of Mux8_1 is begin process (SEL,A,B,C,D,E,F,G,H) begin case SEL is when "000" => MUX_OUT <= A; when "001" => MUX_OUT <= B; when "010" => MUX_OUT <= C; when "011" => MUX_OUT <= D; when "100" => MUX_OUT <= E; when "101" => MUX_OUT <= F; when "110" => MUX_OUT <= G; when "111" => MUX_OUT <= H; when others => null; end case; end process; 5

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end behavioural;

VERILOG Code: module mux8_1v(A,B,C,D,E,F,G,H ,sel, MUX_OUT); input A,B,C,D,E,F,G,H; input [2:0] sel; output MUX_OUT; reg MUX_OUT; always@(sel, A,B,C,D,E,F,G,H) begin case(sel) 3'd0 : MUX_OUT = A; 3'd1 : MUX_OUT = B; 3'd2 : MUX_OUT = C; 3'd3 : MUX_OUT = D; 3'd4 : MUX_OUT = E; 3'd5 : MUX_OUT = F; 3'd6 : MUX_OUT = G; 3'd7 : MUX_OUT = H; endcase end endmodule

SYNTHESIS RESULTS:

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SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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3. Write HDL code to implement 1:8 De-Multiplexers. AIM: To design a 1:8 De-Multiplexer and verify its functionality and check its simulation report. Truth Table: Enable S2
1 0 0 0 0 0 0 0 0 X 0 0 0 0 1 1 1 1

S1
X 0 0 1 1 0 0 1 1

S1
X 0 1 0 1 0 1 0 1

Y[0]
0 din 0 0 0 0 0 0 0

Y[1]
0 0 din 0 0 0 0 0 0

Y[2]
0 0 0 din 0 0 0 0 0

Y[3]
0 0 0 0 din 0 0 0 0

Y[4]
0 0 0 0 0 din 0 0 0

Y[5]
0 0 0 0 0 0 din 0 0

Y[6]
0 0 0 0 0 0 0 din 0

Y[7]
0 0 0 0 0 0 0 0 din

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1X8 is Port ( din : in std_logic; enable : in std_logic; sel : in std_logic_vector(2 downto 0); y : out std_logic_vector(7 downto 0)); end demux1X8; architecture Behavioral of demux1X8 is begin process(enable, din,sel) begin if(enable=1)then y<=(others=>0); else case sel is when "000" => y(0) <= din ; when "001" => y(1) <= din ; 8

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when "010" => y(2) <= din ; when "011" => y(3) <= din; when "100" => y(4) <= din ; when "101" => y(5) <= din ; when "110" => y(6) <= din ; when "111" => y(7) <= din ; when others => null; end case; end if; end process; end Behavioral; VERILOG Code: module demux1_8v(din, sel, y); input din; input [0:2] sel; output [0:7] y; // reg din; // reg [0:2] sel; wire din; wire [0:2] sel; reg [0:7]y; always@(sel,din) begin case (sel) 3'b000:y=8'b10000000; 3'b001:y=8'b01000000; 3'b010:y=8'b00100000; 3'b011:y=8'b00010000; 3'b100:y=8'b00001000; 3'b101:y=8'b00000100; 3'b110:y=8'b00000010; 3'b111:y=8'b00000001; default:y=8'b11111111; endcase end endmodule

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SYNTHESIS RESULTS:

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SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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4. Write a HDL program for the 8 to 3 Encoder with priority and Verify.
Truth Table: enable Din7 1 X X 0 X 0 X 0 X 0 X 0 X 0 0 X 0 1 VHDL Code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pri_enc is Port ( enable : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end pri_enc; architecture Behavioral of pri_enc is begin process(enable,din) begin if(enable='1')then dout<=(others=>'0'); else if(din(0)='1')then dout<="000"; elsif(din(1)='1')then dout<="001"; elsif(din(2)='1')then dout<="010"; elsif(din(3)='1')then dout<="011"; 12

Din6 X X X X X X X 1 0

Din5 X X X X X X 1 0 0

Din4 X X X X X 1 0 0 0

Din3 X X X X 1 0 0 0 0

Din2 X X X 1 0 0 0 0 0

Din1 X X 1 0 0 0 0 0 0

Din0 X 1 0 0 0 0 0 0 0

Dout2 Dout1 Dout0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

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elsif(din(4)='1')then dout<="100"; elsif(din(5)='1')then dout<="101"; elsif(din(6)='1')then dout<="110"; elsif(din(7)='1')then dout<="111"; else dout<="000"; end if; end if; end process; end Behavioral; VERILOG Code: module pri_enc (DIN,DOUT,enable); input [7:0] DIN; output [2:0] DOUT; input enable; reg [2:0] DOUT; always @(DIN,enable) begin if(enable==1'b1) DOUT=3'b000; else begin casex (DIN) 8'bxxxxxxx1 : DOUT= 3'b000; 8'bxxxxxx10 : DOUT= 3'b001; 8'bxxxxx100 : DOUT= 3'b010; 8'bxxxx1000 : DOUT= 3'b011; 8'bxxx10000 : DOUT= 3'b100; 8'bxx100000 : DOUT= 3'b101; 8'bx1000000 : DOUT= 3'b110; 8'b10000000 : DOUT= 3'b111; default : DOUT=3'b000; endcase end end endmodule

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SYNTHESIS RESULTS:

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SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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5. Write a HDL program for the 8 to 3 Encoder without priority and Verify. Truth Table: enable Din7 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Din6 X 0 0 0 0 0 0 1 0 Din5 X 0 0 0 0 0 1 0 0 Din4 X 0 0 0 0 1 0 0 0 Din3 X 0 0 0 1 0 0 0 0 Din2 X 0 0 1 0 0 0 0 0 Din1 X 0 1 0 0 0 0 0 0 Din0 X 1 0 0 0 0 0 0 0 Dout2 Dout1 Dout0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3wpvh is Port ( enable : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end encoder8_3wpvh ; architecture Behavioral of encoder8_3wpvh is begin process(enable,din) begin if (enable='1') then dout<="000"; else case din is when "00000001"=> dout<="000"; when "00000010"=> dout<="001"; when "00000100"=> dout<="010"; when "00001000"=> dout<="011"; when "00010000"=> dout<="100"; when "00100000"=> dout<="101"; when "01000000"=> dout<="110"; when "10000000"=> dout<="111"; when others => dout<="000"; end case; 16

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end if; end process; end Behavioral; VERILOG Code: module encoder8_3v(din,enable,dout); input [7:0] din; input enable; output [2:0] dout; reg [2:0] dout; always @(din,enable) begin if (enable == 1'b1) dout = 3'b000; else begin case (din) 8'b00000001 : dout=3'b000; 8'b00000010 : dout=3'b001; 8'b00000100 : dout=3'b010; 8'b00001000 : dout=3'b011; 8'b00010000 : dout=3'b100; 8'b00100000 : dout=3'b101; 8'b01000000 : dout=3'b110; 8'b10000000 : dout=3'b111; default : dout=3'b000; endcase end end endmodule

SYNTHESIS RESULTS:

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SIMULATION RESULTS: INPUT Test bench waveform:

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Output Waveform:

6. Write HDL code to implement 2:4 Decoder and verify.

Truth Table: enable Din1 1 X 0 0 0 0 0 1 0 1
VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

Din0 X 0 1 0 1

Dout3 Dout2 Dout1 Dout0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0

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entity decoder2_4vh is Port ( enable : in std_logic; din : in std_logic_vector ( 1 downto 0 ); dout : out std_logic_vector ( 3 downto 0 )); end decoder2_4vh; architecture Behavioral of decoder2_4vh is begin process (enable,din) begin if(enable = '1')then dout <= "0000"; else case din is when "00" => dout <= "0001" ; when "01" => dout <= "0010" ; when "10" => dout <= "0100" ; when "11" => dout <= "1000" ; when others => dout <= "0000"; end case; end if; end process; end Behavioral;

VERILOG Code: module decoder2_4v(enable,din,dout); input enable; input [1:0] din; output [3:0] dout; reg [3:0] dout; always @(enable,din) begin if (enable==1'b1) begin dout=4'b0000; end else begin case(din) 2'b00 : dout=4'b0001; 2'b01 : dout=4'b0010; 20

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2'b10 : dout=4'b0100; 2'b11 : dout=4'b1000; endcase end end endmodule

SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

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Output Waveform:

7.

Write HDL code to implement 4-bit Comparator and verify.

Truth Table: enable
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1

A
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1

B
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1

aeb
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

agb
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0

alb
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity comp is Port ( enable : in std_logic; a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); aeb,agb,alb : out std_logic); end comp; architecture Behavioral of comp is begin process(enable,a,b) variable x,y,z:std_logic; begin if(enable='1')then x:='0'; y:='0'; z:='0'; else if(a=b)then x:='1'; y:='0'; z:='0'; elsif(a>b)then x:='0'; y:='1'; z:='0'; else x:='0'; y:='0'; z:='1'; end if; end if; aeb<=x; agb<=y; alb<=z; end process; end Behavioral; VERILOG Code: module comparator(a,b,en,aeb,agb,alb); input [3:0] a; input [3:0] b; input en; output aeb; 23

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output agb; output alb; reg aeb,agb,alb; always @(a,b,en) begin if (en==1) if(a==b) begin aeb=1; agb=0; alb=0; end else if(a>b) begin aeb=0; agb=1; alb=0; end else begin aeb=0; agb=0; alb=1; end else begin aeb=0; agb=0; alb=0; end end endmodule

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SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

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Output Waveform:

8. Write a HDL program for 4 bit Binary to Gray conversion and Verify.
Truth Table:

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VHDL Code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binarytogray is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end binarytogray; architecture Behavioral of binarytogray is begin process(b) begin g(3)<=b(3); g(2)<=b(3) xor b(2); g(1)<=b(2) xor b(1); g(0)<=b(1) xor b(0); end process; end Behavioral;

VERILOG Code:
module bintogray(b,g); input [3:0] b; output [3:0] g; reg [3:0] g; always@(b) begin g[3]=b[3]; g[2]=b[3] ^ b[2]; g[1]=b[2] ^ b[1]; g[0]=b[1] ^ b[0]; end endmodule

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SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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9. Write a HDL program for 4 bit Gray to Binary conversion and verify. Truth Table:

VHDL Code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity graytobin is Port ( g : in std_logic_vector(3 downto 0); b : out std_logic_vector(3 downto 0)); end graytobin; architecture Behavioral of graytobin is begin process(g) begin b(3)<=g(3); 29

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b(2)<=g(3) xor g(2); b(1)<=g(3) xor g(2) xor g(1); b(0)<=g(3) xor g(2) xor g(1) xor g(0); end process; end Behavioral;

VERILOG Code:
module gratobin(g,b); input [3:0] g; output [3:0] b; reg [3:0] b; always@(g) begin b[3]=g[3]; b[2]=g[3] ^ g[2]; b[1]=g[3] ^ g[2] ^ g[1]; b[0]=g[3] ^ g[2] ^ g[1] ^ g[0]; end endmodule

SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

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Output Waveform:

10. Design a 8 bit ALU with minimum 8 operations using HDL Truth Table: ENABLE 1 1 1 1 1 1 1 1 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU is Port ( a,b : in std_logic_vector(7 downto 0); opcode : in std_logic_vector(2 downto 0); enable : in std_logic; y : out std_logic_vector(7 downto 0));
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00000101(05h) 00000010(02h)

OPCODE 000 + 001 010 not 011 * 100 AND 101 OR 110 NAND 111 XOR

Y 00000111(07h) 00000011(03h) 11111010(FAh) 00000000(00h) 00000111(07h) 11111111(FFh) 00000111(07h)

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end ALU; architecture Behavioral of ALU is begin process(enable,a,b,opcode) begin if(enable='1')then case opcode is when "000" => y <= a + b; when "001" => y <= a - b; when "010" => y <= not a; when "011" => y <= a * b; when "100" => y <= a and b; when "101" => y <= a or b; when "110" => y <= a nand b; when "111" => y <= a xor b; when others => y <= (others=>'0'); end case; else y <= (others=>'0'); end if; end process; end Behavioral; VERILOG Code: module ALU_v(a,b,opcode,enable,y); input [7:0] a,b; input [3:0] opcode; input enable; output [7:0] y; reg [7:0] y; always@(a,b,enable,opcode) begin if(enable==1'b1) begin case (opcode) 4'b0001 : y = a + b; 4'b0010 : y = a - b; 4'b0011 : y = ~ a; 4'b0100 : y = a * b; 4'b0101 : y = a & b; 4'b0110 : y = a | b; 4'b0111 : y = ~(a & b); 4'b1000 : y = a ^ b;
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default: y=8'd0; endcase end else begin y=8'd0; end end endmodule

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11. Write a HDL code to describe the functions of a Full Adder using three modeling styles. Truth Table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1

i. DATA FLOW DESCRIPTION VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is Port ( a,b,cin : in std_logic; sum,cout : out std_logic); end FullAdder; architecture dtfl of FullAdder is begin sum <= a xor b xor cin; cout <= (a and b) or (b and cin) or (cin and a); end dtfl; VERILOG Code: module FullAdder(a,b,cin,sum,cout); input a,b,cin;
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output sum,cout; assign sum = a ^ b ^ cin ; assign cout = (a & b) | (b & cin) | (cin & a); endmodule ii. BEHAVIORAL DESCRIPTION VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Seq_Full is Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; Sum : out std_logic; Cout : out std_logic); end Seq_Full; architecture Behavioral of Seq_Full is begin process(A,B,Cin) begin if(A='0' and B='0' and Cin='0')then Sum<='0'; Cout<='0'; elsif(A='0' and B='0' and Cin='1')then Sum<='1'; Cout<='0'; elsif(A='0' and B='1' and Cin='0')then Sum<='1'; Cout<='0'; elsif(A='0' and B='1' and Cin='1')then Sum<='0'; Cout<='1'; elsif(A='1' and B='0' and Cin='0')then Sum<='1'; Cout<='0'; elsif(A='1' and B='0' and Cin='1')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='0')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='1')then
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Sum<='1'; Cout<='1'; end if; end process; end Behavioral; VERILOG Code: module fulladd(a,b,cin,sum,cout); input a,b,cin; output sum,cout; reg sum,cout; always@(a,b,cin) begin if(a==1'b0 & b==1'b0 & cin==1'b0) begin sum=1'b0; cout=1'b0; end else if(a==1'b0 & b==1'b0 & cin==1'b1) begin sum=1'b1; cout=1'b0; end else if(a==1'b0 & b==1'b1 & cin==1'b0) begin sum=1'b1; cout=1'b0; end else if(a==1'b0 & b==1'b1 & cin==1'b1) begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b0 & cin==1'b0) begin sum=1'b1; cout=1'b0; end else if(a==1'b1 & b==1'b0 & cin==1'b1) begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b1 & cin==1'b0)
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begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b1 & cin==1'b1) begin sum=1'b1; cout=1'b1; end end endmodule
iii. STRUCTURAL DESCRIPTION

VHDL Code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FA is Port ( a,b,cin : in std_logic; sum,cout : out std_logic); end FA; architecture Behavioral of FA is component HA port (I1, I2 : in std_logic; O1, O2 : out std_logic); end component; component orgate port (I1, I2 : in std_logic; O1 : out std_logic); end component; signal s0,c0,c1:std_logic; begin HA1 : HA port map (a,b,s0,c0); HA2 : HA port map (cin,s0,sum,c1); O1 : orgate port map (c0,c1,cout); end Behavioral; ---------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; 37

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use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( I1 : in std_logic; I2 : in std_logic; O1 : out std_logic; O2 : out std_logic); end HA; architecture Behavioral of HA is begin O1 <= I1 xor I2; O2 <= I1 and I2; end Behavioral; ---------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is port ( I1: in std_logic; I2: in std_logic; O1: out std_logic); end orgate; architecture Behavioral of orgate is begin O1 <= I1 or I2; end Behavioral; ----------------------------------------------------------------

VERILOG Code:
module FA(a,b,cin,sum,cout); input a; input b; input cin; output sum; output cout; HA H1 (a,b,s0,c0); HA H2 (cin,s0,sum,c1); or_gate O1 (c0, c1, cout); endmodule module HA(a,b,s,c); input a,b; output s,c; xor (s,a,b); and (c,a,b); endmodule

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module or_gate(a,b,y); input a; input b; output y; assign y = a | b; endmodule

SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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12. Verify the functionality of D Flip Flop using HDL AIM: To design a D-flip flop in behavioral model and testing the functionality using test bench RESET CLK D Q Qb 1 X X 0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 VHDL Code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity D_ff is Port ( d : in std_logic; reset : in std_logic; clk : in std_logic; q,qb : buffer std_logic); end D_ff; architecture Behavioral of D_ff is begin process(clk,reset) begin if(reset='1')then q <= '0'; elsif(clk'event and clk='1')then q <= d; end if; 40

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end process; qb <= not q; end Behavioral; VERILOG Code: module D_ff(d,clk,reset,q,qb); input d; input clk; input reset; output q; output qb; reg q,qb; always@(posedge clk or posedge reset) begin if(reset==1'b1) begin q<=1'b0; qb<=1'b1; end else begin q<=d; qb<=~d; end end endmodule

SYNTHESIS RESULTS:

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SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

13. Verify the functionality of T Flip Flop using HDL. RESET CLK T Q 1 X X 0 0 1 0 Q(0) 0 0 0 Q(0) not Q(1) 0 1 1 0 0 1 1

Qb 1 1 1 0 0

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use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity T_ff is Port ( clk : in std_logic; reset : in std_logic; t : in std_logic; q : inout std_logic; qb : inout std_logic); end T_ff; architecture Behavioral of T_ff is begin process(clk,reset) begin if reset='1' then q <= '0'; elsif(clk'event and clk='1')then if t='1' then q <= not q ; else q<=q; end if; end if; end process; qb <= not q ; end Behavioral; VERILOG Code: module T_ff(clk,reset,t,q,qb); input clk; input reset; input t; output q; output qb; reg q,qb; always@(posedge clk) begin if (reset==1'b1) begin q=1'b0; qb=1'b1; end else begin if(t==1'b1) q = ~q; else 43

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q = q; end qb=~q; end endmodule

SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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14. Verify the functionality of SR-Flip flop using HDL

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SR_ff is Port ( S : in std_logic; R : in std_logic; clk : in std_logic; reset : in std_logic; q,qb : out std_logic); end SR_ff; architecture Behavioral of SR_ff is begin process (clk,reset) variable temp : std_logic; begin if(reset='1')then temp := '0'; elsif(clk'event and clk='1')then if(S='0' and R='0')then temp := temp ; elsif(S='0' and R='1')then temp := '0' ; elsif(S='1' and R='0')then temp := '1' ; elsif(S='1' and R='1')then temp := 'Z' ; end if; end if; q <= temp; 45

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qb <= not temp; end process; end Behavioral; VERILOG Code: module SR_f_f(SR,clk,reset,q,qb); input [1:0] SR ; input clk,reset; output q,qb; reg q,qb; always@(posedge clk) begin if(reset==1'b1) q = 1'b0; else begin case (SR) 2'b00 : q = q ; 2'b01 : q = 1'd0 ; 2'b10 : q = 1'd1 ; 2'b11 : q = 1'dZ ; endcase end qb = ~ q; end endmodule

SYNTHESIS RESULTS:

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SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

15. Verify the functionality of JK Flip Flop using HDL

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JK_ff is Port ( J : in std_logic; K : in std_logic; 47

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clk : in std_logic; reset: in std_logic; q : buffer std_logic; qb : inout std_logic); end JK_ff; architecture JK_ff_arch of JK_ff is begin process(clk,reset) variable temp:std_logic; begin if(reset='1')then temp := '0'; elsif(clk'event and clk='1')then if(J='0' and K='0')then temp := temp ; elsif(J='0' and K='1')then temp := '0' ; elsif(J='1' and K='0')then temp := '1' ; elsif(J='1' and K='1')then temp := not temp ; end if; end if; q <= temp; qb <= not temp; end process; end JK_ff_arch;

VERILOG Code: module JK_ff(JK,clk,reset,q,qb); input [1:0] JK; input clk; input reset; output q,qb; reg q,qb; always@(posedge clk) begin if (reset==1b1) q = 1'd0 ; else begin case(JK) 2'b00 : q = q ; 2'b01 : q = 1'd0 ; 48

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2'b10 : q = 1'd1 ; 2'b11 : q = ~ q ; endcase end qb = ~q; end endmodule

SYNTHESIS RESULTS:

SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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16. Design 4 bit binary counter (Asynchronous reset and Synchronous reset).
i. ASYNCHRNOUS UP/DOWN BINARY COUNTER VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ASYNC_RST_COUNTER is Port ( clk : in std_logic; reset : in std_logic; qout : inout std_logic_vector(3 downto 0)); end ASYNC_RST_COUNTER; architecture Behavioral of ASYNC_RST_COUNTER is begin process(clk) begin if(reset='1')then qout<="0000"; elsif(clk'event and clk='1')then qout<=qout+1; end if; end process; end Behavioral;

VERILOG Code:
module async_reset_binary(clk,reset,qout); input clk; input reset; output [3:0] qout; reg [3:0] qout; always@(posedge clk or posedge reset) begin if(reset) begin qout=4'b0000; end else begin qout=qout+1; end end endmodule

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SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

ii. SYNCHRONOUS BINARY UP COUNTER VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sync_rst_binary is Port ( clk : in std_logic; reset : in std_logic; qout : inout std_logic_vector(3 downto 0)); end sync_rst_binary; architecture Behavioral of sync_rst_binary is begin 51

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process(clk) begin if(clk'event and clk='1') then if(reset='1')then qout<="0000"; else qout<=qout+1; end if; end if; end process; end Behavioral; VERILOG Code: module SYNC_RESET_BINARY(clk,reset,qout); input clk; input reset; output [3:0] qout; reg [3:0] qout; always@(posedge clk) begin if(reset==1'b1) qout=4'b0000; else qout=qout+1; end endmodule

SIMULATION RESULTS: INPUT Test bench waveform:

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Output Waveform:

17. Design BCD counter (Synchronous reset).

SYNCHRNOUS BCD COUNTER VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BCD_COUNTER is port(Clock: in std_logic; Reset: in std_logic; Output: out std_logic_vector(0 to 3)); end BCD_COUNTER ; architecture Behavioral of BCD_COUNTER is signal COUNT: std_logic_vector(0 to 3); begin process(Clock,Reset) begin if Reset='1' then COUNT <= "0000"; elsif(Clock'event and Clock='1') then if COUNT="1001" then COUNT<="0000"; else COUNT <= COUNT + 1; end if; else COUNT <= COUNT; end if; end process; 53

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Output <= COUNT; end Behavioral; VERILOG Code: module sync_reset_bcd(reset,clk,qout); input reset; input clk; output [3:0] qout; reg [3:0] temp; assign qout=temp; always@(posedge clk) begin if(reset==1'b1) temp=4'b0000; else begin temp=temp+1; if(temp==4'b1001) temp=4'b0000; end end endmodule

SYNTHESIS RESULTS:

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SIMULATION RESULTS: INPUT Test bench waveform:

Output Waveform:

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HARDWARE INTERFACING EXPERIMENTS

18. Write HDL code to implement all Basic gates and verify it on FPGA Kit.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity all_gates is Port ( A,B : in std_logic; y_not : out std_logic; y_or : out std_logic; y_and : out std_logic; y_nor : out std_logic; y_nand : out std_logic; y_xor : out std_logic; y_xnor : out std_logic); end all_gates; architecture Behavioral of all_gates is begin y_not <= not A; y_or <= A or B; y_and <= A and B; y_nor <= A nor B; y_nand <= A nand B; y_xor <= A xor B; y_xnor <= A xnor B; end Behavioral;
UCF file(User constraint)

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19. Write a VHDL code to control external lights using relays.

VHDL CODING library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity extlight is Port ( cntrl1,cntrl2 : in std_logic; light : out std_logic); end extlight; architecture Behavioral of extlight is begin light<= cntrl1 OR cntrl2 ; end Behavioral;

UCF file(User constraint)

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20. Write a VHDL code to control speed, direction of Stepper motor.

VHDL CODING library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity STEPPERnew is Port ( dout : out std_logic_vector(3 downto 0); clk,reset: in std_logic; row:in std_logic_vector(1 downto 0); dir:in std_logic); end STEPPERnew; architecture Behavioral of STEPPERnew is signal clk_div : std_logic_vector(25 downto 0); signal clk_int: std_logic; signal shift_reg : std_logic_vector(3 downto 0); begin process(clk) begin if rising_edge (clk) then clk_div <= clk_div + '1'; end if; end process; clk_int<=clk_div(21) when row="00"else clk_div(19) when row="01"else clk_div(17) when row="10"else clk_div(15) ;

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process(reset,clk_int,dir) begin if reset='0' then shift_reg <= "1001"; elsif rising_edge(clk_int) then if dir='0' then shift_reg <= shift_reg(0) & shift_reg(3 downto 1); else shift_reg<=shift_reg(2 downto 0) & shift_reg(3); end if; end if; end process; dout <= shift_reg; end Behavioral; UCF file(User constraint File)

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21. Write a VHDL code to generate different waveforms using DAC change the frequency and amplitude.
Procedure: 1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board. 4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data.

i.

SINE Waveform

VHDL CODING LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SINE IS PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; dac_out : OUT STD_LOGIC_VECTOR(0 to 7)); END SINE; 60

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ARCHITECTURE BEHAVIORAL OF SINE IS SIGNAL C1:STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL I :INTEGER RANGE 0 TO 179; TYPE SINE IS ARRAY (0 TO 179) OF INTEGER RANGE 0 TO 255; CONSTANT VALUE:SINE:=(128,132,136,141,154,150,154,158,163,167, 171,175,180,184,188,192,195,199,203,206, 210,213,216,220,223,226,228,231,234,236, 238,241,243,244,246,247,248,249,250,251, 252,253,254,255,255, 255,255,255,254,254, 253,252,251,249,246,244,243,241,238,236, 234,231,228,226,223,220,216,213,210,206, 203,199,195,192,188,184,180,175,171,167, 163,158,154,150,145,141,136,132,128, 123, 119, 114, 110, 105, 101, 97, 92,88,84,80, 75,71,67,64,60,56,52,49,45,42, 39,35,32,29,27,24,21,19,17,14, 12, 11, 9, 7,6,4,3,2,1,1, 0,0,0,0, 0, 0, 0,0,1,1, 2, 3,4,6,7,9,11,12,14,17, 19,21,24,27,29,32,35,39,42,45, 49, 52, 56, 60,64,67,71,75,80,84, 88,92,97,101,105,110,114,119,123,128); BEGIN PROCESS(CLK,RST) BEGIN 61

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IF(RST='1') THEN C1<=(OTHERS=>'0'); ELSIF(CLK'EVENT AND CLK='1') THEN C1<=C1+1; END IF; END PROCESS;

PROCESS(C1(3)) BEGIN IF(C1(3)'EVENT AND C1(3)='1')THEN

dac_out<=CONV_STD_LOGIC_VECTOR(VALUE(I),8); I<=I+1; IF(I=179) THEN I<=0; END IF; END IF; END PROCESS; END BEHAVIORAL;

UCF file(User constraint File)

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ii.

Square waveform

Aim: To generate Square wave using DAC change the frequency and amplitude.

Procedure: 1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board.

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4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data.

VHDL CODING LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY square IS PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; dac_out : OUT STD_LOGIC_VECTOR(0 to 7)); END square;

ARCHITECTURE BEHAVIORAL OF square IS SIGNAL C1:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL I :INTEGER RANGE 0 TO 179; TYPE square IS ARRAY (0 TO 179) OF INTEGER RANGE 0 TO 255; CONSTANT VALUE: square:=(255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 64

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255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1') THEN C1<=(OTHERS=>'0'); ELSIF(CLK'EVENT AND CLK='1') THEN C1<=C1+1; END IF; END PROCESS;

PROCESS(C1(3)) BEGIN

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IF(C1(3)'EVENT AND C1(3)='1')THEN

dac_out<=CONV_STD_LOGIC_VECTOR(VALUE(I),8); I<=I+1; IF(I=179) THEN I<=0; END IF; END IF; END PROCESS; END BEHAVIORAL;

UCF file(User constraint File)

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iii.

Triangular waveform

Aim: To generate Triangular wave using DAC change the frequency and amplitude. . Procedure: 1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. 2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. 3. Connect the downloading cable and power supply to the FPGA board. 4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 5. Make the reset switch on (active low) and analyze the data.

VHDL CODING LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Triangular IS PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; dac_out : OUT STD_LOGIC_VECTOR(0 to 7)); END Triangular; 67

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ARCHITECTURE BEHAVIORAL OF Triangular IS SIGNAL C1:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL I :INTEGER RANGE 0 TO 179; TYPE Triangular IS ARRAY (0 TO 1) OF INTEGER RANGE 0 TO 255; CONSTANT VALUE: Triangular:=(255,0); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1') THEN C1<=(OTHERS=>'0'); ELSIF(CLK'EVENT AND CLK='1') THEN C1<=C1+1; END IF; END PROCESS;

PROCESS(C1(3)) BEGIN IF(C1(3)'EVENT AND C1(3)='1')THEN

dac_out<=CONV_STD_LOGIC_VECTOR(VALUE(I),8); I<=I+1; IF(I=179) THEN I<=0; END IF;

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END IF; END PROCESS; END BEHAVIORAL;

UCF file(User constraint File)

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Pin details of interfacing boards

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Pin details of mother boards

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