Dica

Digital IC Applications
KRISHNA MOHAN KANDULA

Associate Professor SVIET NANDAMURU
krishna mohan kandula
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A multiplexer is a digital switchit connects data from one of n sources to its output. The inputs and outputs of an n-input, b-bit multiplexer. There are n sources of data, each of which is b bits wide, and there are b output bits. In typical commercially available multiplexers, n = 1, 2, 4, 8, or 16, and b = 1, 2, or 4. There are s inputs that select among the n sources, so s = log2 n. An enable input EN allows the multiplexer to do its thing; when EN = 0, all of the outputs are 0. A multiplexer is often called a mux for short. Figure (b) shows a switch circuit that is roughly equivalent to the multiplexer. However, unlike a mechanical switch, a multiplexer is a unidirectional device: information flows only from inputs (on the left) to outputs (on the right). We can write a general logic equation for a multiplexer output:
Here, the summation symbol represents a logical sum of product terms. Variable iY is a particular output bit and variable iDj is input bit i of source j Mj represents minterm j of the s select inputs. Thus, when the multiplexer is enabled and the value on the select inputs is j, each output iY equals the corresponding bit of the selected input, iDj.
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Figure Multiplexer structure: (a) inputs and outputs; (b) functional equivalent.
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Figure A multiplexer driving a bus and amohan kandula demultiplexer receiving the bus: krishna (a) switch equivalent; (b) block diagram symbols.
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Table Dataflow VHDL program for a 4-input, 8-bit multiplexer. library IEEE; use IEEE.std_logic_1164.all; entity mux4in8b is port ( S: in STD_LOGIC_VECTOR (1 downto 0); -- Select inputs, 0-3 ==> AD A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -- Data bus input Y: out STD_LOGIC_VECTOR (1 to 8) -- Data bus output ); end mux4in8b; architecture mux4in8b of mux4in8b is begin with S select Y <= A when "00", B when "01", C when "10", D when "11", (others => 'U') when others; -- this creates an 8-bit vector of 'U' end mux4in8b;
Table Behavioral architecture for a 4-input, 8-bit multiplexer.
architecture mux4in8p of mux4in8b is begin process(S, A, B, C, D) begin case S is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when "11" => Y <= D; when others => Y <= (others => 'U'); -- 8-bit vector of 'U' end case; end process; end mux4in8p;
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EXCLUSIVE OR and EXCLUSIVE NOR Gates An Exclusive OR (XOR) gate is a 2-input gate whose output is 1 if exactly one of its inputs is 1. Stated another way, an XOR gate produces a 1 output if its inputs are different. An Exclusive NOR (XNOR) or Equivalence gate is just the oppositeit produces a 1 output if its inputs are the same.
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Figure Multigate designs for the 2-input XOR function: (a) AND-OR; (b) three-level NAND.
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Figure Equivalent symbols for (a) XOR gates; (b) XNOR gates.
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As shown in Figure (a), n XOR gates may be cascaded to form a circuit with n + 1 inputs and a single output. This is called an odd-parity circuit, because its output is 1 if an odd number of its inputs are 1. The circuit in (b) is also an oddparity circuit, but its faster because its gates are arranged in a tree-like structure. If the output of either circuit is inverted, we get an evenparity circuit, whose output is 1 if an even number of its inputs are 1.
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krishna mohan kandula Figure 5-76 Error-correcting circuit for a 7-bit Hamming code.
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Table Behavioral VHDL program for a 9-input parity checker. library IEEE; use IEEE.std_logic_1164.all; entity parity9 is port ( I: in STD_LOGIC_VECTOR (1 to 9); EVEN, ODD: out STD_LOGIC ); end parity9; architecture parity9p of parity9 is begin process (I) variable p : STD_LOGIC; variable j : INTEGER; begin p := I(1); for j in 2 to 9 loop if I(j) = '1' then p := not p; end if; end loop; ODD <= p; EVEN <= not p; end process; krishna mohan kandula end parity9p;
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Tabl e Structural VHDL program for a 74x280-like parity checker. library IEEE; use IEEE.std_logic_1164.all; entity V74x280 is port ( I: in STD_LOGIC_VECTOR (1 to 9); EVEN, ODD: out STD_LOGIC ); end V74x280; architecture V74x280s of V74x280 is component vxor3 port (A, B, C: in STD_LOGIC; Y: out STD_LOGIC); end component; signal Y1, Y2, Y3, Y3N: STD_LOGIC; begin U1: vxor3 port map (I(1), I(2), I(3), Y1); U2: vxor3 port map (I(4), I(5), I(6), Y2); U3: vxor3 port map (I(7), I(8), I(9), Y3); Y3N <= not Y3; U4: vxor3 port map (Y1, Y2, Y3, ODD); U5: vxor3 port map (Y1, Y2, Y3N, EVEN); end V74x280s;
Table Behavioral VHDL program for Hamming error correction. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity hamcorr is port ( DU: IN STD_LOGIC_VECTOR (1 to 7); DC: OUT STD_LOGIC_VECTOR (1 to 7); NOERROR: OUT STD_LOGIC ); end hamcorr; architecture hamcorr of hamcorr is function syndrome (D: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is variable SYN: STD_LOGIC_VECTOR (2 downto 0); begin SYN(0) := D(1) xor D(3) xor D(5) xor D(7); SYN(1) := D(2) xor D(3) xor D(6) xor D(7); SYN(2) := D(4) xor D(5) xor D(6) xor D(7); return(SYN); end syndrome; begin process (DU) variable SYN: STD_LOGIC_VECTOR (2 downto 0); variable i: INTEGER; begin DC <= DU; i := CONV_INTEGER(syndrome(DU)); if i = 0 then NOERROR <= '1'; else NOERROR <= '0'; DC(i) <= not DU(i); end if; end process; krishna mohan kandula end hamcorr;
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Figure General structure of an iterative combinational circuit.
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Figure Traditional logic symbol for the 74x85 4-bit comparator.
Figure A 12-bit comparator using 74x85s.
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Table Behavioral VHDL program for comparing 8-bit unsigned integers. library IEEE; use IEEE.std_logic_1164.all; entity vcompare is port ( A, B: in STD_LOGIC_VECTOR (7 downto 0); EQ, NE, GT, GE, LT, LE: out STD_LOGIC ); end vcompare; architecture vcompare_arch of vcompare is begin process (A, B) begin EQ <= '0'; NE <= '0'; GT <= '0'; GE <= '0'; LT <= '0'; LE <= '0'; if A = B then EQ <= '1'; end if; if A /= B then NE <= '1'; end if; if A > B then GT <= '1'; end if; if A >= B then GE <= '1'; end if; if A < B then LT <= '1'; end if; if A <= B then LE <= '1'; end if; end process; krishna mohan kandula end vcompare_arch
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Table Behavioral VHDL program for comparing 8-bit integers of various types. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity vcompa is port ( A, B: in UNSIGNED (7 downto 0); C: in SIGNED (7 downto 0); D: in STD_LOGIC_VECTOR (7 downto 0); A_LT_B, B_GE_C, A_EQ_C, C_NEG, D_BIG, D_NEG: out STD_LOGIC ); end vcompa; architecture vcompa_arch of vcompa is begin process (A, B, C, D) begin A_LT_B <= '0'; B_GE_C <= '0'; A_EQ_C <= '0'; C_NEG <= '0'; D_BIG <= '0'; D_NEG <= '0'; if A < B then A_LT_B <= '1'; end if; if B >= C then B_GE_C <= '1'; end if; if A = C then A_EQ_C <= '1'; end if; if C < 0 then C_NEG <= '1'; end if; if UNSIGNED(D) > 200 then D_BIG <= '1'; end if; if SIGNED(D) < 0 then D_NEG <= '1'; end if; end process; end vcompa_arch;
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Adders, Subtractors, and ALUs
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Ripple Adders Two binary words, each with n bits, can be added using a ripple addera cascade of n fulladder stages, each of which handles one bit. Figure shows the circuit for a 4-bit ripple adder. The carry input to the least significant bit (c0) is normally set to 0, and the carry output of each full adder is connected to the carry input of the next most significant full adder.
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Subtractors A binary subtraction operation analogous to binary addition was also specified in the Table . A full subtractor handles one bit of the binary subtraction algorithm, having input bits X (minuend), Y (subtrahend), and BIN (borrow in), and output bits D (difference) and BOUT (borrow out). We can write logic equations corresponding to the binary subtraction table as follows:
Alternatively
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Carry Lookahead Adders
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--Table VHDL program for adding and subtracting 8-bit integers of various types. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity vadd is port ( A, B: in UNSIGNED (7 downto 0); C: in SIGNED (7 downto 0); D: in STD_LOGIC_VECTOR (7 downto 0); S: out UNSIGNED (8 downto 0); T: out SIGNED (8 downto 0); U: out SIGNED (7 downto 0); V: out STD_LOGIC_VECTOR (8 downto 0) ); end vadd; architecture vadd_arch of vadd is begin S <= ('0' & A) + ('0' & B); T <= A + C; U <= C + SIGNED(D); V <= C - UNSIGNED(D); krishna mohan kandula end vadd_arch;
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Tabl e Truth table for a 74x151 8-input, 1-bit multiplexer.
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Figure The 74x157 2-input, 4-bit multiplexer: logic diagram, including pin numbers for a standard 16-pin dual krishna mohan kandula in-line package; (b) traditional logic symbol.
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Most approaches to combinational multiplication are based on the paperand- pencil shift-and-add algorithm. Figure below illustrates the basic idea for an 88 multiplier for two unsigned integers, multiplicand X = x7x6x5x4x3x2x1x0 and multiplier Y = y7y6y5y4y3y2y1y0. We call each row a product component, a shifted
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Each small box represents one product-component bit yixj
The product P = p15p14 . .. 2p1p0 has 16 bits and is obtained by adding together all the product components
Partial products in an 8 8 multiplier.
1 2 The carries in each row of full adders are connected to make an 8-bit ripple adder. 3 4 5
6 Overall delay is 20 tPD 7
tPD is delay of one

Full adder 11 12
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1 carry-save addition 2
Overall delay is 14 tPD 4
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PC: array8x8; -- product component bits PCS: array8x8; -- full-adder sum bits PCC: array8x8; -- full-adder carry output bits RAS, RAC;-- ripple adder sum and carry bits
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library IEEE; use IEEE.std_logic_1164.all; entity vmul8x8p is port ( X: in STD_LOGIC_VECTOR (7 downto 0); Y: in STD_LOGIC_VECTOR (7 downto 0); P: out STD_LOGIC_VECTOR (15 downto 0) ); end vmul8x8p; architecture vmul8x8p_arch of vmul8x8p is function MAJ (I1, I2, I3: STD_LOGIC) return STD_LOGIC is begin return ((I1 and I2) or (I1 and I3) or (I2 and I3)); end MAJ; begin process (X, Y)
type array8x8 is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0); variable PC: array8x8; -- product component bits variable PCS: array8x8; -- full-adder sum bits variable PCC: array8x8; -- full-adder carry output bits variable RAS, RAC: STD_LOGIC_VECTOR (7 downto 0); -- ripple adder sum and carry bits
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begin for i in 0 to 7 loop for j in 0 to 7 loop PC(i)(j) := Y(i) and X(j); -- compute product component bits end loop; end loop; for j in 0 to 7 loop PCS(0)(j) := PC(0)(j); -- initialize first-row "virtual" PCC(0)(j) := '0'; -- adders (not shown in figure) end loop; for i in 1 to 7 loop -- do all full adders except last row for j in 0 to 6 loop PCS(i)(j) := PC(i)(j) xor PCS(i-1)(j+1) xor PCC(i-1)(j); PCC(i)(j) := MAJ(PC(i)(j), PCS(i-1)(j+1), PCC(i-1)(j)); PCS(i)(7) := PC(i)(7); -- leftmost "virtual" adder sum output end loop; end loop;
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RAC(0) := '0'; for i in 0 to 6 loop -- final ripple adder RAS(i) := PCS(7)(i+1) xor PCC(7)(i) xor RAC(i); RAC(i+1) := MAJ(PCS(7)(i+1), PCC(7)(i), RAC(i)); end loop; for i in 0 to 7 loop P(i) <= PCS(i)(0); -- first 8 product bits from full-adder sums end loop; for i in 8 to 14 loop P(i) <= RAS(i-8); -- next 7 bits from ripple-adder sums end loop; P(15) <= RAC(7); -- last bit from ripple-adder carry end process; end vmul8x8p_arch;
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Building-Block Design Examples Barrel Shifter A barrel shifter is a combinational logic circuit with n data inputs, n data outputs, and a set of control inputs that specify how to shift the data between input and output. A barrel shifter that is part of a microprocessor CPU can typically specify the direction of shift (left or right), the type of shift (circular , arithmetic, or logical), and the amount of shift (typically 0 to n1 bits, but sometimes 1 to n bits).
UNIT-V L.P-5.1
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S3_L 0 15 14 13 12 11 10 9 S3 8 7 6 5 4 3 2 1
16-bit barrel shifter that does left circular shifts only, using a 4-bit control input S[3:0] to specify the amount of shift. S2S1S0 Are common to both the For example, if the input word is multiplexers. ABCDEFGHGIHKLMNOP S3_L Upper mux will be selected (where each letter represents When s3 lower mux will be one bit), and the selected. control input is 0101 (5), then the output word is FGHGIHKLMNOPABCDE.
S2 S1 S0
S2 S1 S0
0 S0 3 2 1 0 2 1 0 15
1A 2A 3A 4A 1B 2B 3B 4B
S0=0 3 2 1 0
S0=1 2 1 0 15
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity barrel16 is port ( DIN: in STD_LOGIC_VECTOR (15 downto 0); -- Data inputs S: in UNSIGNED (3 downto 0); -- Shift amount, 0-15 C: in STD_LOGIC_VECTOR (2 downto 0); -- Mode control DOUT: out STD_LOGIC_VECTOR (15 downto 0) -- Data bus output ); constant Lrotate: STD_LOGIC_VECTOR := "000"; -- Define the coding of constant Rrotate: STD_LOGIC_VECTOR := "001"; -- the different shift modes constant Llogical: STD_LOGIC_VECTOR := "010"; constant Rlogical: STD_LOGIC_VECTOR := "011"; constant Larith: STD_LOGIC_VECTOR := "100"; constant Rarith: STD_LOGIC_VECTOR := "101"; end barrel16;
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VHDL-93 actually has built-in array operators, rol, ror, sll, srl, sla, and sra, you can use those functions instead of this Vrol function Range of the for loop is dynamic. So some of the synthesis tools does not allow this kind of behavioral modeling. architecture barrel16_behavioral of barrel16 is subtype DATAWORD is STD_LOGIC_VECTOR(15 downto 0); function Vrol (D: DATAWORD; S: UNSIGNED) return DATAWORD is variable N: INTEGER; variable TMPD: DATAWORD; begin N := CONV_INTEGER(S); TMPD := D; for i in 1 to N loop TMPD := TMPD(14 downto 0) & TMPD(15); end loop; return TMPD; end Vrol; ...
No of bits to be rotated.
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begin process(DIN, S, C) begin case C is when Lrotate => DOUT <= Vrol(DIN,S); when Rrotate => DOUT <= Vror(DIN,S); when Llogical => DOUT <= Vsll(DIN,S); when Rlogical => DOUT <= Vsrl(DIN,S); when Larith => DOUT <= Vsla(DIN,S); when Rarith => DOUT <= Vsra(DIN,S); when others => null; end case; end process; end barrel16_behavioral;
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library IEEE; use IEEE.std_logic_1164.all; entity rol16 is port ( DIN: in STD_LOGIC_VECTOR(15 downto 0); -- Data inputs S: in STD_LOGIC_VECTOR (3 downto 0); -- Shift amount, 0-15 DOUT: out STD_LOGIC_VECTOR(15 downto 0) -- Data bus output ); end rol16; architecture rol16_arch of rol16 is begin process(DIN, S) variable X, Y, Z: STD_LOGIC_VECTOR(15 downto 0); begin if S(0)='1' then X := DIN(14 downto 0) & DIN(15); else X := DIN; end if; if S(1)='1' then Y := X(13 downto 0) & X(15 downto 14); else Y := X; end if; if S(2)='1' then Z := Y(11 downto 0) & Y(15 downto 12); else Z := Y; end if; if S(3)='1' then DOUT <= Z(7 downto 0) & Z(15 downto 8); else DOUT <= Z; end if; end process; end rol16_arch;
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library IEEE; use IEEE.std_logic_1164.all; entity rolr16 is port ( DIN: in STD_LOGIC_VECTOR(15 downto 0); -- Data inputs S: in STD_LOGIC_VECTOR (3 downto 0); -- Shift amount, 0-15 DIR: in STD_LOGIC; -- Shift direction, 0=>L, 1=>R DOUT: out STD_LOGIC_VECTOR(15 downto 0) -- Data bus output ); end rolr16;
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architecture rol16r_arch of rolr16 is begin process(DIN, S, DIR) variable X, Y, Z: STD_LOGIC_VECTOR(15 downto 0); variable CTRL0, CTRL1, CTRL2, CTRL3: STD_LOGIC_VECTOR(1 downto 0); begin CTRL0 := S(0) & DIR; CTRL1 := S(1) & DIR; CTRL2 := S(2) & DIR; CTRL3 := S(3) & DIR; case CTRL0 is when "00" | "01" => X := DIN; when "10" => X := DIN(14 downto 0) & DIN(15); when "11" => X := DIN(0) & DIN(15 downto 1); when others => null; end case; case CTRL1 is when "00" | "01" => Y := X; when "10" => Y := X(13 downto 0) & X(15 downto 14); when "11" => Y := X(1 downto 0) & X(15 downto 2); when others => null; end case;
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case CTRL2 is when "00" | "01" => Z := Y; when "10" => Z := Y(11 downto 0) & Y(15 downto 12); when "11" => Z := Y(3 downto 0) & Y(15 downto 4); when others => null; end case; case CTRL3 is when "00" | "01" => DOUT <= Z; when "10" | "11" => DOUT <= Z(7 downto 0) & Z(15 downto 8); when others => null; end case; end process; end rol16r_arch;
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COMPARATORS
UNIT-V L.P-5.2
Design a combinational circuit whose inputs are two 8-bit unsigned binary integers, X and Y, and a control signal MIN/MAX. The output of the circuit is an 8-bit unsigned binary integer Z such that Z = min(X,Y) if MIN/MAX = 1,and Z = max(X,Y) if MIN/MAX = 0. This circuit is fairly easy to visualize in terms of MSI functions. Clearly, we can use a comparator to determine whether X > Y. We can use the comparators output to control multiplexers that produce min(X,Y) and max(X,Y), and we can use another multiplexer to select one of these results depending on MIN/MAX.
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity comp8 is port ( A, B: in STD_LOGIC_VECTOR (7 downto 0); EQ, GT: out STD_LOGIC ); end comp8; architecture comp8_arch of comp8 is begin EQ <= '1' when A = B else '0'; GT <= '1' when A > B else '0'; end comp8_arch;
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architecture comp64s_arch of comp64 is component comp8 port ( A, B: in STD_LOGIC_VECTOR (7 downto 0); EQ, GT: out STD_LOGIC); end component; signal EQ8, GT8: STD_LOGIC_VECTOR (7 downto 0); -- =, > for 8-bit slice signal SEQ, SGT: STD_LOGIC_VECTOR (8 downto 0); -- serial chain of slice results begin SEQ(8) <= '1'; SGT(8) <= '0'; U1: for i in 7 downto 0 generate U2: comp8 port map (A(7+i*8 downto i*8), B(7+i*8 downto i*8), EQ8(i), GT8(i)); SEQ(i) <= SEQ(i+1) and EQ8(i); SGT(i) <= SGT(i+1) or (SEQ(i+1) and GT8(i)); end generate; EQ <= SEQ(0); GT <= SGT(0); end comp64s_arch;
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architecture comp64s_arch of comp64 is component comp8 port ( A, B: in STD_LOGIC_VECTOR (7 downto 0); EQ, GT: out STD_LOGIC); end component; signal EQ8, GT8: STD_LOGIC_VECTOR (7 downto 0); -- =, > for 8-bit slice signal SEQ, SGT: STD_LOGIC_VECTOR (8 downto 0); -- serial chain of slice results begin SEQ(8) <= '1'; SGT(8) <= '0'; U1: for i in 7 downto 0 generate U2: comp8 port map (A(7+i*8 downto i*8), B(7+i*8 downto i*8), EQ8(i), GT8(i)); SEQ(i) <= SEQ(i+1) and EQ8(i); SGT(i) <= SGT(i+1) or (SEQ(i+1) and GT8(i)); end generate; EQ <= SEQ(0); GT <= SGT(0); end comp64s_arch;
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Simple Floating-Point Encoder
UNIT-V L.P-5.3
fixed-point to floating-point encoder. An unsigned binary integer B in the range 0 B < 211 can be represented by 11 bits in fixed-point format, B = b10b9..b1b0. We can represent numbers in the same range with less precision using only 7 bits in a floating-point notation, F = M 2E, where M is a 4-bit mantissa m3m2m1m0 and E is a 3-bit exponent e2e1e0. The smallest integer in this format is 020 and the largest is (24-1) 27.
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11010110100 = 1101 27 + 0110100 00100101111 = 1001 25 + 01111 00000111110 = 1111 22 + 10 00000001011 = 1011 20 + 0 00000000010 = 0010 20 + 0
Given an 11-bit fixed-point integer B, we can convert it to our 7-bit floating-point notation by picking off four highorder bits beginning with the most significant 1, for example, The last term in each equation is a truncation error that results from the loss of precision in the conversion. Corresponding to this conversion operation, we can write the specification for a fixed-point to floating-point encoder circuit:
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A combinational circuit is to convert an 11-bit unsigned binary integer B into a 7-bit floating-point number M,E, where M and E have 4 and 3 bits, respectively. The numbers have the relationship B = M2E + T, where T is the truncation error, 0 T < 2E. Starting with a problem statement like the one above, it takes some creativity to come up with an efficient circuit designthe specification gives no clue. However, we can get some ideas by looking at how we converted numbers by hand earlier. We basically scanned each input number from left to right to find the first position containing a 1, stopping at the b3 position if no 1 was found. We picked off four bits starting at that position to use as the mantissa, and the starting position number determined the exponent. These operations are beginning to sound like MSI building blocks. Scanning for the first 1 is what a generic priority encoder does. The output of the priority encoder is a number that tells us the position of the first 1. The position number determines the exponent; first-1 positions of b10 - b3 imply exponents of 70, and positions of b2 - b0 or no-1-found imply an exponent of 0. Therefore, we can scan for the first 1 with an 8-input priority encoder .
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11010110 100 = 1101 27 + 0110100 00100101111 = 1001 25 + 01111
Active low version of input Priority Encoder
Multiplexer
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity fpenc is port ( B: in STD_LOGIC_VECTOR(10 downto 0); -- fixed-point number M: out STD_LOGIC_VECTOR(3 downto 0); -- floating-point mantissa E: out STD_LOGIC_VECTOR(2 downto 0) -- floating-point exponent ); end fpenc; architecture fpenc_arch of fpenc is begin process(B) variable BU: UNSIGNED(10 downto 0); begin BU := UNSIGNED(B); if BU < 16 then M <= B( 3 downto 0); E <= "000"; elsif BU < 32 then M <= B( 4 downto 1); E <= "001"; elsif BU < 64 then M <= B( 5 downto 2); E <= "010"; elsif BU < 128 then M <= B( 6 downto 3); E <= "011"; elsif BU < 256 then M <= B( 7 downto 4); E <= "100"; elsif BU < 512 then M <= B( 8 downto 5); E <= "101"; elsif BU < 1024 then M <= B( 9 downto 6); E <= "110"; else M <= B(10 downto 7); E <= "111"; end if;end process;end fpenc_arch;
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architecture fpence_arch of fpenc is begin process(B) begin if B(10) = '1' then M <= B(10 downto 7); E <= "111"; elsif B(9) = '1' then M <= B( 9 downto 6); E <= "110"; elsif B(8) = '1' then M <= B( 8 downto 5); E <= "101"; elsif B(7) = '1' then M <= B( 7 downto 4); E <= "100"; elsif B(6) = '1' then M <= B( 6 downto 3); E <= "011"; elsif B(5) = '1' then M <= B( 5 downto 2); E <= "010"; elsif B(4) = '1' then M <= B( 4 downto 1); E <= "001"; else M <= B( 3 downto 0); E <= "000"; end if; end process; end fpence_arch;
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Dual-Priority Encoder
UNIT-V L.P-5.4
It is defined as priority encoder that identifies not only the highest but also the second-highest priority asserted signal among a set of eight request inputs.
The Trick: Use another priority encoder and apply inputs with masking the first highest priority.
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First highest Priority decoder.
Decodes the highest Priority input
Second highest Priority decoder.
Masks the highest Priority .

Propagation time for signal
Propagation time for combinational circuit
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Latches and Flip-Flops

Latches: As a definition they watch inputs continuously and change outputs .
Flip-Flops: As a definition they watch inputs at a clock event and change at that event only.
Latch Flip-Flops
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VHDL structural program for the D latch in library IEEE; use IEEE.std_logic_1164.all; entity Vdlatch is port (D, C: in STD_LOGIC; Q, QN: buffer STD_LOGIC ); end Vdlatch; architecture Vdlatch_s of Vdlatch is signal DN, SN, RN: STD_LOGIC; component inv port (I: in STD_LOGIC; O: out STD_LOGIC ); end component; component nand2b port (I0, I1: in STD_LOGIC; O: buffer STD_LOGIC ); end component; begin U1: inv port map (D,DN); U2: nand2b port map (D,C,SN); U3: nand2b port map (C,DN,RN); U4: nand2b port map (SN,QN,Q); U5: nand2b port map (Q,RN,QN); end Vdlatch_s;
VHDL behavioral architecture for a D latch. architecture Vdlatch_b of Vdlatch is begin process(C, D, Q) begin if (C='1') then Q <= D; end if; QN <= not Q; end process; end Vdlatch_b;
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first generation of sequential PLDs, which used bipolar (TTL) technology. This device has eight primary inputs, eight outputs, and common clock and output-enable inputs, and fits in a 20-pin package.
8 registered outputs
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6 registered outputs
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Dotted line called as macro cell and it can be configurable inependently. 16v8 is superior thanPAL16R8
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Counters The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle. The modulus of a counter is the number of states in the cycle. A counter with m states is called a modulo-m counter or, sometimes, a divide-by-m counter. A counter with a non power of-2 modulus has extra states that are not used in normal operation.
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Ripple Counters An n-bit binary counter can be constructed with just n flip-flops and no other components, for any value of n. Figure shows such a counter for n = 4. Recall that a T flip-flop changes state (toggles) on every rising edge of its clock input. Thus, each bit of the counter toggles if and only if the immediately preceding bit changes from 1 to 0. This corresponds to a normal binary counting sequencewhen a particular bit changes from 1 to 0, it generates a carry to the next most significant bit. The counter is called a ripple counter because the carry information ripples from the less significant bits to the more significant bits, one bit at a time.
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A synchronous counter connects all of its flip-flop clock inputs to the same common CLK signal, so that all of the flip-flop outputs change at the same time, after only tTQ ns of delay. As shown in Figure this requires the use of T flip-flops with enable inputs; the output toggles on the rising edge of T if and only if EN is asserted. Combinational logic on the EN inputs determines which, if any, flip-flops toggle on each rising edge of T.
The counter structure in Figure is sometimes called a synchronous serial counter because the combinational enable signals propagate serially from the least significant to the most significan bits. If the clock period is too short, there may not be enough time for a change in the counters LSB to propagate to the MSB.
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each EN input is driven with a dedicated AND gate with just a single level of logic. Called a synchronous parallel counter This is the fastest binary counter structure.
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--VHDL program for a 74x163-like 4-bit binary counter. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity V74x163 is port ( CLK, CLR_L, LD_L, ENP, ENT: in STD_LOGIC; D: in UNSIGNED (3 downto 0); Q: out UNSIGNED (3 downto 0); RCO: out STD_LOGIC ); end V74x163; architecture V74x163_arch of V74x163 is signal IQ: UNSIGNED (3 downto 0); begin process (CLK, ENT, IQ) begin if (CLK'event and CLK='1') then if CLR_L='0' then IQ <= (others => '0'); elsif LD_L='0' then IQ <= D; elsif (ENT and ENP)='1' then IQ <= IQ + 1; end if; end if; if (IQ=15) and (ENT='1') then RCO <= '1'; else RCO <= '0'; end if; Q <= IQ; end process; end V74x163_arch;
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--VHDL architecture for counting in excess-3 order. architecture V74xs3_arch of V74x163 is signal IQ: UNSIGNED (3 downto 0); begin process (CLK, ENT, IQ) begin if CLK'event and CLK='1' then if CLR_L='0' then IQ <= (others => '0'); elsif LD_L='0' then IQ <= D; elsif (ENT and ENP)='1' and (IQ=12) then IQ <= ('0','0','1','1'); elsif (ENT and ENP)='1' then IQ <= IQ + 1; end if; end if; if (IQ=12) and (ENT='1') then RCO <= '1'; else RCO <= '0'; end if; Q <= IQ; end process; end V74xs3_arch;
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library IEEE; use IEEE.std_logic_1164.all; entity V74x163s is port( CLK, CLR_L, LD_L, ENP, ENT: in STD_LOGIC; D: in STD_LOGIC_VECTOR (7 downto 0); Q: out STD_LOGIC_VECTOR (7 downto 0); RCO: out STD_LOGIC ); end V74x163s;
architecture V74x163s_arch of V74x163s is component syncsercell port( CLK, LDNOCLR, NOCLRORLD, CNTENP, D, CNTEN: in STD_LOGIC; CNTENO, Q: out STD_LOGIC ); end component; signal LDNOCLR, NOCLRORLD: STD_LOGIC; -- common signals signal SCNTEN: STD_LOGIC_VECTOR (8 downto 0); -- serial count-enable inputs begin LDNOCLR <= (not LD_L) and CLR_L; -- create common load and clear controls NOCLRORLD <= LD_L and CLR_L; SCNTEN(0) <= ENT; -- serial count-enable into the first stage RCO <= SCNTEN(8); -- RCO is equivalent to final count-enable output g1: for i in 0 to 7 generate -- generate the eight syncsercell stages U1: syncsercell port map ( CLK, LDNOCLR, NOCLRORLD, ENP, D(i), SCNTEN(i), SCNTEN(i+1), Q(i)); end generate; end V74x163s_arch;
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Shift-Register Structure A shift register is an n-bit register with a provision for shifting its stored data by one bit position at each tick of the clock. Figure 8-46 shows the structure of a serial-in, serial-out shift register. The serial input, SERIN, specifies a new bit to be shifted into one end at each clock tick. This bit appears at the serial output, SEROUT, after n clock ticks, and is lost one tick later. Thus, an n-bit serial-in, serial-out shift register can be used to delay a signal by n clock ticks.
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10.3.5 Synchronous SRAM
A new variety of SRAM, called a synchronous SRAM (SSRAM) (S-S-ram) uses latches internally has a clocked interface for control, address, and data. internal edgetriggered registers AREG and CREG are placed on the signal paths for address and control. As a result, an operation that is set up before the rising edge of the clock is performed internally during a subsequent clock period. Register INREG captures the input data for write operations, and depending on whether the device has pipelined or flow through outputs, register OUTREG is or is not provided to hold the output data from a read operation.The first variety of SSRAM to be introduced was the latewrite SSRAM with flow-through outputs. For a read operationthe control and address inputs are sampled at the rising edge of the clock, and the internal address register AREG is loaded only if ADS_L is asserted. During the next clock period, the internal SRAM array is accessed and read data is delivered to the devices DIO data-bus pins. The device also supports a burst mode, in which data at sequence of addresses is read. In this mode, AREG behaves as a counter, eliminating the need to apply a new address at each cycle.
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krishna mohan Figure Internal structure of akandula synchronous SRAM.
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Figure Timing behavior for a late-write SSRAM with flow-through outputs: (a) read operations; (b) write operations.
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Figure Read-timing behavior for a late-write SSRAM with pipelined outputs.

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Standard SRAM: 6264
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Standard SRAM: 6264
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Dynamic-RAM Structure It is not possible to build a bi-stable element with just one transistor. Instead, the memory cells in a dynamic RAM (DRAM) store information on a tiny capacitor accessed through a MOS transistor. Figure shows the storage cell for one bit of a DRAM, which is accessed by setting the word line to a HIGH voltage. To store a 1, a HIGH voltage is placed on the bit line, which charges the capacitor through the on transistor. To store a 0, LOW voltage on the bit line discharges the capacitor. To read a DRAM cell, the bit line is first pre-charged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. Depending on whether the capacitor voltage is HIGH or LOW, the precharged bit line is pulled slightly higher or slightly lower. A sense amplifier detects this small change and recovers a 1 or 0 accordingly. Note that reading a cell destroys the original requirements, the chip generates an internal CAS signal at a later clock tick. How many ticks later is a function of the CLK frequency and the speed grade of the SDRAM chip itself. To accommodate differing requirements, the RAS-to-CAS delay, called the CAS latency, is programmable. This and several other important operating parameters must be downloaded into an SDRAM at initialization. Downloading is fairly easy; the load parameters command is recognized when RAS_L, CAS_L, and WE_L control signals are all asserted simultaneously, and the parameters themselves are transferred on the address lines.
Dynamic RAM Cell
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KRISHNA MOHAN KANDULA

krishna mohan kandula

krishna mohan kandula

krishna mohan kandula

krishna mohan kandula

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Table Behavioral architecture for a 4-input, 8-bit multiplexer.

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Figure General structure of an iterative combinational circuit.

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Figure Traditional logic symbol for the 74x85 4-bit comparator.

Figure A 12-bit comparator using 74x85s.

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Adders, Subtractors, and ALUs

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Carry Lookahead Adders

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Tabl e Truth table for a 74x151 8-input, 1-bit multiplexer.

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Each small box represents one product-component bit yixj

Partial products in an 8 8 multiplier.

6 Overall delay is 20 tPD 7

tPD is delay of one

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Overall delay is 14 tPD 4

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