22/06/2011

ISSUE no:1

Revision no: 0

U5EEA23 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

Lab Mannual
B.Tech - EEE Semester - 5

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

Prepared by G.ILANGOVAN, M.TECH S.RAMAKRISHNAN, M.E

LIST OF EXPERIMENTS: 1. Study of Basic Digital ICs. Verification of truth table for AND, OR, NOT, NAND, NOR, EXOR, JK FF, RS FF, D FF) 2. Implementation of Boolean Functions, Adder/ Subtractor circuits. 3. Code converters, Parity generator and parity checking, Excess 3, 2s Complement, Binary to gray code using suitable ICs. 4. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs. 5. Multiplexer/ De-multiplexer: Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer 6. Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation. 7. Application of Op-Amp Slew rate verifications, inverting and non-inverting amplifier Adder,

8. Op Amp as comparator, Integrator and Differentiator. 9. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated ICs.

10. Study of VCO and PLL ICs i. Voltage to frequency characteristics of NE/ SE 566 IC. ii. Frequency multiplication using NE/SE 565 PLL IC.

Ex. No.1a

STUDY OF BASIC DIGITAL ICS

AIM: To verify the truth table of basic digital ICsof AND, OR, NOT, NAND, NOR, EX-OR gates and JK flip flop, RS flip flop and D flip flop. THEORY: a. AND gate: An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of 1 only if all the input signals are 1. LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408:

CIRCUIT DIAGRAM:

TRUTH TABLE (AND Gate): S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = A. B 0 0 0 1

b. OR gate: An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of 1 if any of the input signal is 1. LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7432:

CIRCUIT DIAGRAM:

TRUTH TABLE (OR Gate): S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A+B 0 1 1 1

c. NOT gate: A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7404:

CIRCUIT DIAGRAM:

TRUTH TABLE (NOT Gate): S.No 1. 2. d. NAND gate: A NAND gate is a complemented AND gate. The output of the NAND gate will be 0 if all the input signals are 1 and will be 1 if any one of the input signal is 0. LOGIC DIAGRAM: INPUT A 0 1 OUTPUT Y = A 1 0

PIN DIAGRAM OF IC 7400:

CIRCUIT DIARAM:

TRUTH TABLE (NAND Gate):

S.No 1. 2. 3. 4.

INPUT A 0 0 1 1 B 0 1 0 1

OUTPUT Y = (A. B) 1 1 1 0

e. NOR gate: A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if all the inputs are 0 and will be 0 if any one of the input signal is 1.

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7402

CIRCUIT DIAGRAM:

TRUTH TABLE (NOR Gate):

S.No 1. 2. 3. 4.

INPUT A 0 0 1 1 B 0 1 0 1

OUTPUT Y = (A + B) 1 0 0 0

f. EX-OR gate: An Ex-OR gate performs the following Boolean function, A B = ( A . B ) + ( A . B )

It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal 0 when the two input signals are equal either 0 or 1. LOGIC DIAGRAM

PIN DIAGRAM OF IC 7486:

CIRCUIT DIAGRAM:

TRUTH TABLE (EX-OR Gate): S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A B 0 1 1 0

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. To verify the truth table of basic digital Ics APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate Range IC 7408 IC 7432 IC 7404 IC 7400 Quantity 1 1 1 1 1

6. 7. 8.

NOR gate EX-OR gate Connecting wires

IC 7402 IC 7486 As required

1 1

Result: Thus verify the truth table of basic digital Ics of AND, OR, NOT, NAND, NOR, EX-OR gates.

Ex.NO:1b

STUDY OF FLIP FLOPS

AIM: To verify the characteristic table of RS, D, JK, and T Flip flops. THEORY: A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states. RS FLIP FLOP: The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state. LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: CLOCK INPUT PULSE S R 1 0 0 2 0 0 3 0 1 4 0 1 5 1 0 6 1 0 7 1 1 8 1 1 D FLIP FLOP:

PRESENT STATE (Q) NC NC 0 1 0 1 X X -8-

NEXT STATE(Q+1) NC NC 0 0 1 1 X X

STATUS NO CHANGE RESET SET UNDEFINED

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other. LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:

CLOCK PULSE 1 2 3 4

INPUT D 0 0 1 1

PRESENT STATE (Q) 0 1 0 1

NEXT STATE(Q+1) 0 0 1 1

STATUS

JK FLIP FLOP: The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided. LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: CLOCK PULSE 1 2 3 4 5 6 7 8 T FLIP FLOP: This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop. INPUT J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 PRESENT STATE (Q) 0 1 0 1 0 1 0 1 NEXT STATE(Q+1) 0 1 0 0 1 1 1 0 STATUS NO CHANGE SET RESET TOGGLE

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: CLOCK PULSE 1 2 3 4 INPUT T 0 0 1 1 PRESENT STATE (Q) 0 1 0 1 NEXT STATE(Q+1) 0 0 1 0 STATUS

TOGGLE

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit NOR gate NOT gate AND gate ( three input ) NAND gate Connecting wires Range IC 7402 IC 7404 IC 7411 IC 7400 Quantity 1 1 1 1 1 As required

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and observe the status of all the flip flops.

RESULT: The Characteristic tables of RS, D, JK, T flip flops were verified.

QUESTIONS: 1. What are the basic logic gates? 2. What is mean by universal logic gates? 3. How many bits a flip flop can store? 4. What is mean by RS flip flop? 5. What is the different between RS and JK flip flop? 6. What will be the output of D-Flip flop if the input is zero? 7. NAND gate is a combination of _____________________ 8. What is the use of flip-flops? 9. How many OR gate and NOT gate needed for constructing a NOR gate? 10. What is the different between a truth table and a characteristics table? 11. Why are the gates used in manufacturing ICs? 12. Why the digital circuit always represents 1s and 0s?

Ex. No.2a AIM:

IMPLEMENTATION OF BOOLEAN FUNCTIONS

To design the logic circuit and verify the truth table of the given Boolean expression: F (A, B, C, D) = (0, 1, 2, 5, 8, 9, 10) [Design can be changed by changing the Boolean expression] DESIGN: Given , F (A,B,C,D) = (0,1,2,5,8,9,10) The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a simplified expression for the output as shown,

From the K-Map, F = B C + D B + A C D Since we are using only two input logic gates the above expression can be re-written as, F = C (B + A D) + D B Now the logic circuit for the above equation can be drawn. CIRCUIT DIAGRAM:

TRUTH TABLE: S.No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PROCEDURE: 1. Connections are given as per the circuit diagram 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the given Boolean expression. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 Quantity 1 1 1 1 1 1 1 As required INPUT B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 OUTPUT F=DB+C(B+AD) 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

RESULT: The truth table of the given Boolean expression was verified.

Ex. No. 2b AIM:

IMPLEMENTATION OF HALF ADDER & FULL ADDER

To design and verify the truth table of the Half Adder & Full Adder circuits. THEORY: The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely, 0+0=0 0+1=1 1+0=1 1 + 1 = 102 The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. HALF ADDER: A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. FULL ADDER: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate. HALF ADDER TRUTH TABLE(HALF ADDER): S.No 1. 2. 3. 4. DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A B Carry, C = A . B INPUT A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 OUTPUT C 0 0 0 1

CIRCUIT DIAGRAM (HALF ADDER):

FULL ADDER TRUTH TABLE (FULL ADDER): S.No 1. 2. 3. 4. 5. 6. 7. 8. DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, SUM = ABC + ABC + ABC + ABC CARRY = ABC + ABC + ABC +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, SUM INPUT B 0 0 1 1 0 0 1 1 OUTPUT SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

A 0 0 0 0 1 1 1 1

C 0 1 0 1 0 1 0 1

SUM = ABC + ABC + ABC + ABC = A CARRY

CARRY = AB + AC + BC CIRCUIT DIAGRAM (FULL ADDER):

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half adder and full adder circuits. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7486 Quantity 1 1 1 1 1 As required

RESULT: The design of the half adder and full adder circuits was done and their truth tables were verified.

Expt. No. 2c IMPLEMENTATION OF HALF SUBTRACTOR & FULL SUBTRACTOR AIM: To design and verify the truth table of the Half Subtractor& Full Subtractor circuits. THEORY: The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely,

0-0=0 0 - 1 = 1 with 1 borrow 1-0=1 1-1=0 In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed. HALF SUBTRACTOR: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two halfsubtractor and one OR gate. HALF SUBTRACTOR TRUTH TABLE(HALF SUBTRACTOR): S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT DIFF BORR 0 0 1 1 1 0 0 0

DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF = A B Borrow, BORR = A . B

CIRCUIT DIAGRAM (HALF SUBTRACTOR):

FULL SUBTRACTOR TRUTH TABLE (FULL SUBTRACTOR): INPUT A 1. 2. 3. 4. 5. 6. 7. 8. 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT DIFF 0 1 1 0 1 0 0 1 BORR 0 1 1 1 0 0 0 1

S.No

DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF= ABC + ABC + ABC + ABC Borrow, BORR = ABC + ABC + ABC +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as;

DIFFERENCE

DIFF = ABC + ABC + ABC + ABC = A BORROW

BORR = AB + AC + BC CIRCUIT DIAGRAM (FULL SUBTRACTOR) :

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7486 Range Quantity 1 1 1 1 1 As required

RESULT: The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.

Questions: 1. 2. 3. 4. What is meant by half and full adder? What is meant by half and full subtractor? What is meant by Karnaugh map? What are the ICs required for constructing adder and subtractor circuit? 5. How many half adders are there in a full adder? 6. What are the outputs produced at the end of full subtraction? 7. What is mean by SOP and POS? 8. List out the various types of k-maps. 9. What is the maximum possible grouping in a four variable k-map? 10. What are the various laws of Boolean algebra?

Ex. No. 3a AIM:

PARITY GENERATOR & CHECKER

To design and verify the truth table of a three bit Odd Parity generator and checker. THEORY: A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity the added parity bit will make the total number of 1s an even amount and in odd parity the added parity bit will make the total number of 1s an odd amount. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission. Since the information was transmitted with odd parity the four bits received must have an odd number of 1s. An error occurs during the transmission if the four bits received have an even number of 1s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1s. CIRCUIT DIAGRAM: ODD PARITY GENERATOR

ODD PARITY GENERATOR TRUTH TABLE (ODD PARITY GENERATOR):

INPUT S.No ( Three bit message) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1

OUTPUT ( Odd Parity bit) P 1 0 0 1 0 1 1 0

1 2 3 4 5 6 7 8

From the truth table the expression for the output parity bit is, P( A, B, C) = (0, 3, 5, 6) Also written as, P = ABC + ABC + ABC + ABC = (A B C)

CIRCUIT DIAGRAM: ODD PARITY CHECKER

TRUTH TABLE (ODD PARITY CHECKER): INPUT ( four bit message Received ) A B C P 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 OUTPUT (Parity error check) X 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1

S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.

From the truth table the expression for the output parity checker bit is, X (A, B, C, P) = (0, 3, 5, 6, 9, 10, 12, 15) The above expression is reduced as, This X = (A APPARATUS REQUIRED: S.No 1. 2. 3. 4. Name of the Apparatus Digital IC trainer kit EX-OR gate NOT gate Connecting wires Range IC 7486 IC 7404 As required Quantity 1 B C P)

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the Parity generator and checker. RESULT: The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified.

Ex. No. 3b AIM

EXCESS 3, 2S COMPLEMENT CONVERSION

To convert the given binary number in to its twos complement Theory: 2s complement is the binary number that results when we add 1b to the 1s complement of the number. 2s complement = 1s complement + 1b Where 1s complement is obtained by converting all 1s to 0s and all 0s to 1s in the given binary number. 7483 PIN Diagram: B4 4 C4 C0 GND B1 A1 1 16 15 14 13 12 11 10 9

7483
1 A4 3 A3 B3 Circuit Diagram: 2 3 4 5 6 7 8

Vcc 2 B2 A2

Binary input B0 7404

B1 B2 B3

GND 10 8 3 1 11 7 4 16 5 Vcc C0 Vcc GND C4

7483
9 S0 6 S1 2 S2

12 14

15 S3

Truth table: Binary code B2 B1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 2s Complement S2 S1 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0

Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

S3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Apparatus required: 1. Digital IC trainer kit 2. IC 7483, IC 7404 Connecting wires Procedure: 1. Verify the IC number IC for the respective logic gates 2. Connections are made as shown in the circuit diagram 3. Pin 14 is connected to +Vcc and pin 7 to ground 4. Input binary code to B0, B1, B2, and B3 are given at respective pins and 2s Complement outputs S0, S1, S2, S3 are taken for all the 16 combinations of the input. 5. Connect the logic state output from the trainer kit to the input of the logic gate IC. 6. Connect the output from the logic gate IC to the output LED indicator of the trainer kit. 7. Change the different logic states and note down the output. 8. Verify the actual output with the given truth table for the respective logic gates.

Result: Thus the truth table for binary code to twos complement converter is verified.

Ex. No. 3c AIM:

BINARY TO GRAY CODE CONVERTER

To design and verify the truth table of a three bit binary to gray code converter.

THEORY: Code converter is a circuit that makes two systems compatible even though each uses different binary codes. There is a wide variety of binary codes used in digital systems. Some of these codes are Binary Coded Decimal, Gray code, Excess- 3 code , ASCII code, etc. A combinational circuit performs the transformation of a three bit binary to gray code converter by means of logic gates. The input variables are binary bits named as A,B,C with A as the MSB and C as the LSB. The Gray code output bits are termed as X,Y,Z with X as the MSB and Z as the LSB. The Gray code is also called as reflective code. The gray coded number corresponding to the decimal number 2n 1, for any n, differs from gray coded 0 (0000) in one bit position only. DESIGN: TRUTH TABLE (3 BIT BINARY TO GRAY CODE CONVERTER): S.No 1. 2. 3. 4. 5. 6. 7. 8. INPUT - BINARY A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 OUTPUT-GRAY X Y Z 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0

From the truth table the expression for the output gray bits are, X (A, B, C) = (4, 5, 6, 7) Y (A, B, C) = (2, 3, 4, 5) Z (A, B, C) = (1, 2, 5, 6) Hence obtain the reduced SOP expression using Karnaugh maps as follows,

For X:

X=A For Y:

Y=A For Z:

Z=B

CIRCUIT DIAGRAM (3 BIT BINARY TO GRAY CODE CONVERTER):

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the three bit binary to gray code converter. APPARATUS REQUIRED: S.No 1. 2. 3. Name of the Apparatus Digital IC trainer kit EX-OR gate Connecting wires Range IC 7486 As required Quantity 1

RESULT: The design of the three bit Binary to Gray code converter circuit was done and its truth table was verified.

Questions:
1. What is mean by parity generator? 2. What are the types of parity and where those are used? 3. What are types of binary codes used in digital system? 4. What is the use of parity checker? 5. What is mean by 1s and 2s complement? 6. What is the difference between binary and BCD code? 7. What are the advantages of code converter? 8. Why gray code is called as reflective code? 9. What is the use of k-map? 10. Give some applications for code converters.

Ex. No. 4

IMPLEMENTATION OF SHIFT REGISTERS

AIM: To design and implement 4 bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs. THEORY: A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next. The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register. PIN DIAGRAM OF IC 7474:

CIRCUIT DIAGRAM:

TRUTH TABLE: For a serial data input of 1101, S.NO 1 2 3 4 5 6 7 8 CLOCK PULSE 1 2 3 4 5 6 7 8 INPUTS D2 D3 X 1 1 0 1 X X X X X 1 1 0 1 X X OUTPUTS Q2 Q3 X 1 1 0 1 X X X X X 1 1 0 1 X X

D1 1 1 0 1 X X X X

D4 X X X 1 1 0 1 X

Q1 1 1 0 1 X 1 0 X

Q4 X X X 1 1 0 1 X

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter APPARATUS REQUIRED: S.No 1. 2. 3. Name of the Apparatus Digital IC trainer kit D Flip Flop Connecting wires Range IC 7474 Quantity 1 2 As required

RESULT: The truth table of a serial in serial out left shift register was hence verified. QUESTION PAPER 1. What is a shift register? 2. List out the various types of shift register. 3. What is meant by serial input and serial output? 4. FIFO can also called as------------------5. LIFO is possible only in ------------------------shift register 6. What is the use of clock pulse in shift register? 7. What is a register? 8. How many flip flops can be used in an 8 bit shift registers? 9. What is mean by a universal shift register? 10. Mention some of the uses of shift register.

Expt. No. 5 AIM:

MULTIPLEXER & DEMULTIPLEXER

To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer. THEORY: Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is many into one and it provides the digital equivalent of an analog selector switch. A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines. 4 X 1 MULTIPLEXER LOGIC SYMBOL:

TRUTH TABLE (4 X 1 MULTIPLEXER): S.No 1. 2. 3. 4. SELECTION INPUT S1 0 0 1 1 S2 0 1 0 1 OUTPUT Y I0 I1 I2 I3

PIN DIAGRAM OF IC 7411:

CIRCUIT DIAGRAM:

7408 7432 7408

7432

7408 7432

7408

1X4 DEMULTIPLEXER LOGIC SYMBOL:

TRUTH TABLE (1X4 DEMULTIPLEXER):

INPUT S.No S1 1. 2. 3. 4. 5. 6. 7. 8. 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 Din 0 1 0 1 0 1 0 1 Y0 0 1 0 0 0 0 0 0

OUTPUT Y1 0 0 0 1 0 0 0 0 Y2 0 0 0 0 0 1 0 0 Y3 0 0 0 0 0 0 0 1

CIRCUIT DIAGRAM:

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the multiplexer &Demultiplexer.

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. Name of the Apparatus Digital IC trainer kit OR gate NOT gate AND gate ( three input ) Connecting wires Range IC 7432 IC 7404 IC 7411 Quantity 1 1 1 1 As required

RESULT: The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were verified.

QUESTIONS: 1. Why multiplexer is also called as data selector? 2. How many select lines are needed for 4:1 multiplexer? 3. What is mean by de-multiplexer? 4. How many outputs will be produced for 4 inputs in a de-multiplexer? 5. Why de-multiplexer is also called as decoder? 6. What are the applications of mux and demux? 7. What is mean by active high signal and active low signal? 8. What is the different between an encoder and a multiplexer? 9. When the output will be high in a de-multiplexer? 10. What are the various combinations of multiplexer and de-multiplexer?

Ex. No.6a STUDY OF NE555 TIMER IN ASTABLE MULTIVIBRATOR AIM: Todesign an astable multivibrator circuit for the given specifications using 555 Timer IC. THEORY: An astable multivibrator, often called a free-running multivibrator, is a rectangularwave-generating circuit. This circuit does not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by, tc = 0.69 (R1 + R2) C Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by, td = 0.69 (R2) C Thus the total time period of the output waveform is, T = tc + td = 0.69 (R1 + 2 R2) C The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed in percentage. In equation form, % duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100 PIN DIAGRAM:

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

DESIGN: Given f= 4 KHz, Therefore, Total time period, T = 1/f = ____________ We know, duty cycle = tc/ T Therefore, tc = -----------------------and td = ____________ We also know for an astable multivibrator td = 0.69 (R2) C Therefore, R2 = _____________ tc = 0.69 (R1 + R2) C Therefore, R1 = _____________ PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + 5V supply is given to the + Vcc terminal of the timer IC. 3. At pin 3 the output waveform is observed with the help of a CRO 4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage waveforms are plotted in a graph sheet. OBSERVATIONS: Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) tc 1. Output Voltage , Vo td

S.No

Waveforms

2.

Capacitor voltage , Vc

APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 555 Quantity 1 1 1 1 1 As required As required As required

RESULT: The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained.

Ex. No.6b

STUDY OF NE555 TIMER IN MULTIVIBRATOR MONOSTABLE OPERATION

AIM: Todesign a monostable multivibrator for the given specifications using 555 timer IC. THEORY: A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an external trigger pulse is applied, the output is forced to go high (approx. Vcc). The time during which the output remains high is given by, tp = 1.1 R1 C At the end of the timing interval, the output automatically reverts back to its logic low state. The output stays low until a trigger pulse is applied again. Then the cycle repeats. Thus the monostable state has only one stable state hence the name monostable.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

DESIGN: Given tp = 0.616 ms = 1.1 R1 C Therefore, R1 = _____________ PROCEDURE: 1. 2. 3. 4. 5. Connections are given as per the circuit diagram. + 5V supply is given to the + Vcc terminal of the timer IC. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC At pin 3 the output waveform is observed with the help of a CRO At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage waveforms are plotted in a graph sheet.

OBSERVATIONS: Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) ton toff

S.No

Observation

1.

Trigger input

2.

Output Voltage , Vo

3.

Capacitor voltage , Vc

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes Range 3 MHz, Analog 30 MHz 0 30 V IC 555 Quantity 1 1 1 1 1 As required As required As required

RESULT: The design of the Monostable multivibrator circuit was done and the input and output waveforms were obtained.

Questions: 1. 2. 3. 4. 5. 6. What is meant by astable multivibrator? In an astable multivibrator what type of wave form is generated? What is meant by duty cycle? What is meant by monostable multivibrator? Monostable multivibrator is also called as------------? Explain the differences between oscillations obtained from 555 and digital IC. 7. What is meant by a trigger? 8. How many stable states can be achieved in a monostable multivibrator? 9. What are the applications of multivibrator? 10.List out the applications of 555 timer IC.

Ex. No.7a

INVERTING AMPLIFIER

AIM To design an Inverting Amplifier for the given specifications using Op-Amp IC 741. THEORY: The input signal Vi is applied to the inverting input terminal through R1 and the noninverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to the inverting input terminal through the Rf - R1 network, where Rf is the feedback resistor. The output voltage is given as, Vo = - ACL Vi Here the negative sign indicates that the output voltage is 1800 out of phase with the input signal. PRECAUTIONS: Output voltage will be saturated if it exceeds 15V. PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the OpAmp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. PIN DIAGRAM:

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

DESIGN: We know for an inverting Amplifier ACL = RF / R1 Assume R1 (approx. 10 K) and find Rf Hence Vo(theoretical) = - ACL Vi OBSERVATIONS: S.No. Amplitude ( No. of div x Volts per div ) Input Output Theoretical Practical -

Time period ( No. of div x Time per div )

APPARATUS REQUIRED: S.No Name of the Apparatus 1. Function Generator 2. CRO 3. Dual RPS 4. Op-Amp 5. Bread Board 6. Resistors 7. Connecting wires and probes

Range 3 MHz 30 MHz 0 30 V IC 741

Quantity 1 1 1 1 1 As required As required

RESULT: The design and testing of the inverting amplifier is done and the input and output waveforms were drawn

Ex. No.7b

NON - INVERTING AMPLIFIER

AIM: To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741. THEORY: The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies the signal without inverting the input signal. It is also called negative feedback system since the output is feedback to the inverting input terminals. The differential voltage Vd at the inverting input terminal of the op-amp is zero ideally and the output voltage is given as,Vo = ACL Vi . Here the output voltage is in phase with the input signal. PRECAUTIONS: Output voltage will be saturated if it exceeds 15V. PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. PIN DIAGRAM:

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN: We know for a Non-inverting Amplifier ACL = 1 + (RF / R1) Assume R1 ( approx. 10 K ) and find Rf Hence Vo = ACL Vi OBSERVATIONS: S.No. Amplitude Time period ( No. of div x Volts per div ) ( No. of div x Time per div )

Input Output Theoretical Practical -

APPARATUS REQUIRED: S.No Name of the Apparatus 1. Function Generator 2. CRO 3. Dual RPS 4. Op-Amp 5. Bread Board 6. Resistors 7. Connecting wires and probes

Range 3 MHz 30 MHz (0 30) V IC 741

Quantity 1 1 1 1 1 As required As required

RESULT: The design and testing of the Non-inverting amplifier is done and the input and output waveforms were drawn.

Questions:
1. What is mean by amplifier? 2. What is mean by inverting amplifier? 3. What is mean by Non - inverting amplifier? 4. What is mean by op amp? 5. Where this inverter and non-inverter amplifier used? 6. Mention the various applications of an op-amp. 7. What is mean by feedback resistance? 8. What is the use of function generator? 9. Mention the voltage rating of an op-amp. 10. What is mean by offset voltage?

Expt. No.8a

INTEGRATOR

Obtain the output of an Integrator circuit with component values R1Cf = 0.1ms, Rf = 10 R1 and Cf = 0.01 F , if 2 V peak to peak square wave at 1000Hz is applied as input. AIM: To design an Integrator circuit for the given specifications using Op-Amp IC 741. THEORY: A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given as, Vo = - (1/Rf C1) Vi dt Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf. That is, T Rf Cf The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits. PIN DIAGRAM:

CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN: We know the frequency at which the gain is 0 dB, fb = 1 / (2 R1 Cf) Therefore fb = _____ Since fb = 10 fa, and also the gain limiting frequency fa = 1 / (2 Rf Cf) We get, Rf = _______ and hence R1 = __________ PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the OpAmp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. OBSERVATIONS: S.No. Amplitude ( No. of div x Volts per div ) Input Output APPARATUS REQUIRED: S.No Name of the Apparatus 1. Function Generator 2. CRO 3. Dual RPS 4. Op-Amp 5. Bread Board 6. Resistors 7. Capacitors 8. Connecting wires and probes

Time period ( No. of div x Time per div )

Range 3 MHz 30 MHz 0 30 V IC 741

Quantity 1 1 1 1 1 As required As required As required

RESULT: The design of the Integrator circuit was done and the input and output waveforms were obtained.

Expt. No.8b

DIFFERENTIATOR

AIM: To design a Differentiator circuit for the given specifications using Op-Amp IC 741. THEORY: The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R 1 is replaced by a capacitor C1. The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt) Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps: 1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of C1 < 1 F, calculate the value of Rf. 2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf. The differentiator is most commonly used in waveshaping circuits to detect high frequency components in an input signal and also as a rateofchange detector in FM modulators. PIN DIAGRAM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DESIGN: Given fa = --------------We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf C1) Let us assume C1 = 0.1 F; then Rf = _________ Since fb = 20 fa, fb = --------------We know that the gain limiting frequency fb = 1 / (2 R1 C1) Hence R1 = _________ Also since R1C1 = Rf Cf ; Cf = _________ PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the OpAmp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

OBSERVATIONS: Input - Sine wave S.No. Amplitude ( No. of div x Volts per div ) Input Output Input Square wave S.No. Amplitude ( No. of div x Volts per div ) Input Output APPARATUS REQUIRED: S.No Name of the Apparatus 1. Function Generator CRO 2. Dual RPS 3. Op-Amp 4. Bread Board 5. Resistors 6. Capacitors 7. 8. Connecting wires and probes

Time period ( No. of div x Time per div )

Time period ( No. of div x Time per div )

Range 3 MHz 30 MHz 0 30 V IC 741

Quantity 1 1 1 1 1 As required As required As required

RESULT: The design of the Differentiator circuit was done and the input and output waveforms were obtained.

Questions: 1. What is mean by integrator? 2. Where the integrator circuit is used? 3. What is mean by differentiator? 4. Where the differentiator circuit is used? 5. What is the difference between integrator and differentiator? 6. What are the applications of differentiator and integrator? 7. Give the mathematical expiration for differentiation and integration. 8. What is the use of feedback resistance and capacitance? 9. Define delay time? 10. What are the various types of wave forms obtained for integrator and differentiator?

Ex. No.9

STUDY OF ANALOG TO DIGITAL CONVERTER AND DIGITAL TO ANALOG CONVERTER

AIM To verify A/D conversion and D/A conversion using dedicated ICs THEORY: An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device which converts a continuous quantity to a discrete timedigital representation. An ADC may also provide an isolated measurement. The reverse operation is performed by a digital-to-analog converter(DAC). Typically, an ADC is an electronicdevice that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current. However, some non-electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs. A digital-to-analog converter (DAC or D-to-A) is a device that converts a digital (usually binary) code to an analog signal (current, voltage, or electric charge). An analog-to-digital converter (ADC) performs the reverse operation.

DIGITAL TO ANALOG CONVERTER Circuit Diagram: Digital to analog diagram

NC GND

MSB A1 A2 A3 A4

1 16 2 15 3 14 4 13 5 12 6 11 7 10 8

COMPENSATION

DAC0808
AB LSB A7 A6 A4

Circuit Diagram Analog to digital converter

CLOCK INPUT

OE

ALE

ANALOG INPUT

12 22 EOC 10 21 SC 7 20 IN0 6 19 IN1 26 18

CLK IN2 IN3 IN4 IN5 IN6 IN7

11

D0 D1 D2 D3

LED1 LED2 LED3 LED4

A1 A2 A3 A4

MSB

D4

LED5 LED6 LED7

A5 A6 A7

27 8 28 15 1 14 2 3 17 4 5 16 25 13

ADC 0808

D5 D6

D7

LED8

A8

LSB

24

23

GND

Procedure: 1. 2. 3. 4. Connections are made as per the circuit diagram. Input analog voltage is applied to pin 6. The corresponding digital output is noted in the LED sequence. Input voltage is varied and the corresponding digital output is noted in the LED sequence the bit batten is.

Tabular Column: OUTPUT BIT PATTERN S.NO I/P VOLTAGE A1 (MSB) A2 A3 A4 A5 A6 A7 A8 (LSB)

+5V

13 A1 5 14 A2 6 7 A3 15 8 A4 2 A5 9 10 A6 4 11 A7 12 16 A8 1 5K 10 V

5K DAC0808 5K 2 741 4 3 3 0.1 7 +15 14 -15 Output

DESIGN: Output Voltage VO=Vref=(A1/2+A2/4+A3/8+A4/16++A5/32+A6/64+A7/128+A8/256) PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Output from pin 4 is current signal and it is converted to proportional voltage by IC 741 op-amp. 3. Output voltage is measured using a voltmeter. 4. Output voltage for different input bit pattern is measured and tabulated. Tabular column: S.NO A1 (MSB) A2 A3 Input Bit Pattern A4 A5 A6 A7 A8 (LSB) Output Voltage

Components required: 1. Analog ice trainer kit. 2. ADC 0808 3. DAC 0808 4. 741 op amp 5. Resistors 6. Capacitors. 7. Voltmeter (0-30v) 8. Connecting wires. RESULT: Thus the A/D conversion and D/A conversion using dedicated ICs is studied and verified.

QUESTIONS: 1. What is mean by ADC? 2. Why flash type ADC is mostly used? 3. What are the various types of inputs given to ADC? 4. Why op-amp is used in ADC? 5. What is the advantage of ADC? 6. What is mean by DAC? 7. What are the various other methods of DAC? 8. What are the input sources given to a DAC? 9. What is mean by reference voltage? 10. Mention some of the applications of DAC?

Ex.No.10 AIM:

STUDY OF VCO AND PLL ICS

To study voltage to frequency conversion characteristics of NE566 VCO IC and frequency multiplication characteristics of NE565 PLL IC. CIRCUIT DIAGRAM VOLTAGE FREQUENCY CONVERSION CHARACTERISTICS OF NE566 IC
+6V

1K 1K

6
0.1

8
Triangular Wave Output

4 NE 566 VCO IC

3
1K

Square Wave Output

7 1 CR0 O
0.1

DESIGN: fo=2(Vcc-Vm)/(Vcc X Rt X Ct) fo-output oscillation frequency Vcc-supply voltage Vm-modulating input voltage PROCEDURE 1. connections are made as per the circuit diagram 2. square wave output from pin 3 is observed in the CRO

3. modulating input voltage is varied and corresponding output frequency is measured and tabulated OBSERVATION Vcc=+5V S.NO Vm (VOLTS) fo(Hz)

CIRCUIT DIAGRAM FREQUENCY MULTIPLICATION CHARACTERISTICS OF NE565 IC

+6V

20 K

2K

0.001

8 10 7 2 NE565 PLL VCO Output IC4 FG 3 5 9

0.01 F

- 6V4.7 K 10 K

11 5 7490 2 3 10 1 6 7
2N2222

CR O

DESIGN
Fo=Nfs Fo-output oscillation frequency Fs-input frequencyN-dividend of the divide by counter

PROCEDURE 1. 2. 3. 4. connections are made as per the circuit diagram square wave input given to pin 2 output taken from pin 4 is observed in the CRO input frequency is varied and corresponding output frequency is measured and tabulated

OBSERVATION N=5 S.NO fs(Hz) fo(Hz)

APPARATUS REQUIRED 1. 2. 3. 4. 5. 6. 7. 8. 9. Analog IC trainer kit NE566 VCO IC NE 565 PLL IC Resistors Capacitors Voltmeter Function generator CRO Connecting wires

RESULT Thus the voltage to frequency conversion and phase locked loop is studied.

QUESTIONS: 1. What is mean by an oscillator? 2. What is mean by VCO? 3. Mention the applications of VCO. 4. What are characteristics of VCO? 5. What is mean by voltage multiplexer? 6. What is mean by PLL? 7. What are the various blocks of PLL? 8. What is mean by frequency multiplexing? 9. What are the ICs used for constructing a PLL? 10. What is mean by filter and mention the various types of filters?