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GEZGN
Space-proven on BiLSAT LEO Satellite, successfull in-orbit Launched in Sept 2003, to a sun-synchronous, 686km orbit 31 x 33 x 6cm size, 2 kg mass JPEG2000 Implementation similiar to the CCSDS 122.0-R-2 Draft for Image Compression in Space
Original Image (BiLSAT-1, 26m GSD) 16MB Image Compressed by GEZGiN 0.838% (120 times) 140KB
GEZGN-2
Space-qualified for RASAT LEO Satellite To be launched in 2010, to a sun-synchronous, 700km orbit 16 x 33 x 6cm size, 1kg mass JPEG2000 Implementation with novel techniques for fine adjustment of compression rate Full ASIC implementation Rate-Distortion Optimization adopted for non-iterative on-board processing RONI extraction for detecting and decreasing the budget of cloudy regions AES Encryption cascaded with compression
Cloud Elimination
GEZGiN-2A
GEZGN2-A has been qualified for 700km LEO mission in 2011 and is expected to be in orbit by the end of 2012 16 x 33 x 6cm size, 1kg mass JPEG2000 Implementation with novel techniques for fine adjustment of compression rate Double JPEG Engine for high pixel rates Full ASIC implementation Rate-Distortion Optimization adopted for non-iterative on-board processing RONI extraction for detecting and decreasing the budget of cloudy regions AES Encryption cascaded with compression
GEZGN
I/P Features 4 MSI Inputs @ 80Mbps
GEZGN-2
3 MSI+PAN Inputs @ 55Mbps
GEZGN-2A
4 MSI +PAN Inputs off-line @ 100 Mbps Real-time @ 500-600 Mbps LVDS @ 25Mbps, Spacewire @ 100Mbps LOSSLESS & LOSSY @ 45-55Mpixel/sec 11-bit/pixel
O/P Features
COARSE FINE FINE Quantization, Rate-Distortion Optimization & Rate-Distortion Optimization & SubbandOmissionColour RONI extraction RONI extraction Transform Divided between Xilinx 2 JPEG2000 engines Fully Integrated on Xilinx VirtexE300 FPGA @ 80MHz Integrated on Xilinx Virtex-5 LX330 Virtex-2 2M gate FPGA @ 110MHz and TMS320C6701 DSP @ 100MHz FPGA @ 250MHz Redundancy, TMR, Latch-up protection, Reconfiguration & Software upload in Orbit, Graceful Degradation 2 kg RSA and AES encryption ASICs on a daughterboard Redundancy, Latch-up protection, Reconfiguration & Software upload in Orbit 1 kg AES encryption embedded in Xilinx FPGA Redundancy, Latch-up protection, Configuration scrubbing 1 kg
Other Features
Fail-safe operation
Mass
Power Consumption
8 Watts @ 28V
6 Watts @ 28V
15 Watts @ 28V
TBTAK UZAY
06531 ODT Yerlekesi ANKARA TRKYE T +90 312 210 1050 +90 312 210 1310 www.uzay.tubitak.gov.tr F +90 312 210 1315 bilgi@uzay.tubitak.gov.tr