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An SVM Algorithm to Balance the Capacitor Voltages of the Three-Level NPC Active Power Filter
Huibin Zhang, Stephen Jon Finney, Ahmed Massoud, and Barry Wayne Williams
AbstractA requirement of the three-level neutral-pointclamped voltage source inverter, with or without a separately supporting dc link, is to maintain the balance of the two dc-link capacitor voltages. In this paper, balancing of the capacitor voltages for these two dc-link voltage source possibilities is analyzed and an algorithm is proposed to independently balance the capacitor voltages. The algorithm considers the average energy effect of each vector on capacitor voltage and the necessary optimal vector state sequence in each modulation cycle. The algorithm minimizes the voltage rating overheads of the hardware, reduces the voltage ripple, and attenuates the negative effects associated with dc-link voltage oscillations. Index TermsCapacitor voltage ripple, neutral point diodeclamped (NPC), space vector modulation.

I. INTRODUCTION

HE THREE-LEVEL neutral-point diode-clamped (NPC) voltage source inverter (VSI) [1] is a common structure in medium- and high-power industrial applications. It avoids the complexity associated with the series connection of semiconductor switches or the bulky coupling transformer, impresses a lower voltage stress on semiconductor switches thus increasing the power handling capability, and produces lower current/voltage harmonics thus reducing communications interference. One three-level NPC inverter requirement is to balance the voltages of the two series-connected capacitors across the dc rail. The three-level NPC VSI structure shown in Fig. 1, without an external dc supply, has a oating neutral point (NP). Capacitor voltage balancing has been extensively researched [2][4] and traditional modulation techniques produce low-frequency voltage oscillations at the NP [5], [6]. This voltage oscillation causes adverse effects, such as low-frequency harmonics in the output line-to-line voltages, and the bridge devices and capacitors must withstand higher varying voltage stresses. Methods to eliminate the voltage ripple have been proposed both with space vector modulation (SVM) [7] and sinusoidal pulsewidth modulation [8]. When the three-level NPC VSI is used as an active power lter (APF) to improve the power quality at the point of common coupling, as shown in Fig. 1, the dc-link capacitors are independent. A correctly controlled APF can reduce harmon-

Fig. 1.

Three-level NPC active power lter.

Manuscript received March 31, 2008; revised June 2, 2008; accepted July 14, 2008. Current version published December 9, 2008. Recommended for publication by Associate Editor A. Rufer. The authors are with the Department of Electronics and Electrical Engineering, University of Strathclyde, Glasgow G1 1XW, U.K. (e-mail: ahmed. massoud@eee.strath.ac.uk). Digital Object Identier 10.1109/TPEL.2008.2002820

ics, compensate reactive power, and balance the ac source currents. Control of the independent dc-link capacitors in multilevel APF inverters has been extensively researched [9][16], and capacitor sizing due to the transient load changes has also been considered. Capacitor voltage balance is almost achieved in [13], but with voltage ripple that is out of phase. This accentuates the imbalance, and becomes more serious when the instantaneous power difference between the supply and the load is more signicant. Voltage balancing effects from the viewpoint of each SVM functional vector type in each modulation cycle has not been fully quantied for the NPC inverter. An SVM algorithm for balancing the independent dc-link capacitor voltages of the NPC three-level APF inverter is proposed. The algorithm considers the average energy effect of each functional vector and the optimal vector sequence involved in each modulation cycle in order to optimize capacitor balancing. The aim is to make the two capacitor voltages track each other. Because the APF capacitors reect the energy difference between the ac source and the load, capacitor voltage ripple is an inherent phenomenon. Thus, capacitor voltage ripple cannot be eliminated using only modulation techniques. However, in conjunction with an accurate voltage balancing technique, the capacitor voltage ripple can be reduced, thereby attenuating voltage oscillation adverse effects.

0885-8993/$25.00 2008 IEEE

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Fig. 3. Fig. 2. Space vector diagram for three-level SVM.

First sextant of three-level SVM.

II. SPACE VECTOR MODULATION The nearest inverter state vectors to the rotating reference vector [17] are preferred with space vector modulation. The proposed algorithm uses symmetrical modulation rather than three-nearest-vector modulation because when the modulation index is less than unity, capacitor voltages can be more accurately controlled [6]. Capacitor balancing techniques differ when the three-level NPC structure is used in an APF mode and in a VSI mode with a dc-link source voltage. With a dc-link voltage source, the sum of two capacitor voltages is a constraint to the dc-link voltage. Without a dc-link voltage supply, when current ows into the NP, the capacitor voltage summation is not constrained by any dc voltage source and the charging/discharging of the two capacitors is determined by the specic circuit conditions, as will be shown. The space vector diagram for a three-level SVM is shown in Fig. 2. There are: r six long vectors (200, 220, 020, 022, 002, and 202); r six medium vectors (210, 120, 021, 012, 102, and 201); r twelve short vectors (100-211, 110-221, 010-121, 011-122, 001-112, and 101-212); and r three zero vectors (222, 111, 000). To balance the capacitor voltages, each vector and its effect on the dc-link capacitor voltages need to be analyzed. When there is an external dc supply on the dc link, the zero-average NP current in each SVM modulation cycle ensures the balancing of the capacitor voltages, thereby eliminating any voltage ripple [8]. Long vectors and zero vectors do not affect voltage balance because no NP current ows. Medium vectors are uncontrolled vectors that cause voltage imbalance and the redundant short vectors are utilized to balance the capacitor voltages. However, when there is no external dc-link supply, as congured in the APF in Fig. 1, capacitor voltage ripple is unavoidable. This means the two capacitor voltages continuously change. Thus, the principle for balancing the two capacitor voltages needs to be analyzed. The key requirement is to specify the correct average current owing into the NP to balance the capacitor voltages. The redundant short vectors are still used to implement balance, zero vectors still have no effect on the

capacitor voltages, and long vectors do not affect balance but do cause voltage ripple. However, in this algorithm, medium vectors are not treated as uncontrollable quantities: their effect is taken into consideration. III. PROPOSED SVM ALGORITHM The algorithm utilizes the short vectors to compensate for the effects of all the vectors within each carrier cycle. By predicting the average energy effect of each vector on the timing parameters one cycle earlier, optimized balancing results. Due to the symmetry of the SVM state diagram, the algorithm can be explained in the rst sextant, with the diagram shown in Fig. 3. When vectors V1 , V2 , and V3 are used to compose the desired voltage vector Vref in a modulation cycle Ts , then Vref Ts = V1 T1 + V2 T2 + V3 T3 Ts = T1 + T 2 + T 3 . (1) (2)

Among the four sectors (14), sectors 1 and 2 are similar, in as far as, if the reference vector locates in either of these sectors, no redundant vector sequence exists. For example, the vector sequence in sector 1 is 100-200-210-211-211-210-200-100 and 110-210-220-221-221-220-210-110 for sector 2. In sectors 3 and 4, there are two optional vector sequences. In sector 3, they are 100-110-210-211-211-210-110-100 and 110-210-211221-221-211-210-110, and in sector 4, 100-110-111-211-211111-110-100, and 110-111-211-221-221-211-111-110. Therefore, only sectors 1 and 3 need be analyzed. A. Sector 1 As shown in Fig. 3, the symmetrical modulation vector sequence in sector 1 is 100-200-210-211-211-210-200-100. Current ow paths for each vector are shown in Fig. 4, which are represented by bold lines. For short vectors 100 and 211, provided currents remain in the same direction within the modulation cycle, both capacitors experience the same charging or discharging process. For long vector 200, the current ow causes the same voltage change on each capacitor, resulting in a voltage ripple. The capacitor voltage effect of the medium vector 210 depends on the circuit parameters and conditions, and is determined by the APF currents if a and if c and the conducting time of the medium vector. Table I shows the charging/discharging effect of different vectors on the two dc-link capacitors.

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Fig. 4.

Current ow paths for vectors in sector 1: i. 100; ii. 211; iii. 200; and iv. 210. TABLE I CHARGING/DISCHARGING EFFECT ON TWO DC-LINK CAPACITORS

APF phase currents and the corresponding conduction time for each vector. The higher the switching frequency, the more accurate the predictions. After the capacitor voltage effects of each vector are obtained, these values are added to the initial capacitor voltage values, and the voltage difference is found. The voltage balancing ability of short vector V1 : 100/211 in the modulation cycle is |v1 | = 1 C
T1

if a dt
0

(3)

In sector 1, the short and medium vectors affect the capacitor voltages. Short vectors are used to balance the capacitor voltages. In this algorithm, the current directions within a switching cycle are considered invariable, which is true for most of the conducting periods. Within each modulation cycle, the short vectors implement the same capacitor charging or discharging process, but the capacitor voltage differences can be canceled by apportioning the time given to each short vector. Thus, to accurately balance the capacitor voltages, an exact time distribution of T1 between short vectors 100 and 211 is required. At the beginning of each modulation cycle, the effect of each vector on the capacitor voltages is predicted using the measured

where v1 is the voltage change in the upper link capacitor due to current if a owing for a period of T1 (capacitor C2 is unchanged). The voltage effect of medium vector V3 : 210 on each capacitor (it is assumed C = C1 = C2 ) is v3C 1 = and v3C 2 = 1 C
T3

1 C

T3

if a dt
0

(4)

if c dt.
0

(5)

Assume the initial voltage on the upper capacitor is vc1 and vc2 on the lower capacitor, then the voltage difference for the short

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Fig. 5.

Current ow paths for vectors: i. 110 and ii. 221. TABLE II CHARGING/DISCHARGING EFFECT ON TWO DC-LINK CAPACITORS

vector to balance is cap = c1 c2 + 3c1 3c2 . (6)

Next, the balancing ability of the short vector is compared with the predicted capacitor voltage difference vcap so as to determine the time durations of vectors 100 and 211. If |v1 | < |vcap |, the maximum time of T1 is assigned to that short vector which charges/discharges the capacitor toward eliminating the voltage imbalance. If |v1 | > |vcap |, assuming vcap is positive and if a > 0, then the time for the short vector 211 to discharge the upper capacitor to eliminate the initial capacitor voltage difference vcap is t1 = |Cvcap /if a |. The remaining time (T1 t1 ) is assigned equally to the two short vectors to achieve the same discharging process, thus producing a symmetrical voltage on both capacitors. Assuming the nal conducting time for 100 is ta and tb for 211, then 1 (T1 t1 ) (7) 2 1 tb = (T1 + t1 ) . (8) 2 The same analysis is applied to other vcap conditions and current directions so as to obtain the conducting times for 100 and 211. ta = B. Sector 3 In sector 3, two four-vector sequences are available for selection, namely 100-110-210-211-211-210-110-100 and 110-210211-221-221-211-210-110. In each sequence, there are two pairs of short vectors, 100/211 and 110/221. One pair is restricted to balance the capacitor voltage and the other contributes to the predicted voltage difference. Fig. 5 shows the current ow path for short vectors 110/221, and Table II shows their charging/discharging effect on the two dc-link capacitors. To optimize the balancing effect, the balancing ability of two pairs of short vectors 100/211 and 110/221 is compared to enable proper vector sequence selection. Assume the timing

parameters for short vector pair 100/211 is T1 , T2 for short vector pair 110/221, and T3 for medium vector 210. The voltage balancing ability for short vector 100/211 is |v1 | = 1 C
T1

if a dt
0

(9)

and for short vectors 110/221 is |v2 | = 1 C

T2

if c dt .
0

(10)

If |v1 | > |v2 |, then short vectors 100/211 have better balancing ability than 110/221, i.e., states 110/221 have less effect on the capacitor voltages. Therefore, vector sequence 100-110210-211-211-210-110-100 is selected. With this state sequence, the short vectors 100/211 are used as in sector 1 to balance the capacitor voltages. The effect of vectors 110 and 210 is considered in terms of the predicted voltage difference. The voltage effects of medium vector 210 on the two capacitors are v3C 1 = and v3C 2 = 1 C
T3

1 C

T3

if a dt
0

(11)

if c dt.
0

(12)

The short vector 110 affects the lower capacitor v2 = 1 C

T2

if c dt.
0

(13)

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TABLE III VECTOR SEQUENCE IN SVM PLANE

Assume the initial voltage on the upper capacitor is vC 1 and vC 2 on the lower capacitor. Thus, the nal capacitor voltage difference for the short vectors 100/211 to balance is vcap = vC 1 vC 2 + v3C 1 v3C 2 v2 . (14)

TABLE IV PARAMETERS FOR SIMULATION

After the combined voltage difference is obtained, the time for vectors 100 and 211 is decided by comparison of 1 and cap , as explained in Section III-A. Table III shows the vector sequences in the SVM plane. In each sequence, there is one pair of short vectors to balance the capacitor voltages, and other medium and/or short vectors that inuence the capacitor voltages during the modulation cycle. IV. SIMULATION RESULTS The simulation for Fig. 1 is executed with Matlab using the parameters listed in Table IV. Two scenarios are implemented with balanced source-side impedances. One is with a balanced three-phase rectied bridge resistive load, and the other adds a

single-phase rectied load to the balanced three-phase rectied load as shown in Fig. 1. A. Balanced Load The balanced load simulation results in Fig. 6. show that although the capacitor voltages are balanced and follow the

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Fig. 7.

Simulation results with unbalanced loads.

Fig. 6.

Simulation results with balanced load.

same trace, there is a capacitor voltage ripple. The voltage ripple oscillates at six times the line frequency and is within 0.2%, and the voltage difference between two capacitor voltages is less than 0.06%. Fig. 6(c) shows that the capacitor voltage spikes caused by commutation of the three-phase diode bridge are symmetrically distributed on each capacitor. B. Unbalanced Load The simulation results in Fig. 7 for unbalanced load conditions show that the voltage ripple becomes signicant but the two capacitor voltages still follow the same trace. The maximum capacitor voltage difference is less than 0.4%. C. Evaluation of the Proposed Algorithm The accuracy of the proposed algorithm is switching frequency (fs ) dependent. The algorithm is evaluated by comparison with the traditional balancing method without weighting the
Fig. 8. Evaluation of the proposed algorithm.

functional vectors, i.e., only APF current direction and capacitor voltage difference are considered (similar to symmetric modulation in [6] but when applied to APF). The relation between the maximum capacitor voltage difference under unbalanced load (Table IV) conditions and switching frequency is shown in Fig. 8. As the switching frequency increases, the current values

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Fig. 9.

Capacitor voltages under balanced compensated conditions.

sampled at the beginning of each switching cycle better approximate the average current in the switching period. The capacitor balancing accuracy of this algorithm remains acceptable at a 2.5-kHz switching frequency.

B. Unbalanced Load Fig. 10 shows the capacitor voltages for an unbalanced load, where although the voltages are controlled and balanced, signicant voltage ripple appears. The hardware components must withstand a widely varying voltage stress, where the maximum capacitor voltage difference is less than 1.2%. Fig. 10(c) shows the NP current inp under unbalanced conditions. Under such a condition, signicant fundamental frequency NP current ows in order to balance the real power drawn from each source phase. Therefore, this current needs to be considered when designing the APF. Fig. 11 shows experimental results for evaluating the proposed algorithm. When the switching frequency has been reduced from 12 to 4 kHz for a balanced nonlinear load, the maximum capacitor voltage difference in Fig. 11(a) is less than 0.6%. The less accurate current prediction at 4 kHz results in increased total capacitor voltage ripple, 1.8%. Fig. 11(b) compares the balancing effect for the proposed algorithm (the upper plot) and the method without weighting the functional vectors (the lower plot), working at 12 kHz for the same unbalanced nonlinear load conditions. With the same hardware conditions, the proposed algorithm balances the two capacitor voltages at 172 V dc, with a maximum capacitor voltage difference of 1.2%. Although the method without the weighting functional vectors maintains the capacitor voltages constant, the two capacitor voltages do not balance, having mean values of 171 V dc and 169 V dc, respectively, and the maximum capacitor voltage difference

V. EXPERIMENTAL VERIFICATION The experimental platform based on Fig. 1 uses the same practical parameters as used for the simulations. An Inneon TriCore TC1796 is used to implement the control scheme, and algorithm processing times allow SVM with a switching frequency well in excess of 12 kHz.

A. Balanced Load Fig. 9 shows the controlled capacitor voltages where the practical voltage ripple on the two capacitors follow the same trace, with less than 0.7% total voltage variation. The maximum difference between the capacitor voltages is less than 0.5%, which means component voltage stresses are practically the same. There is a small line frequency voltage component in the capacitor voltages, as shown in the upper plot of Fig. 9(b). This is due to system meassurement errors and nonlinearities. Fig. 9(c) shows the dc-link capacitor NP current inp under balanced condition.

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Fig. 10.

Capacitor voltages for unbalanced compensated conditions.

Fig. 11.

Experimental results for evaluation of the proposed algorithm.

is 2.2%. The inverter switching and ON-state losses are the same for both techniques. VI. CONCLUSION A new algorithm to independently balance the capacitor voltages of the three-level NPC APF is proposed, based on the analysis of the functional vectors in each modulation cycle. The algorithm considers the average energy effect of each vector and the optimal vector sequence involved in each modulation cycle, thus giving optimized balancing results. The proposed algorithm has been compared with the traditional balancing method, without weighting the functional vectors. Although the conventional

method maintains constant capacitor voltage, the two capacitor voltages are not equal. The proposed algorithm unies hardware ratings, reduces capacitor voltage ripple, and attenuates the negative effects associated with voltage oscillations. ACKNOWLEDGMENT The authors thank Mr. C. Croser for his continuous assistance during this research. REFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523, 1981.

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[2] L. Lin, Y.P. Zou, Z. Wang, and H.Y. Jin, Modeling and control of neutralpoint voltage balancing problem in three-level NPC PWM inverters, in Proc. Power Electron. Spec. Conf. (PESC 2005), Recife, Brazil, Jun. 11 16, pp. 861866. [3] C. Newton and M. Sumner, Neutral point control for multi-level inverters: Theory, design and operational limitations, in Proc. Ind. Appl. Soc. (IAS), New Orleans, LA, Oct. 1997, vol. 2, pp. 13361343. [4] D. S. Zhou and D. G. Rouaud, Experimental comparisons of space vector neutral point balancing strategies for three-level topology, IEEE Trans. Power Electron., vol. 16, no. 6, pp. 872879, Nov. 2001. [5] N. Celanovic and D. Boroyevich, A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters, IEEE Trans. Power Electron., vol. 15, no. 2, pp. 242249, Mar. 2000. [6] J. Pou, R. Pindado, D. Boroyevich, and P. Rodriguez, Evaluation of the low-frequency neutral-point voltage oscillations in the thee-level inverter, IEEE Trans. Power Electron., vol. 52, no. 6, pp. 15821588, Dec. 2005. [7] S. Busquets-Monge, J. Bordonau, D. Boroyevich, and S. Somavilla, The nearest three virtual space vector PWM-A comprehensive neutral-point balancing in the three-level NPC inverter, IEEE Power Electron. Lett., vol. 2, no. 1, pp. 1115, Mar. 2004. [8] J. Pou, J. Zaragoza, P. Rodriguez, S. Ceballos, V. M. Sala, R. P. Burgos, and D. Boroyevich, Fast-processing modulation strategy for the neutralpoint-clamped converter with total elimination of low-frequency voltage oscillations in the neutral point, IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 22882294, Aug. 2007. [9] T. T Jin, J. Wen, and K. Smedley, Control and topologies for three-phase three-level active power lters, in Proc. Appl. Power Electron. Conf. (APEC 2005), Austin, TX, Mar. 610, pp. 655664. [10] B.-R. Lin, C. H. Huang, T.-Y. Yang, and Y. C. Lee, Analysis and implementation of shunt active power lter with three-level PWM scheme, in Proc. Power Electron. Drive Syst. (PEDS 2003), Singapore, Nov. 1720, pp. 15801585. [11] V. Aburto, M. Schneider, L. Moran, and J. Dixon, An active power lter implemented with a three-level NPC voltage-source inverter, in IEEE Power Electron. Spec. Conf. (PESC 1997) Rec., St. Louis, MO, Jun. 22 27, pp. 11211126. [12] E. I. Gutierrez and J. L. Duran-Gomez, Power quality improvement of a current-pulsed power supply based on a three-level NPC PWM VSI scheme as an active power lter, in Proc. Int. Power Electron. Congr. (CIEP 2006), Cholula, Mexico, Oct. 1618, pp. 16. [13] B.-R. Lin and T.-Y. Yang, Three-level voltage-source inverter for shunt active lter, in Inst. Electr. Eng. Proc. Electr. Power Appl., Nov. 2004, vol. 151, no. 6, pp. 744751. [14] A. M. Massoud, S. J. Finney, A. J. Cruden, and B. W. Williams, Threephase, three-wire, ve-level cascaded shunt active lter for power conditioning, using two different space vector modulation techniques, IEEE Trans. Power Del., vol. 22, no. 4, pp. 23492361, Oct. 2007. [15] P. -C. Tan, P. C. Loh, and D. G. Holmes, A robust multilevel hybrid compensation system for 25-kV electried railway applications, IEEE Trans. Power Elect., vol. 19, no. 4, pp. 10431052, Jul. 2004. [16] M. Basu, S. P. Das, and G. K. Dubey, Parallel converter scheme for highpower active power lters, in Inst. Electr. Eng. Proc. Electr. Power Appl., Jul. 2004, vol. 151, no. 4, pp. 460466. [17] N. Celanovic and D. Boroyevich, A fast space-vector modulation algorithm for multilevel three-phase converters, IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 637641, Mar./Apr. 2001.

Stephen Jon Finney received the M.Eng. degree from Loughborough University of Technology, Loughborough, U.K., in 1988, and the Ph.D. degree from Heriot-Watt University, Edinburgh, U.K., in 1995. For two years, he was with the Electricity Council Research Centre Laboratories near Chester, U.K. He is currently a Senior Lecturer at the Department of Electronics and Electrical Engineering, Strathclyde University, Glasgow, U.K. His current research interests include soft-switching techniques, power semiconductor protection, energy recovery snubber circuits, and low-distortion rectier topologies.

Ahmed Massoud received the B.Sc. (rst class honours) and M. Sc. degrees from the Faculty of engineering, Alexandria University, Alexandria, Egypt, in 1997 and 2000, respectively, and the Ph.D. degree in electrical engineering from the Computing and Electrical Department, Heriot-Watt University, Edinburgh, U.K., in 2004. He is currently a Research Fellow at the Department of Electronics and Electrical Engineering, Strathclyde University, Glasgow, U.K. His current research interests include power quality, active power lter, and multilevel converters.

Barry Wayne Williams received the M.Eng.Sc. degree from the University of Adelaide, Adelaide, Australia, in 1978, and the Ph.D. degree from Cambridge University, Cambridge, U.K., in 1980. After seven years as a Lecturer at Imperial College, University of London, U.K., he was appointed to a Chair of Electrical Engineering at Heriot-Watt University, Edinburgh, U.K, in 1986. He is currently a Professor at the Department of Electronics and Electrical Engineering, Strathclyde University, Glasgow, U.K. His teaching covers power electronics and drive systems. He is the author or coauthor of texts published in the eld of power electroncs. His current research interests include power semiconductor modeling and protection, converter topologies and soft-switching techniques, and application of application-specied integrated circuits and microprocessors to industrial electronics.

Huibin Zhang received the M.Sc. degree in electrical engineering from the Computing and Electrical Department, Heriot-Watt University, Edinburgh, U.K., in 2004. He is currently working toward the Ph.D. degree at the Department of Electronics and Electrical Engineering, Strathclyde University, Glasgow, U.K. His current research interests include active power lter and multilevel converters.