APPLICATION NOTE AN1935

How to Boot from a Single Level Cell NAND Flash Memory

This Application Note describes how to boot from an STMicroelectronics Single Level Cell NAND Flash memory. Single Level Cell NAND Flash memories include two families:

the Small Page (528 Byte/ 264 Word Page) NAND Flash family (NANDxxx-A) the Large Page (2112 Byte/1056 Word Page) NAND Flash family (NANDxxx-B)

The terms of Small Page and Large Page will be used to refer to the two respective families throughout the document.

INTRODUCTION
The requirements of PDA (Personal Digital Assistants) and mobile phone platforms are converging because of multimedia applications such as graphic and audio accelerators, LCDs and data and code storage. Typically these systems require a large storage capacity for Operating System (OS) images, multimedia objects such as MP3 files and applications such as Java applets. NAND Flash memories are becoming a must for these applications. Besides a high throughput, fast erasing time and high density, the cost per Byte is much lower than for NOR architecture based Flash memories. As a result NAND is the best choice to store large quantities of data and code. This Application Note shows how to use a Single Level Cell NAND Flash as the primary memory device. It also describes different ways to boot a system from a NAND device on a general purpose architecture. Since the NAND can be used in-system and easily used for booting, ST has introduced the Automatic Page 0 Read at Power-Up, where the first page is available in the NAND internal buffer after the power is supplied to device. This means that the CPU can directly download the code from page 0 by toggling the Read Enable, R, signal. Devices are shipped from factory with Block 0 always valid, so using this block to store boot code means that boot code can be read from the NAND without having to use Error Correction Code (ECC).

November 2004

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TABLE OF CONTENTS
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 OVERVIEW OF TYPICAL BOOT ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 1. Boot Architecture without NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 HOW TO BOOT FROM A SINGLE LEVEL CELL NAND FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Large Page and Small Page Single Level Cell NAND Flash Families . . . . . . . . . . . . . . . . . . . . . 5 Table 1. .Large Page versus Small Page NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 USING BLOCK 0 TO STORE CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Large Page Divided into Chunks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Automatic Page 0 Read at Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Sequential Row Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 BOOT LOADER METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standard Boot Loader Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Standard Boot Loader Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Standard Boot Loader Method Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Two Level Boot Loader Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Case of a Small Page Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Case of a Large Page Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Two Level Boot Loader Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Two Level Boot Loader Method Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BOOT ENGINE METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9. Boot Engine Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 NAND PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 NAND PROTECTION DURING BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Connecting the NAND to the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 APPENDIX A.PRATICAL IMPLEMENTATION OF TWO LEVEL BOOT LOADER METHOD . . . . . . 15 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11.Reference Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Code Shadowing Performance Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Figure 12.NAND Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2. Execution Time, Internal vs. External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. Execution Time, With DMA vs. Without DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ECC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.Code Transfer to External SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14.CPU vs. DMA Usage Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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OVERVIEW OF TYPICAL BOOT ARCHITECTURE

Typically System Architecture consists of a CPU, one or more Non-Volatile Memory (NVM) and a Random Access Memory (RAM). The CPU starts its operations recovering the Reset Vector and the Boot Code from the NVM. This last operation is called the Boot Loader. The Reset Vector initializes the state of all the devices (e.g. POST Power On Self Test, control registers) and then the boot code downloads the OS code and drivers into the RAM. Once the Operating System is loaded into the RAM, it takes control of the system. This means that when power is supplied to the system and a reset signal is generated, the system components change from an unknown state to a known state. When a boot is initiated, the CPU places on the bus a default address that points to a location in memory that must contain the Reset Vector. To ensure compatibility, this address is typically either at the top (e.g. FFFFFFF0h) or bottom (e.g. 00000000h) of the CPU's address space. Only after it has accessed this address, can the CPU start to fetch instructions, data or a jump address from the Reset Vector location. For this operation the memory must allow XIP (eXecute In Place). A memory technology allows XIP only if it supports direct code execution. This means that the CPU can execute the code directly from it (cycle fetch-decode-execute). Figure 1. shows an example of a typical architecture used in other types of applications, for example DVDs and second generation mobile phones. The Non-Volatile Memory that provides the random access feature must be mapped at the top or at the bottom of the CPU's address space. Figure 1. Boot Architecture without NAND

00000000h ROM CPU

Reset Vector Boot Code OS Code

SRAM
Working Area

Reset

Ai08646

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HOW TO BOOT FROM A SINGLE LEVEL CELL NAND FLASH

Single Level Cell NAND Flash memories are suitable for the boot procedure if they are used in association with a RAM memory. The NAND Flash memory provides the high density required to store the code while the RAM provides the random access required to perform the code XIP. When a boot is initiated, a mechanism called Code Shadowing transfers the code from the NAND Flash to the RAM, where it is executed. This code can be the image of the operating system or a part of the boot loader (see BOOT LOADER METHOD section). The high throughput in read operations from the NAND Flash, allows the Code Shadowing to be implemented in a very short time. As the code is subsequently executed in a RAM, booting from NAND is very efficient. In fact executing code in Random Access Memories is faster and consumes less power than other memory technologies. This implies that the time necessary to do Code Shadowing and Execution in RAM is less than the time necessary to execute directly in a Non-volatile Memory. For this reason the Code Shadowing approach consumes less power then the XIP approach, as the NVM device goes into Standby (low power consumption) when the transfer is completed. Direct Memory Access (DMA) can be used for Code Shadowing to increase the performance. In fact, the read operation from the NAND, and in particular the speed of the data transfer between the NAND page buffer and the RAM, is greatly increased thanks to DMA. There are two different methods that can be adopted to boot from NAND using Code Shadowing techniques:

Boot Loader Method Boot Engine Method

The first is a software implementation of Code Shadowing. It uses a ROM, mapped at the top of the controller address space, that contains the Reset Code and the Boot Loader Code. The second is a hardware implementation, where a dedicated part loads the boot loader code from the NAND into the RAM, while keeps the controller in the reset state. A RAM is mapped at the top of the microcontroller address space. Large Page and Small Page Single Level Cell NAND Flash Families The feature differences between the Large Page and Small Page Single Level Cell NAND Flash families are summarized in Table 1. Table 1. .Large Page versus Small Page NAND Flash
NAND Flash Memory Large Page NAND Flash Small Page NAND Flash Number of Pages 64 32 Page Size 2112 Bytes 528 Bytes Block Size 128 KBytes 16 KBytes Features Supported Cache Read / Autoread Page 0(1) Sequential Row Read / Auto Read Page 0

Note: 1. To enable this option in Large Page NAND Flash devices, the PRL pin must be tied to VDD (if the PRL pin is High, a Blocks Unlock Command is required before writing to the NAND Flash).

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USING BLOCK 0 TO STORE CODE

Error Correction Code Normally an Error Correction Code algorithm is used to correct and detect any errors in Single Level Cell NAND Flash memories. In some recent controllers the ECC implemented by hardware. In other controllers the ECC has to be implemented by software. Small Page and Large Page NAND Flash memory Pages are split into two areas:

Main Area, used to store the data Spare Area, used to store the ECC

When a Page is read, an ECC checks and eventually corrects the data read. This is also valid for Code Shadowing, as the code read from the NAND is copied into the RAM after the ECC check. The difference in page size (528 Bytes for the Small Page family and 2112 Bytes for the Large Page family) is not critical for the implementation of the ECC. In fact it is possible to use the same algorithm for Large Page devices as for Small Page ones. The method consists in organizing large pages as four smaller logical pages, called chunks, as shown in Figure 2. As STs Single Level Cell NAND devices are shipped from the factory with Block 0 always valid, the ECC check can be avoided for Block 0. This makes the Code Shadowing process simpler and faster and means that both the Main and Spare Areas of Block 0 can be used to store the Boot Code. Note that no ECC or BBM information can be stored in the Spare Area of Block 0. Figure 2. Large Page Divided into Chunks
2048 Bytes Main Area 64 Bytes Spare Area

1st Page Main Area

2nd Page Main Area

3rd Page Main Area

4th Page Main Area

1st Page Spare 2nd Page Spare 3rd Page Spare

4th Page Spare

ai10704

Bad Blocks Other blocks in the NAND may be Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to datasheet for more details), and the number of Bad Block will not exceed 2% of the total number of blocks. These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes (for example using the spare area). Automatic Page 0 Read at Power-Up Another feature that ST has introduced to simplify booting, is Automatic Page 0 Read at Power-Up. This feature makes the first page available in the NAND internal buffer after power-up, which allows the CPU to directly download the code from Page 0 by toggling the Read Enable, R, signal.

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Sequential Row Read The Sequential Row Read operation implemented in ST Small Page NAND Flash memories is also very useful for Code Shadowing (see Figure 3.). Sequential Row Read is not available in ST Large Page NAND Flash memories. After the data in last column of the page is output, if the Read Enable signal is pulsed and Chip Enable remains Low, then the next page is automatically loaded into the Page Buffer and the read operation continues. Note that a Sequential Row Read operation can only be used to read within a block and in a device without the Chip Enable Dont Care Option. If the device has the Automatic Page 0 Read at Power-Up option only (Chip Enable Dont Care disabled), it automatically enters Sequential Row Read mode after the power-up sequence, and starts reading Page 0, Page 1, etc., until the last memory location is reached. If the device has the Chip Enable Dont Care and Automatic Page 0 Read at Power-Up, only the first page (Page 0) will be automatically read after the power-up sequence. Cache Read The Cache Read operation implemented in ST Large Page NAND Flash memories is also very useful for Code Shadowing (see Figure 3.). Cache Read is not available in ST Small Page NAND Flash memories. Reading data using the Cache Register dramatically improves the read throughput. As soon as the user starts to read one page, the device automatically loads the next page into the Cache Register. This means that a Cache Read operation can be used to read an entire block uninterruptedly after the first latency time. As a result, using a device with Automatic Page 0 Read at Power-Up and Sequential Row Read or Cache Read features, simplifies the Code Shadowing operation in block 0, as all that is required is to toggle the Read Enable, R, signal. Figure 3. Sequential Row Read Operations
tBLBH1
(Read Busy time)

tBLBH1

tBLBH1

RB Busy I/O 00h/ 01h/ 50h Command Code

ai07597

Busy 1st Page Output 2nd Page Output

Busy Nth Page Output

Address Inputs

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Figure 4. Cache Read Operation

(Read Busy time)

tBLBH1

RB Busy I/O
00h 31h

1st page

2nd page

3rd page

last page

34h

Read Setup Code

Cache Read Confirm Code

Block N Data Output

Exit Cache Read Code

ai08661

BOOT LOADER METHOD

Description The Boot Loader Method uses a ROM to execute the initial code, which wakes up the system after powerup and contains the Reset Vector code and Boot Loader code. There are two different ways to implement the Boot Loader Method:

Standard Boot Loader method, where all the Boot Loader code is stored in the ROM Two Level Boot Loader method, where part of the Boot Loader code is stored in the ROM and part in the NAND.

Standard Boot Loader Method Figure 5. shows an example of a Standard Boot Loader method for a PDA or 2,5/3G phone architecture. The code is stored in two different memories: a small ROM embedded with the microcontroller that contains the Boot Loader code and a high density NAND Flash memory that contains the OS code and the application data. The RAM may be a DRAM because of the density requirements (more RAM to manage multimedia objects). In the Standard Boot Loader Method there are three operations to perform (see Figure 6.): 1. System Initialisation: hardware initialisation of all the system functions - Execute code stored inside the ROM (Reset Vector and Boot Loader) 2. Code Shadowing: Download the code from the NAND into RAM, checking with ECC 3. Start OS: Pass execution control to the code in RAM. The embedded ROM provides random access capability, so the Boot Loader runs directly from it. After it initializes the board, the Boot Loader downloads the OS code from the NAND device into the DRAM and passes over the control. As the OS code is usually bigger than NAND Block 0, a robust Boot Loader solution has to use ECC. The ECC can be implemented in either the hardware or software. Implementing it in the hardware is the best solution for performance but not for cost, as it requires a specific hardware design. The software solution is easier to implement, but it introduces overheads in terms of execution time and memory space, as it is part of the Boot Loader that is stored in the ROM. The page read operation should use Direct Memory Access (DMA) to increase the performance. The use of DMA speeds up the data transfer and the ECC calculation by executing them in parallel. In practice,
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during the software calculation of the ECC, a new page of memory is transferred from the NAND Flash to the RAM via DMA. Figure 5. Standard Boot Loader Method

00000000h ROM CPU

Reset Vector Boot Loader &ECC

DRAM
OS Execution

NAND
OS Code OS Code

Reset

Ai08647

Note: 1. In this example of a Standard Boot Loader method it is supposed that the ECC is implemented via software.

Figure 6. Standard Boot Loader Method Flowchart

Start Boot Code

Reset Vector & Initial Configuration

Read a Page from NAND to RAM

ECC on Page in RAM

NO

End of Download? YES

Branch at Execution Address

Ai08648

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Two Level Boot Loader Method The second implementation of the Boot Loader Method takes advantage of ST Single Level Cell NAND features to save ROM space, and consequently reduce cost and board space. As shown in Figure 7., it splits the Boot Loader code into two different levels. In this implementation the first level Boot Loader stored in the ROM does not contain ECC. For a NAND Flash of the Small Page family that has the Automatic Page 0 Read at Power-Up and Sequential Row Read features, it is possible to download all of Block 0 with a single DMA request. For a NAND Flash of the Large Page family, it is also possible to download an entire block with a single DMA request but a Cache Read command and an Exit Cache Read command are required first. The second level Boot Loader is stored in the NAND Block 0. It downloads the OS code and checks the ECC. Case of a Small Page Device. This implementation uses:

Automatic Page 0 Read at Power-Up, where the first page is ready in the Page Buffer after powerup, so it can be read by toggling R, Sequential Row Read for all of Block 0, when a page has been read, the next page is automatically loaded into the Page Buffer and read, Block 0 Valid, no ECC is necessary, Entire Block 0 is used to store code, the Spare Area is used as Main Area, Ready/Busy, RB, pin connected to the Wait State Machine of the Memory Controller: Between two page reads, the device goes into busy state, so the memory controller waits until the device is ready, DMA controller asks for a memory access to the Memory Controller, who answers when it is ready,

Thanks to these features, the downloading process of the first level Boot Loader is simplified and consists of only three steps: 1. Set DMA registers (Main Configuration, Source Address, Destination Address and Transfer Width), 2. Start DMA, 3. Jump to Second Level Boot Loader. See Figure 8. for a practical implementation. Case of a Large Page Device. The Cache Read operation can be used, which means that once a Cache Read command has been issued and the first page has been loaded into the buffer, block 0 can be downloaded entirely with a single uninterrupted DMA request as consecutive pages are downloaded with no latency time. So for a Large Page device, the downloading process of the first level Boot Loader becomes: 1. Issue Cache Read command 2. Set DMA registers (Main Configuration, Source Address, Destination Address and Transfer Width) 3. Start DMA 4. Issue Exit Cache Read comand 5. Jump to Second Level Boot Loader. As for the Standard Boot Loader method, the page read operation should use Direct Memory Access (DMA) to increase the performance. The use of DMA speeds up the data transfer and the ECC calculation by executing them in parallel. In practice, during the software calculation of the ECC, a new page of memory is transferred from the NAND Flash to the RAM via DMA.

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Figure 7. Two Level Boot Loader Method

DRAM 00000000h ROM CPU

Reset Vector Boot Loader 1 Working Area

NAND
Boot Loader 2 & ECC algorithm OS Code

Reset

Ai08649

Note: 1. In this example of a Two Level Boot Loader method it is supposed that the ECC is implemented via software.

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Figure 8. Two Level Boot Loader Method Flowchart

Start Boot Code

Reset Vector & Initial Configuration First Level Boot Loader DMA Configuration

DMA transfer START

NO

Transfer Complete? YES

Branch at Second Level Boot Loader Second Level Boot Loader Start

Read a Page from NAND to RAM

ECC on Page in RAM

NO

End of Download? YES

Branch at Execution Address

Ai08650

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BOOT ENGINE METHOD

In the Boot Engine Method, Code Shadowing is done using a hardware mechanism. Usually the ECC is hardware implemented in this kind of mechanism. This mechanism transfers the initial code from the NAND device into the RAM device, during which it has to activate the CPU Reset signal. After the transfer has completed, the Boot Engine mechanism wakes up the CPU by releasing the Reset signal. Finally the CPU takes control, executing the code in the RAM, which must be mapped at the beginning of the CPU address space. Note that, for the same reason as explained before, it is not necessary to execute ECC on Block 0. In addition, if Automatic Page 0 Read at Power-Up and Sequential Row Read are used, the Boot Engine hardware is simplified as the Boot Engine mechanism only has to toggle the Read Enable signal to download the entire Block 0 into the RAM. From the point of view of the NAND, this method is similar to the Two Level Boot Loader, in that Block 0 is used to store the Boot code while the others blocks store the OS code. The code stored in Block 0 of the NAND device is the same as the code stored in the ROM in the Standard Boot Loader method, so it has the same characteristics. Figure 9. Boot Engine Method

00000000h BE DRAM
OS Execution

NAND
Block 0 Reset Vector Boot Loader OS Code OS Code

CPU

Boot Buffer Download Engine ECC

Microcontroller equiped with BFN

Ai08651b

NAND PROGRAMMING
To be able to perform a boot from a Single Level Cell NAND Flash memory, it is necessary to program the NAND devices with the Boot code and OS code. Typically, systems with NAND devices do not have the NAND programming functionality. So it is necessary to use Programmer tools to perform this operation. NAND program operations differ according to the type of Boot Loader used:

Standard Boot Loader. Only the OS code has to be programmed in the NAND as the Boot Code, Reset Vector and ECC software are stored in a ROM Two Level Boot Loader. Boot Loader code has to be programmed in Block 0 of the NAND and the OS image in the other blocks

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The Block 0 must be programmed entirely using both the Main and the Spare Areas to store the code (Block 0 does not require ECC). The others blocks must be programmed using Main Area for the code and the Spare Area for the ECC and BBM (Bad Block Management) information. Bad Blocks may be discovered during the program operation. These blocks cannot be used and the code should be programmed in the next valid block (refer to AN1819 Bad Block Management in Single Level Cell NAND Flash Memories, the NAND128-A, NAND256-A, NAND512-A, NAND01G-A datasheet and the NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B, 2112 Byte/1056 Word Page datasheet for further details).

NAND PROTECTION DURING BOOT

NAND device store the code and data necessary for the system to work. It is a good idea to protect the NAND device from any noise generated during the power-up sequence, as the state of the system bus is unknown during power-up. The Write Protect signal, WP, can be used to avoid unwanted access to the NAND device and data corruption during the power-up sequence. Figure 10. shows two possible solutions that can be used to connect the NAND to the microcontroller. Figure 10. Connecting the NAND to the Microcontroller

NAND System Reset IO Pin WP System Reset WP

NAND

Ai08652

CONCLUSION
Single Level Cell NAND Flash memories (including the Small Page and the Large Page NAND Flash families) can be used as a primary non-volatile memory device in an application, and can be used to store the initializing code used to boot a system. Two different methods of the Code Shadowing technique can be used, depending on whether the performance (Boot Engine) or simplicity of the design (Boot Loader) is the most important. Due to the advantages of increased storage capability and lower cost, ST recommends to use NAND devices to boot systems. In addition, booting from a NAND Flash device increases the performance of a system thanks to the excellent throughput provided by NAND technology and the fast code execution in the RAM.

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APPENDIX A. PRATICAL IMPLEMENTATION OF TWO LEVEL BOOT LOADER METHOD

This section presents a practical implementation of the Two Level Boot Loader Method, on a generic development board, not specifically designed for the boot from NAND. Architecture The Hardware used in this study was an ARM Evaluator-7T board. The ARM Evaluator-7T board is a simple ARM7TDMI-based platform that includes a minimal set of core facilities. The default configuration has been extended to host the NAND device, connecting it to the FLASH/ROM controller (see AN1817). This platform has the follow characteristics:

CPU 16/32 bit RISC ARM7TDMI core based DMA channel ROM/SRAM and Flash Memory Controller 8 KB Internal RAM 32 bit Timers Clock at 50MHz (20ns)

ROM memory (mapped on Bank 0) SRAM memory (mapped on Bank 1-2) Small Page NAND memory (mapped on Bank 3)

In addition, this evaluation board allows the ROM that contains the Boot code to be re-programmed. The reference architecture is shown in Figure 11. Figure 11. Reference Architecture

NAND ROM SRAM

DMA Internal RAM

Memory Control

Bus Router Core CPU

Ai08653

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Code Shadowing Performance Improvement This section shows how the Code Shadowing was optimized using the Two Level Boot Loader Method with ECC software and using DMA. At power-up, the microcontroller executes the code stored in the ROM. It contains the instructions for the system initialization and the First Level Boot Loader. It is important to optimize the data transfer between the NAND and SRAM devices connected to the memory controller, as this is the main operation in the Boot Loader Method. Figure 12. shows the details of the page read operation. It consists of three steps: 1. Command and Addresses Input (1+4 Bytes) 2. Busy - Wait for page buffer to be loaded 3. Data Output - transfer to RAM (528 Bytes) Only steps 1 and 3 can be optimized, as step 2 (Busy) is a structural characteristic of the NAND Flash device and so cannot be optimized. DMA can be used to improve step 3. In addition, to reduce the access time, the entire Second Level Boot Loader code should be executed from the CPU internal SRAM memory, which is connected to the CPU by a dedicated bus. Table 2. and Table 3. show the improvement in performance when the Boot Loader code is executed in the internal RAM and a DMA is used. The data refers to a 64 KByte OS code. Figure 12. NAND Read Operation

RB

I/O

Command

Address Step 2, Busy

Data Output

Step 1, Command and Address Input

Step 3, Data Output (Transfer to RAM)

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Table 2. Execution Time, Internal vs. External Memory

Execution Time Improvement External Memory 150ms Internal Memory 66ms 56% Without DMA, 64 KByte OS code Conditions

Table 3. Execution Time, With DMA vs. Without DMA

Execution Time Improvement Without DMA 66ms With DMA 17ms 74% Boot Loader executed in Internal RAM, 64 KByte OS code Conditions

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ECC Implementation The architecture used, allows to perform ECC and data transfers in different ways and allows the two operations to be overlapped. ECC is not necessary to read Block 0 because ST NAND devices are shipped with Block 0 valid. So the First Level Boots Loader, stored in the ROM, does not contain ECC software, which saves memory space. The First Level Boot Loader loads from the NAND (Block 0) to internal memory. The Second Level Boot Loader downloads all the OS code from the NAND, using ECC and the DMA channel. As previously shown, to increase performance, the Boot Loader and ECC code must be executed in the internal memory and DMA must be used. During DMA data transfer operations the CPU is free, so it may be used to execute the ECC software. So the CPU enables the DMA channel to transfer the OS code from the NAND into the RAM, and while the DMA performs this operation, it can check the ECC. The following example shows how to implement this mechanism. The main actions are:

DMA transfers page n+1 from NAND to external SRAM; CPU performs ECC on page n.

Note that the OS code is stored in the Main Area of the NAND pages, so each new page must be transferred into the external SRAM, starting at the end of the Main Area of the previous page (see Figure 13.). In this case it is necessary store a copy of the previous Spare Area in order to allow the ECC software to work properly. Figure 14. shows the time usage for the CPU and DMA in a single page transfer operation from NAND to RAM. The time measured for ECC execution on 528 Bytes is 250s. As previously shown, the transfer time of 528 Bytes with DMA is low compared to the ECC calculation time. Figure 13. Code Transfer to External SRAM

NAND External SRAM

Page n Spare Area Main Area

Page n Page n+1

Page n+1

Spare Area

ECC

CPU

DMA

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Figure 14. CPU vs. DMA Usage Time

Without DMA Resource

DMA CPU Command

(Page) Read

unused ECC executed directly in SRAM unused

Transfer Data from NAND to SRAM

15s

500s

250s

Time

Resource

With DMA

DMA

unused Read

DMA

unused unused

CPU Command
(Page)

ECC executed directly in SRAM

15s

250s

Time

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Note: The times depend on the Hardware used and the algorithms are not optimized.

REFERENCES
The following documents, related to Single Level Cell NAND Flash Memories, are available on www.st.com

NAND128-A, NAND256-A, NAND512-A, NAND01G-A, 528 Byte/ 264 Word Page datasheet NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B, 2112 Byte/1056 Word Page datasheet AN1823 Error Correction Code in Single Level Cell NAND Flash Memories AN1819 Bad Block Management in Single Level Cell NAND Flash Memories

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REVISION HISTORY
Table 4. Document Revision History
Date 07-May-2004 Version 1.0 First Issue Document updated to apply also to the Large Page NAND Flash family (NANDxxx-B). Large Page and Small Page Single Level Cell NAND Flash Families and Cache Read paragraphs added. Figure 2., Large Page Divided into Chunks and Figure 4., Cache Read Operation added. Two Level Boot Loader Method paragraph and BOOT ENGINE METHOD section updated. Note added to Figure 7., Two Level Boot Loader Method and Figure 5., Standard Boot Loader Method. Revision Details

12-Nov-2004

2.0

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If you have any questions or suggestions concerning the matters raised in this document, please refer to the MPG request support web page: http://www.st.com/askmemory

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com

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