IRFP240

Data Sheet January 2002

20A, 200V, 0.180 Ohm, N-Channel Power MOSFET

This N-Channel enhancement mode silicon gate power eld effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specied level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17422.

Features
20A, 200V rDS(ON) = 0.180 Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards

Ordering Information
PART NUMBER IRFP240 PACKAGE TO-247 BRAND IRFP240

Symbol
D

NOTE: When ordering, include the entire part number.

G

Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE

DRAIN (FLANGE)

2002 Fairchild Semiconductor Corporation

IRFP240 Rev. B

IRFP240
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specied IRFP240 200 200 20 12 80 20 150 1.2 510 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC
oC oC

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. TJ = 25oC to 125oC.

Electrical Specications
PARAMETER

TC = 25oC, Unless Otherwise Specied SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured between the Contact Screw on Header that is Closer to Source and Gate Pins and Center of Die Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances
D LD G LS S

TEST CONDITIONS VGS = 0V, ID = 250A (Figure 10) VGS = VDS , ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX , VGS = 11V (Figure 7) VGS = 20V VGS = 10V, ID = 10A (Figures 8, 9) VDS 10V, ID = 11A VDD = 100V, ID 18A, RGS = 9.1 , VGS = 10V, RL = 5.4 MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID = 18A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11)

MIN 200 2.0 20 6.7 -

TYP 0.14 11 14 51 45 36 43 10 32 1275 500 160 5.0

MAX 4.0 25 250 100 0.18 21 77 68 54 60 -

UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH

Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero-Gate Voltage Drain Current

On-State Drain Current (Note 2) Gate to Source Leakage Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain Miller Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance

Internal Source Inductance

LS

12.5

nH

Junction to Case Junction to Ambient

RJC RJA Free Air Operation

0.83 30

oC/W oC/W

2002 Fairchild Semiconductor Corporation

IRFP240 Rev. B

IRFP240
Source to Drain Diode Specications
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D

MIN -

TYP -

MAX 20 80

UNITS A A

Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES:

VSD trr QRR

TJ TJ TJ

= 25oC, ISD = 18A, VGS = 0V (Figure 13) = 25oC, ISD = 18A, dISD/dt = 100A/s = 25oC, ISD = 18A, dISD/dt = 100A/s

120 1.3

250 2.6

2.0 530 5.6

V ns C

2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 1.9mH, RGS = 50 , peak IAS = 20A.

Typical Performance Curves

1.2 POWER DISSIPATION MULTIPLIER 1.0

Unless Otherwise Specied

20

0.8 0.6 0.4 0.2 0

ID, DRAIN CURRENT (A)

16

12

0 0 50 100 150 25 50 75 100 125 150 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

ZJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE

1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 10-2 SINGLE PULSE PDM t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 t1, RECTANGULAR PULSE DURATION (s) 0.1 1 10

10-3 -5 10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

2002 Fairchild Semiconductor Corporation

IRFP240 Rev. B

IRFP240 Typical Performance Curves

1000 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 10s 100s 10 1ms 10ms 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 0.1 1 102 DC ID , DRAIN CURRENT (A)

Unless Otherwise Specied (Continued)

30 VGS = 8V 24 VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 7V

ID , DRAIN CURRENT (A)

100

18 VGS = 6V

12

6 VGS = 5V VGS = 4V 0 20 40 60 80 100 VDS , DRAIN TO SOURCE VOLTAGE (V)

10 VDS , DRAIN TO SOURCE VOLTAGE (V)

103

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

FIGURE 5. OUTPUT CHARACTERISTICS

30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID , DRAIN CURRENT (A) 24 VGS = 10V VGS = 8V ID , DRAIN CURRENT (A) VGS = 7V

100

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V

10

18

12

VGS = 6V

TJ = 150oC 1

TJ = 25oC

6 VGS = 5V 0 0 1 2 3 VGS = 4V 4 5 VDS , DRAIN TO SOURCE VOLTAGE (V)

0.1 0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10

FIGURE 6. SATURATION CHARACTERISTICS

FIGURE 7. TRANSFER CHARACTERISTICS

3.0 1.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 2s DUTY CYCLE = 0.5% MAX rDS(ON) , DRAIN TO SOURCE 1.2 ON RESISTANCE () 2.4

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 10A, VGS = 10V

1.8

0.9 VGS = 10V 0.6

1.2

0.6

0.3 VGS = 20V 0 0 15 30 45 60 75 ID , DRAIN CURRENT (A)

0 -60

-40

-20

20

40

60

80

100 120 140 160

TJ, JUNCTION TEMPERATURE (oC)

NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE GATE VOLTAGE AND DRAIN CURRENT
2002 Fairchild Semiconductor Corporation

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

IRFP240 Rev. B

IRFP240 Typical Performance Curves

1.25 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN 1.15 C, CAPACITANCE (pF) 2400

Unless Otherwise Specied (Continued)

3000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS

1.05

1800

0.95

1200

COSS

0.85

600

CRSS

0.75 -60

-40

-20

20

40

60

80

100 120 140 160

10

20

50

100

TJ , JUNCTION TEMPERATURE (oC)

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

15 ISD , SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX gfs , TRANSCONDUCTANCE (S) 12 TJ = 25oC 9 TJ = 150oC 6

100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

10

TJ = 150oC 1

TJ = 25oC 0.1 0 0.4 0.8 1.2 1.6 2.0

0 0 6 12 18 ID , DRAIN CURRENT (A) 24 30

VSD , SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT

FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20 VGS , GATE TO SOURCE VOLTAGE (V) ID = 18A 16 VDS = 40V 12 VDS = 100V VDS = 160V

0 0 12 24 36 48 60 Qg, GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

2002 Fairchild Semiconductor Corporation

IRFP240 Rev. B

IRFP240 Test Circuits and Waveforms

VDS tP IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG
+

BVDSS L VDS VDD

VDD

0V

IAS 0.01

0 tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT

FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON td(ON) tr VDS RL 90%

tOFF td(OFF) tf 90%

RG DUT

VDD

10% 90%

10%

VGS 0 10%

50% PULSE WIDTH

50%

VGS

FIGURE 17. SWITCHING TIME TEST CIRCUIT

FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

CURRENT REGULATOR

VDS (ISOLATED SUPPLY)

VDD Qg(TOT) VGS

12V BATTERY

0.2F

50k 0.3F

SAME TYPE AS DUT Qgs

Qgd

D G DUT 0

VDS

IG(REF) 0 IG CURRENT SAMPLING RESISTOR

S VDS ID CURRENT SAMPLING RESISTOR

IG(REF) 0

FIGURE 19. GATE CHARGE TEST CIRCUIT

FIGURE 20. GATE CHARGE WAVEFORMS

2002 Fairchild Semiconductor Corporation

IRFP240 Rev. B

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Rev. H4

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