Accurate Timing Simulation of Mixed-Signal Circuits with a Dynamic Delay Model

Tianwen Tang and Xing Zhou School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Republic of Singapore
Abstract
A dynamic delay model is described and implemented in a single-engine multi-level circuit simulator. It is demonstrated that the model provides near circuit-level accuracy with gatelevel speed, and is useful for accurate timing simulation of digital and mixed-signal integrated circuits. as well as mixed-signal circuits at the gate level with near circuit-level accuracy.

2. Delay modeling
The basic model for a logic gate has two representations [2]: behavioral (Boolean function with delay, rise and fall time parameters) and structural (subcircuit consisting of transistors that make up the gate). The logic parameters associated with the gate model, such as input and output capacitances, rise and fall delays, rise and fall times, can be obtained by a full circuit-level electrical simulation of the subcircuit of the gate. The gate delay (including rise and fall delays) uses a generalized expression of the commonly-used linear delay model [3]: td = tdi(ti,N i,C load) + R eff(ti,N i,C load) C load (1)

1. Introduction
The Berkeley SPICE [1] has been the de facto industry standard in electronic circuit simulation and analysis. However, the cost of simulating large digital circuits is often prohibitive using the conventional modified nodal analysis. A wide range of acceleration methods have been employed (such as event driven, selective trace, table lookup, etc.) at different levels (switch, gate, behavioral, etc.). Orders of magnitudes speed-up can be achieved at higher levels of abstraction, but at the expense of accuracy. Although using higher levels of abstraction in circuit simulation can speed up the analysis for a particular design or a particular stage of the design, in many cases it is not sufficient or accurate enough. Moreover, designers often use different levels of abstraction (e.g., transistors, gates, blocks) in the same design session to convey different concepts. It is then desirable to have a single-engine simulator that can handle different algorithms in a consistent manner. The major problem in multi-level simulation is to combine different simulation techniques in a unified data structure, and how to trade accuracy for speed (CPU time). For accurate timing simulation of large digital as well as mixed-signal integrated circuits, the delay of a logic gate, which depends on a number of parameters, must be accurately modeled. One example is the nonlinear dependence of the gate delay on the load capacitance for submicron devices for which the accumulated timing error can be quite large. It is also known that the gate delay depends significantly on the transition time of its input signal as well as which and how many input ports trigger a logic transition. The fanout capacitance of a gate is user-netlist dependent while the input transition time and triggering are run-time dependent, which are difficult to incorporate into a static timing delay model. This paper describes a dynamic delay model to address the above problems with the objective of simulating large digital

in which the intrinsic (unloaded) delay (tdi) and the effective resistance (Reff) of the gate depend on its input transition time (ti) the number of triggered input ports (for multiple-input gate) (N i ) and the loading capacitance (C load ). This dependence is pre-characterized at N loading breakpoints for two extreme input transition times by simulating the corresponding subcircuit of the gate. For multiple-input gates, the delay information is also extracted for single- and all-input triggering. A pair of delay and load values with the above dependencies for each logic gate are stored in the logic gate model. During a transient simulation, the actual fanout of a gate is first extracted from the user netlist. The transition time of the input signal and the number of triggered inputs for each gate are traced at each time step. The actual delay of the gate is determined dynamically (at run time) using linear interpolation/extrapolation based on the stored delay information for the minimum/maximum input transition times and single-/all-input triggering between two neighboring breakpoints of the actual fanout capacitance. In this way, the nonlinear loading effect and the dependence of the input transition time and triggering are fully incorporated. Since the delay information is extracted from the corresponding subcircuit representation, this dynamic delay model provides an accuracy close to that of the circuit level with comparable speed to other common gate-level delay models (such as unit delay or zero delay).

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3. Simulation results and discussion

The above model is tested with the heterostructure fieldeffect transistor (HFET) E/D logic circuits [2] described below. The single-engine mixed-mode simulator runs in three different modes: (i) analog in which each logic gate (U element) is replaced by an X subcircuit call; (ii) digital in which the dynamic delay model (or a unit-delay model) is used; and (iii) mixed in which each logic gate is simulated using the appropriate analog or digital representation based on the quality of its input signal, and the switching between modes happens automatically and dynamically.
U3

Vdd A2

U1

U2

Out

The first test illustrates the effect of the loading capacitance. An inverter loaded with 1, 2, and 3 identical inverters is driven by an ideal voltage pulse (zero input transition time). The circuit is simulated in analog and digital modes (dynamic-delay as well as unit-delay model). Compared with full-circuit (analog mode) simulation, the digital mode speeds up by a factor of 6~7 with reasonable accuracy. With the N-breakpoint dynamic delay model, the accuracy improved by 42% and 61% compared to that of the unit-delay model (using the same simulator) for two and three loads, respectively. The waveforms at node are shown in Fig. 2. The timing errors (calculated at 50% of full voltage swing relative to that of the full-circuit waveform) are summarized in Tab. I. CPU times (for three loads), breaking up into loading the matrix (LOAD), LU decomposition (LU), backward substitution (BACK), output (OUT), and overhead (OVER), are reported in Tab. II. Load 1 2 3 Dynamic-delay 1.5 2.2 2.4 Unit-delay < 1.0 3.8 6.2

In

A1

Vin

U4

(b)

(a)

Fig. 1 (a) Inverter test circuit driven by a square pulse with 1, 2, and 3 loads; (b) subcircuit consists of E/D HFETs.

Tab. I Timing errors (ps) of different delay models relative to full-circuit simulation for the circuit shown in Fig. 1 with different loads.

CPU (sec.)
Full-circuit Dynamic-delay Unit-delay

Full-circuit 3.69 0.47 0.19 0.21 0.08 4.64

1.2 1.0 0.8 0.6 0.4 0.2

Voltage at the Output of U1 (V)
Load = 1

LOAD LU BACK OUT OVER Total

Dynamicdelay 0.12 0.29 0.04 0.12 0.05 0.62

Unit-delay 0.13 0.23 0.08 0.11 0.04 0.59

0.0
1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 50 100 Time (ps) 150 200
Load = 3 Load = 2

Tab. II CPU times of different simulation modes for the circuit shown in Fig. 1 with three loads.

The second example demonstrates the effect of the input transition time in which an analog signal (sine voltage) is propagated through a string of inverters (Fig. 3), which shows the accumulated timing error (compared to full-circuit simulation) at different stages for different delay models. Compared with the unit-delay model, the dynamic delay with input transition time tracing shows a 3639% improvement in accuracy. The waveforms at nodes , , , and are shown in Fig. 4 with different simulation modes as indicated. +
U1 U2 U3

Fig. 2 Voltage waveforms at node of the circuit shown in Fig. 1 with different loads and different simulation modes.

Fig. 3 A string of HFET inverters driven by a sine wave.

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Full-circuit

Dynamic-delay

Unit-delay

Vout (V)

The third example is a three-input NOR gate, which shows the effect of the number of triggered inputs on the timing delay. When the number of triggered inputs is two, the timing error of the dynamic delay model is 3.6 ps while it is 10.8 ps if the input triggering is not incorporated (67% improvement). When the number of triggered inputs is three, the timing error is 3.4 ps for the dynamic delay model as opposed to 11.2 ps without tracing the input triggering, which corresponds to a 70% improvement in accuracy. The waveforms are shown in Fig. 5.

This model allows large digital as well as mixed analog-digital circuits to be simulated more efficiently and accurately.

Full-circuit

Dynamic-delay

Worst-case

1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2

1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 0

Trigger = 1

1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2

1.2

Trigger = 2

V2 (V)

Vout (V)

V3 (V)

0.6 0.4 0.2 0.0 -0.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 0 25 50 Time (ps) 75 100

Vout (V)

1.0 0.8

Trigger = 3

100

200

300

400

Time (ps)

Fig. 5 Voltage waveforms at the output of the NOR gate with different number of triggered inputs.

V4 (V)

References
[1] L. W. Nagel, SPICE2: A Complete Program to Simulate Semiconductor Circuits, Memorandum ERL-M520, University of California, Berkeley, May 1975. [2] X. Zhou and T. Tang, Multi-Level Modelling of GaAs HighSpeed Digital Circuits, The EEE Journal, School of Electrical and Electronic Engineering, Nanyang Technological University, Vol. 7, No. 1, pp. 5864, July 1995. [3] T. Tang and X. Zhou, A Dynamic Delay Model for Mixed Gate/Circuit-Level Simulation of VLSI Circuits, submitted to IEEE Trans. CAD, 1995.

Fig. 4 Voltage waveforms at nodes , , , and of the circuit shown in Fig. 3 with different simulation modes.

4. Conclusion
In conclusion, a dynamic delay model for accurate timing simulation at the gate level with circuit-level accuracy is demonstrated. The model incorporates the nonlinear dependence of the gate delay on the loading capacitance as well as the run-time dependent input transition time and triggering.

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