1/3 Duty General Purpose LCD Driver IC

CT6523

DESCRIPTION
CT6523 is an LCD Driver IC which can drive up to 156 segments. It can be used for frequency display in microprocessor-controlled radio receiver and in other display applications. CT6523 supports both 1/2 bias, 1/3 duty and 1/3 duty, 1/3 bias. Pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages.

FEATURES
Up to 156 Segments Outputs 1/3 Duty - 1/2 Bias and 1/3 Duty - 1/3 Bias Drive Techniques Power Saving Mode and all Segments OFF Function Direct Display of Display Data without using a Decoder RC Oscillation Circuit Power Supply Voltage: 4.5 to 6V LCD Drive Bias Voltage can be provided internally or externally Available in 64 pins, QFP or LQFP

APPLICATIONS
Electronic Dictionary / Translator P.O.S. Caller ID Pager Mini Compo Electronic Equipment with LCD Display

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BLOCK DIAGRAM

COM1 COM2 COM3

SG52

SG5

SG4

SG3

SG2

SG1

VDD1 VDD2

COMMON DRIVER

SEGMENT DRIVER & LATCH

/INH

OSC

CLOCK GENERATOR

SHIFT REGISTER

DI CLK CE

ADDRESS DETECTOR

VDD VSS

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INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:

INPUT PIN: CLK, CE, DI

VDD

VSS

OUTPUT PIN: COM1 TO COM3, SG1 TO SG52

VDD VDD1

VSS

VDD2

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PIN CONFIGURATION
SG47 SG46 SG45 SG42 SG48 SG44 SG43 SG41 SG40 SG39 SG38 SG37 SG36 SG35 SG34 34 SG33 33 32 31 30 29 28 27 26

47

40

38

46

43

41

39

48

45

44

42

SG49 SG50 SG51 SG52 COM1 COM2 COM3 VDD /INH VDD1 VDD2 VSS OSC CE CLK DI

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

37

36

35

SG32 SG31 SG30 SG29 SG28 SG27 SG26 SG25 SG24 SG23 SG22 SG21 SG20 SG19 SG18 SG17

CT6523

25 24 23 22 21 20 19 18 17

SG1

SG3

SG4

SG5

SG7

SG8

SG9

SG10

SG11

SG12

SG13

SG14

SG15

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SG16

SG2

SG6

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PIN DESCRIPTION
Pin Name SG1 to SG52 COM1 to COM3 VDD /INH VDD1 VDD2 VSS OSC CE CLK DI I/O O I I I I/O I I I Description Segment Output Pins Common Driver Output Pins Power Supply Display OFF Control Input Pin When this pin is Low, the display is forcibly turned off. (SG1~SG52, COM1~COM3 are set to Low) (see Note) Used for the 2/3 Bias Voltage when the Bias Voltages are provided externally. Connect to VDD2 when 1/2 bias is used. Used for 1/3 Bias Voltage when the Bias Voltage are provided externally. Connect to VDD1 when 1/2 Bias is used. Ground Pin Oscillation Input/Output Pin Chip Enable Pin Synchronization Clock Transfer Data Pin Pin No. 1~52 53~55 56 57 58 59 60 61 62 63 64

Note: 1. When /INH = Low: Serial data transfers can be performed when the display is forcibly off.

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FUNCTION DESCRIPTION
SERIAL DATA TRANSFER
CONDITION 1: CLK IS TERMINATED AT THE LOW LEVEL

CONDITION 2: CLK IS TERMINATED AT THE HIGH LEVEL

Note: 1. Address: 41H 2. D1 to D156 = Display Data When D1 to D156 are set to 1, Display is turned ON. When D1 to D156 are set to 0, Display is turned OFF. 3. DR = 1/2 Bias Drive or 1/3 Bias Drive Switching Control Data 4. SC = Segment ON/OFF Control Data 5. BU = Normal Mode/Power-Saving Control Data 6. x = Not Relevant For example, there are 63 segments that are being used, the 63 bits of display data (D94 to D156) must be sent. Please refer to the diagram below.
8 BITS 1 0 0 0 0 0 1 0 D94 D95 D96 D154 67 BITS D155 D156 DR SC BU X

------------

ADDRESS

------------

Note: x = Not Relevant

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CONTROL DATA
DR: 1/2 BIAS DRIVE OR 1/3 BIAS DRIVE SWITCHING CONTROL DATA.
DR is the 1/2 bias drive or 1/3 bias drive switching control data bit. It is used to select either 1/2 bias drive or 1/3 bias drive. When this pin is set to 0 the 1/2 bias drive is selected. When this pin is set to 1, the 1/3 bias drive is selected. Please refer to the table below for the DR settings. DR 0 1 Drive Type 1/2 Bias Drive 1/3 Bias Drive

SC: SEGMENT ON/OFF CONTROL DATA

SC is the Segment ON/OFF Control Data Bit. It is used to select the state of the segments. If the SC is set to 0, then the Segment Display are turned ON, however, if the SC is set to 1, the Display State is OFF. Please refer to the table below. SC 0 1 Display State ON OFF

It should be noted that when the segments are turned off via the SC setting (SC=1), the segments are turned off the outputting of the segment OFF waveforms from the Segment Output Pins.

BU: NORMAL MODE/POWER SAVING MODE CONTROL DATA BIT

BU is the Normal Mode/Power Saving Mode Control Data Bit. It is used to select either the Normal Mode or the Power saving Mode. When the BU is set to 0, the Normal Mode is enabled, however, if the BU is set to 1, the Power saving Mode is active. It should be noted that under the Power Saving Mode, the Oscillation (OSC Pin) is stopped and the Common and Segment Pins output Vss levels. BU 0 1 Mode Selected Normal Mode Power Saving Mode

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/INH AND DISPLAY CONTROL

When power is first applied, the CT6523 internal data are not defined (D1 to D156, DR, SC and BU). The display is turned off (SG1 to SG52, COM1 to COM3 are all set to Low Level) by setting the /INH pin to Low at the same time the power is applied. (Please note that when the /INH Pin is set to LOW, the OSC Pin is not active.) As a result of this, irrelevant display at the time of the power ON can be eliminated if not prevented by transferring the serial data from the controller while the display is OFF and by setting the /INH pin after the transfer is completed. Please refer to figures below.
V DD

VDD
/I N H
t1 t2 V IL V IL

R /INH C
D EF IN E D

CE

D IS PL A Y & C ON TR O L D ATA TR A N SF ER

I N T ER N AL D ATA

U N D EF IN E D

where: 1. t1 is determined by the value of C and R. 2. t2=10s (minimum) 3. Vcc=4.5V to 6.0V

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DISPLAY DATA TO SEGMENT OUTPUT PIN CORRESPONDENCE

Segment Output Pin SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 SG39 SG40 SG41 SG42
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COM3 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124

COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125

COM1 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126
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Segment Output Pin SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 SG52 COM3 D127 D130 D133 D136 D139 D142 D145 D148 D151 D154 COM2 D128 D131 D134 D137 D140 D143 D146 D149 D152 D155 COM1 D129 D132 D135 D138 D141 D144 D147 D150 D153 D156

CT6523

For clarity, the table below gives an example of the segment output states for the SG11 Output Pins D31 0 0 0 0 1 1 1 1 Display Data D32 0 0 1 1 0 0 1 1 D33 0 1 0 1 0 1 0 1 Segment Output Pin (SG11) State Correspondence COM1 to COM3=OFF COM1=ON COM2=ON COM1=COM2=ON COM3=ON COM1=COM3=ON COM2=COM3=ON COM1 to COM3=ON

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1/3 DUTY, 1/2 BIAS DRIVE WAVEFORMS

The 1/3 duty, 1/2 bias waveforms are shown below.

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1/3 DUTY, 1/3 BIAS DRIVE WAVEFORMS

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ABSOLUTE MAXIMUM RATING

(Unless otherwise stated, Ta=25, Vss=0V) Parameter Symbol Maximum Supply Voltage VDDmax VIN1 Input Voltage VIN2 Output Voltage VOUT IOUT1 Output Current IOUT2 Allowable Power Dissipation Pd max Operating Temperature Topr Storage Temperature Tstg Condition Ratings VDD -0.3 to +6.5 CE, CLK, DI , /INH -0.3 to VDD+0.3 OSC -0.3 to VDD+0.3 OSC -0.3 to VDD+0.3 SG1 to SG52 300 COM1 to COM3 3 Ta=85 200 -40 to +85 -65 to +150 Unit V V V V uA mA mW

ALLOWABLE OPERATING RANGE

(Unless otherwise stated, Ta=25, Vss=0V) Parameter Symbol Conditions Supply Voltage VDD VDD Input Voltage VDD1 VDD1 Input Voltage VDD2 VDD2 High Level Input Voltage VIH CE, CLK, DI, /INH Low Level Input Voltage VIL CE, CLK, DI, /INH Recommended External Rosc OSC Resistance Recommended External Cosc OSC Capacitance Guaranteed Oscillator fosc OSC Range Data Setup Time * tds CLK, DI: Figure 2 Data Hold Time * tdh CLK, DI: Figure 2 CE Wait Time * tcp CE, CLK: Figure 2 CE Setup Time * tcs CE, CLK: Figure 2 CE Hold Time * tch CE, CLK: Figure 2 High Level Clock Pulse toH CLK: Figure 2 Width * Low Level Clock Pulse toL CLK: Figure 2 Width * Rise Time * tr CE, CLK, DI: Figure 2 Fall Time* tf CE, CLK, DI: Figure 2 /INH, Switching Time t2 /INH, CE: Figure 1 Note: 1. * = Refer to the diagrams below. Min. 4.5 4.0 0 19 100 100 100 100 100 100 100 10 Typ. 2/3VDD 1/3VDD 47 1000 38 100 100 Max. 6.0 VDD VDD VDD 0.7 76 Unit V V V V V K pF KHz ns ns ns ns ns ns ns ns ns s

CONDITION 1: CLK IS TERMINATED AT LOW LEVEL

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1/3 Duty General Purpose LCD Driver IC

CE
to H to L V IH

CT6523

VI H

C LK

VI H VI L
50 %

VI H tr tf VI H VI L td h VI L tc p tc s

VI H tc H

DI

VI H VI L td s

CONDITION 2: WHEN CLK IS TERMINATED AT HIGH LEVEL

CE
to L to H V IH V IH V IL tcp tcs tcH V IH 50% V IL V IH V IL

CLK

tr
V IH V IL td s

tf
V IH V IL td h

DI

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ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, Ta=25, VSS=0V) Parameter Symbol Conditions CE, CLK, DI, High level input current IIH /INH, VI=6V CE, CLK, DI, Low level input current IIL /INH, VI=0V OSC Oscillator frequency fosc Rosc=47K CE, CLK, DI, Hysteresis width VH /INH,VDD=5V High level output SG1 to SG52 VOH1 voltage Io=-20A Low level output SG1 to SG52 VOL1 voltage Io=20A High level output COM1 to COM3 VOH2 voltage Io=-100A Low level output COM1 to COM3 VOL2 voltage Io=100A 1/2 Bias, COM1 to COM3 VMID1 Io=100A 1/3 Bias COM1 to COM3 VMID2 Io=100A 1/3 Bias Intermediate level COM1 to COM3 VMID3 voltage * Io=100A 1/3 Bias SG1 to SG52 VMID4 Io=20A 1/3 Bias SG1 to SG52 VMID5 Io=20A IDD1 Power Saving Mode f=38KHz, 1/2 Bias IDD2 VDD=5V f=38KHz, 1/3 Bias IDD3 Supply current VDD=5V f=38KHz, 1/2Bias IDD2 VDD=6V f=38KHz, 1/3 Bias IDD3 VDD=6V Min. -5 0.3 VDD-1.0 VDD-1.0 1/2VDD-1.0 2/3VDD -1.0 1/3VDD-1.0 2/3VDD-1.0 1/3VDD-1.0 Typ. 38 400 300 650 580 Max. 5 1.0 1.0 1/2VDD+1.0 2/3VDD +1.0 1/3VDD+1.0 2/3VDD+1.0 1/3VDD+1.0 5 800 600 1300 1200 Unit A A KHz V V V V V V V V V V A A A A A

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Note: 1. * = Except the Bias Voltage Generation Divider Resistors that are built-into the VDD1 and VDD2 (Please refer to the figures below)
VDD

VDD1 VDD2

TO COMMON & SEGMENT DRIVERS

EXCEPT THESE RESISTORS

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APPLICATION CIRCUITS
1/3 BIAS (FOR SMALL DISPLAY PANEL)

SG41 41

SG44 44

SG42 42

SG34 34

SG48 48

SG47 47

SG46 46

SG45 45

SG43 43

SG40 40

SG39 39

SG38 38

SG37 37

SG36 36

SG35 35

49 SG49 50 SG50 51 SG51 52 SG52 53 COM1 54 COM2 55 COM3

SG33 33 SG32 32 SG31 31 SG30 30 SG29 29 SG28 28 SG27 27 SG26 26

VDD R1 20p 0.1 F Open

56 VDD 57 /INH 58 VDD1 59 VDD2 60 VSS 61 OSC 62 CE

CT7623

SG25 25 SG24 24 SG23 23 SG22 22 SG21 21 SG20 20 SG19 19 SG18 18 SG17 17

1000pF

47K

MCU

63 CLK 64 DI SG10 SG12 SG13 SG14 SG15 SG16 SG11 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9

Note: 1. 39K R1 10K

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1/3 BIAS (FOR NORMAL SIZE DISPLAY PANELS)

SG41 41

SG44 44

SG42 42

SG34 34

SG48 48

SG47 47

SG46 46

SG45 45

SG43 43

SG40 40

SG39 39

SG38 38

SG37 37

SG36 36

SG35 35

49 SG49 50 SG50 51 SG51 52 SG52 53 COM1 54 COM2 55 COM3

SG33 33 SG32 32 SG31 31 SG30 30 SG29 29 SG28 28 SG27 27 SG26 26

VDD R1 20p 0.1 F C

56 VDD 57 /INH 58 VDD1

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SG25 25 SG24 24 SG23 23 SG22 22 SG21 21 SG20 20 SG19 19 SG18 18 SG17 17

59 VDD2 60 VSS 61 OSC 62 CE

1000pF

47K

MCU

63 CLK 64 DI SG10 SG12 SG13 SG14 SG15 SG16 SG11 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9

Notes: 1. 39K R1 10K 2. C 0.047F

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1/3 BIAS (FOR LARGE PANELS)

SG41 41

SG48 48

SG47 47

SG46 46

SG45 45

SG44 44

SG43 43

SG42 42

SG40 40

SG39 39

SG38 38

SG37 37

SG36 36

SG35 35

SG34 34

49 SG49 50 SG50 51 SG51 52 SG52 53 COM1 54 COM2 55 COM3

SG33 33 SG32 32 SG31 31 SG30 30 SG29 29 SG28 28 SG27 27 SG26 26

VDD R1 20p 0.1 F C R R C R

56 VDD 57 /INH 58 VDD1 59 VDD2 60 VSS 61 OSC 62 CE

CT7623

SG25 25 SG24 24 SG23 23 SG22 22 SG21 21 SG20 20 SG19 19 SG18 18 SG17 17

1000pF

47K

MCU

63 CLK 64 DI SG10 SG12 SG13 SG14 SG15 SG16 SG11 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9

Notes: 1. 39K R1 10K 2. C 0.047F 3. 10K R 1K

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ORDER INFORMATION
Valid Part Number CT6523 (L) CT6523LQ (L) Package Type 64 Pins, LQFP(14x14mm) 64 Pins, LQFP(10x10mm) Top Code CT6523 CT6523LQ

Notes: 1. (L), (C) or (S) = Lead Free. 2. The Lead Free mark is put in front of the date code. 3. F/T is only open short testing

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PACKAGE INFORMATION
64 PINS, LQFP PACKAGE (BODY SIZE: 14MM X 14MM, PITCH: 0.80MM)

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64 PINS, LQFP PACKAGE (BODY SIZE: 10MM X 10MM, PITCH:0.50MM, THK BODY: 1.40MM)
D D1 -DA A2

A1

E1

-A-

-B-

L1 e
1

C SEATING PLANE

ccc

2
R1 -HR2 GAUGE PLANE

0.25mm

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Symbol c L L1 A A1 A2 b D D1 E E1 e R1 R2 S 1 2 3 ccc Min. 0.09 0.45 0.05 1.35 0.17 Nom. 0.60 1.00 REF. 1.40 0.22 12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.50 BASIC 3.5 12 12 0.08 Max. 0.20 0.75 1.60 0.15 1.45 0.27

CT6523

0.08 0.08 0.20 0 0 11 11

0.20 7 13 13

Notes: 1. All dimensioning and tolerancing conform to ASME Y14.5M - 1994. 2. Datums A-B and D to be determined at datum plane H. 3. Dimensions D1 and E1 do not include mold prortrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 do include mold mismatch and are determined at the datum plane H. 4. Controlling Dimension: MILLIMETERS. 5. Dimension b does not include dambar protrusion. The dambar protrusion (s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. minimum space between protrusion and as adjacent lead is 0.07 mm for 0.4mm and 0.5mm pitch packages. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7. Refer to JEDEC MS-026 Variation BCD. JEDEC is the TRADEMARK OF JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.

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