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frequency_counter.vhd
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-- Reference design - Frequency counter for Spartan-3E Starter Kit (Rev.C).
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-- Ken Chapman - Xilinx Ltd - 7th March 2006
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-- *** This design contains an evaluation test feature of the DCM. ****
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-- *** Before this design can be processed a special environment
****
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-- *** needs to be set or the 'dcm_fixed_osc' module removed.
****
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-- *** Please read the notes provided in 'dcm_fixed_osc.vhd' for
****
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-- *** details of this special requirement.
****
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-- Provides a frequency counter with resolution of 1Hz up to a maximum frequency of
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-- approximately 200MHz (limited by maximum clock rate of design).
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-- The 50MHz on board oscillator is used to provide a 1 second time base and therefore
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-- defines the accuracy of the measurement. If the frequency of the 50MHz oscillator can
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-- be determined using a calibrated frequency counter or frequency generator then this
design
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-- could be tuned to match the particular board.
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-- Slide switches SW0, SW1, SW2 and SW3 allow selection of the input signal or one of thr
test
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-- signals. Only one switch should be selected and the LCD display will guide and confirm
the
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-- selection process.
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-- SW0 selects SMA connector (J17) as the input signal to be analysed.
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-- SW1 selects the 50MHz oscillator as a test signal and must yield a perfect result sinc
it is
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-also the definition of the measurement time base..
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-- SW2 selects a signal of approximately 145MHz which is generated by one of the DCMs
operating
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-in a special test oscillator mode.
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-- SW3 selects a ring oscillator implement using a combinatorial loop in the CLB fabric.
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-- LED indicate measurements in progress (1 second alternate flashing of 4 LEDs).
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-- PicoBlaze performs calculations and conversions as well as driving the LCD display.
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-----------------------------------------------------------------------------------36
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-- NOTICE:
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-- Copyright Xilinx, Inc. 2006.
This code may be contain portions patented by other
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-- third parties. By providing this core as one possible implementation of a standard,
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-- Xilinx is making no representation that the provided implementation of this standard
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-- is free from any claims of infringement by any third party. Xilinx expressly
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-- disclaims any warranty with respect to the adequacy of the implementation, including
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-- but not limited to any warranty or representation that the implementation is free
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-- from claims of any third party. Furthermore, Xilinx is providing this core as a
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-- courtesy to you and suggests that you contact all third parties to obtain the
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-- necessary rights to use this implementation.
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-----------------------------------------------------------------------------------50
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-- Library declarations
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-- Standard IEEE libraries
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;

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frequency_counter.vhd
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- The Unisim Library is used to define Xilinx primitives. It is also used during
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-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
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library unisim;
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use unisim.vcomponents.all;
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-----------------------------------------------------------------------------------67
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entity frequency_counter is
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Port (
led : out std_logic_vector(7 downto 0);
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sw : in std_logic_vector(3 downto 0);
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strataflash_oe : out std_logic;
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strataflash_ce : out std_logic;
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strataflash_we : out std_logic;
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lcd_d : inout std_logic_vector(7 downto 4);
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lcd_rs : out std_logic;
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lcd_rw : out std_logic;
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lcd_e : out std_logic;
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sma_clk : in std_logic;
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clk_50mhz : in std_logic);
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end frequency_counter;
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-----------------------------------------------------------------------------------84
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-- Start of test architecture
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architecture Behavioral of frequency_counter is
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-----------------------------------------------------------------------------------90
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-- declaration of KCPSM3
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component kcpsm3
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Port (
address : out std_logic_vector(9 downto 0);
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instruction : in std_logic_vector(17 downto 0);
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port_id : out std_logic_vector(7 downto 0);
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write_strobe : out std_logic;
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out_port : out std_logic_vector(7 downto 0);
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read_strobe : out std_logic;
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in_port : in std_logic_vector(7 downto 0);
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interrupt : in std_logic;
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interrupt_ack : out std_logic;
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reset : in std_logic;
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clk : in std_logic);
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end component;
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-- declaration of program ROM used by data capture processor
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component fc_ctrl
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Port (
address : in std_logic_vector(9 downto 0);
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instruction : out std_logic_vector(17 downto 0);
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proc_reset : out std_logic;
--JTAG Loader version
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clk : in std_logic);
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end component;
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frequency_counter.vhd
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-----------------------------------------------------------------------------------123
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-- Signals used to select and provide sources to be analysed
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signal source_control
: std_logic_vector(7 downto 0);
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signal dcm_oscillator
: std_logic;
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signal ring_oscillator
: std_logic;
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signal freq_for_measurement
: std_logic;
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signal test_clk
: std_logic;
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-- Signals used by clock cycle counters and controls
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signal ab_switch_delay
: std_logic_vector (3 downto 0);
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signal a_count_ce
: std_logic;
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signal a_count_rst
: std_logic;
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signal a_count
: std_logic_vector (31 downto 0);
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signal b_count_ce
: std_logic;
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signal b_count_rst
: std_logic;
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signal b_count
: std_logic_vector (31 downto 0);
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-- Signals for 1 second interrupt generation and counter switching
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signal one_second_count
: integer range 0 to 49999999 :=0;
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signal one_second_pulse
: std_logic;
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signal ab_switch
: std_logic;
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signal interrupt_delay
: std_logic_vector (99 downto 0);
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-- Signals used to connect KCPSM3 to program ROM and I/O logic
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signal address
: std_logic_vector(9 downto 0);
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signal instruction
: std_logic_vector(17 downto 0);
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signal port_id
: std_logic_vector(7 downto 0);
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signal out_port
: std_logic_vector(7 downto 0);
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signal in_port
: std_logic_vector(7 downto 0);
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signal write_strobe
: std_logic;
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signal read_strobe
: std_logic;
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signal interrupt
: std_logic;
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signal interrupt_ack : std_logic;
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signal reset
: std_logic;
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-- Signals for LCD operation
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-- Tri-state output requires internal signals
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-- 'lcd_drive' is used to differentiate between LCD and StrataFLASH communications
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-- which share the same data bits.
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signal
lcd_rw_control : std_logic;
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signal lcd_output_data : std_logic_vector(7 downto 4);
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signal
lcd_drive : std_logic;
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--

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frequency_counter.vhd
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------------------------------------------------------------------------------------------------------------------------------------------------------------------182
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-- Start of circuit description
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begin
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----------------------------------------------------------------------------------------------------------------------------189
-- Disable unused components
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----------------------------------------------------------------------------------------------------------------------------191
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--StrataFLASH must be disabled to prevent it conflicting with the LCD display
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strataflash_oe <= '1';
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strataflash_ce <= '1';
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strataflash_we <= '1';
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----------------------------------------------------------------------------------------------------------------------------200
-- Select and Buffer signal to be analysed
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----------------------------------------------------------------------------------------------------------------------------202
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-- Source selection multiplexer (must be combinatorial)
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freq_for_measurement <= sma_clk when (source_control(1 downto 0)="00")
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else clk_50mhz when (source_control(1 downto 0)="01")
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else dcm_oscillator when (source_control(1 downto 0)="10")
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else ring_oscillator;
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-- Global buffer on selected source
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buffer_clkin: BUFG
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port map( O => test_clk,
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I => freq_for_measurement);
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----------------------------------------------------------------------------------------------------------------------------228
-- Frequency Counters

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frequency_counter.vhd
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-- This is formed of two simple 32-bit binary counters such that one can be counting
whilst the
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-- other is being read and reset. Great care is taken to ensure the switch over between
the two
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-- counters is clean and that no clock cycles are missed or glitches generated.
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-- An asynchronous reset is provided and will be controlled by PicoBlaze using a long
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-- pulse when the counter is disabled. Hence there is no special synchronisation on thi
control.
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----------------------------------------------------------------------------------------------------------------------------238
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counter_switch_control: process(test_clk)
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begin
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if test_clk'event and test_clk='1' then
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-- Four stage register to ensure synhchronisation of control between clock domains
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ab_switch_delay <= ab_switch_delay(2 downto 0) & ab_switch;
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-- Separate enables form switch between counters when control is consistantly high
low.
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case ab_switch_delay(3 downto 1) is
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when "000" => a_count_ce <= '1';
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b_count_ce <= '0';
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when "111" => a_count_ce <= '0';
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b_count_ce <= '1';
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when others => a_count_ce <= a_count_ce;
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b_count_ce <= b_count_ce;
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end case;
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end if;
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end process counter_switch_control;
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-- 32-bit counters
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test_counter_a: process(test_clk, a_count_rst )
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begin
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if a_count_rst='1' then
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a_count <= X"00000000";
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elsif test_clk'event and test_clk='1' then
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if a_count_ce='1' then
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a_count <= a_count + 1;
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else
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a_count <= a_count;
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end if;
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end if;
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end process test_counter_a;
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test_counter_b: process(test_clk, b_count_rst )
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begin
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if b_count_rst='1' then
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b_count <= X"00000000";

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frequency_counter.vhd
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elsif test_clk'event and test_clk='1' then
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if b_count_ce='1' then
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b_count <= b_count + 1;
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else
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b_count <= b_count;
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end if;
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end if;
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end process test_counter_b;
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----------------------------------------------------------------------------------------------------------------------------296
-- One Second Timer and Circuit Control
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-- Using the normal 50MHz clock source, this circuit generates a 1 second timer which i
used to
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-- switch the enable from one counter to the other.
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-- A short delay is then inserted to ensure that the switch has taken place before
interrupting the
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-- PicoBlaze processor. This ensures that the counters are switched and stable for
reading etc.
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-- Note: This could cause an issue when very low frequency signals are being measured.
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----------------------------------------------------------------------------------------------------------------------------306
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one_second_logic: process(clk_50mhz)
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begin
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if clk_50mhz'event and clk_50mhz='1' then
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if one_second_count=49999999 then
--divide by 50,000,000 is 1s
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one_second_count <= 0;
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one_second_pulse <= '1';
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else
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one_second_count <= one_second_count + 1;
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one_second_pulse <= '0';
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end if;
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-- delay of 100 clock cycles before generating interrupt
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interrupt_delay <= interrupt_delay(98 downto 0) & one_second_pulse;
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-- processor interrupt waits for an acknowledgement
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if interrupt_ack='1' then
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interrupt <= '0';
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elsif interrupt_delay(99) ='1' then
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interrupt <= '1';
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else
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interrupt <= interrupt;
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end if;
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-- counter selection switch toggles each second
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if one_second_pulse='1' then
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ab_switch <= not ab_switch;
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end if;
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end if;
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frequency_counter.vhd
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end process one_second_logic;
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----------------------------------------------------------------------------------------------------------------------------342
-- KCPSM3 and the program memory used for capturing data from the counters
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----------------------------------------------------------------------------------------------------------------------------344
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processor: kcpsm3
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port map(
address => address,
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instruction => instruction,
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port_id => port_id,
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write_strobe => write_strobe,
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out_port => out_port,
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read_strobe => read_strobe,
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in_port => in_port,
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interrupt => interrupt,
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interrupt_ack => interrupt_ack,
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reset => reset,
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clk => clk_50mhz);
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program_rom: fc_ctrl
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port map(
address => address,
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instruction => instruction,
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proc_reset => reset,
--JTAG Loader version
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clk => clk_50mhz);
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--reset <= '0'; --When using normal version
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----------------------------------------------------------------------------------------------------------------------------368
-- Capture processor input ports
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----------------------------------------------------------------------------------------------------------------------------370
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-- The inputs are connected via a pipelined multiplexer
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input_ports: process(clk_50mhz)
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begin
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if clk_50mhz'event and clk_50mhz='1' then
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case port_id(7 downto 4) is
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-- read A-counter for addresses 00, 10, 20 and 30 hex
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when "0000" =>
in_port <= a_count(7 downto 0);
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when "0001" =>
in_port <= a_count(15 downto 8);
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when "0010" =>
in_port <= a_count(23 downto 16);
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when "0011" =>
in_port <= a_count(31 downto 24);
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-- read B-counter for addresses 40, 50, 60 and 70 hex
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when "0100" =>
in_port <= b_count(7 downto 0);
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when "0101" =>
in_port <= b_count(15 downto 8);
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when "0110" =>
in_port <= b_count(23 downto 16);

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frequency_counter.vhd
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when "0111" =>
in_port <= b_count(31 downto 24);
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-- read slide switches and counter circuit status at address 80 hex
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when "1000" =>
in_port <= "000" & ab_switch & sw;
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-- read LCD data at address 90 hex
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when "1001" =>
in_port <= lcd_d & "0000";
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-- Don't care used to ensure minimum logic
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when others =>
in_port <= "XXXXXXXX";
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end case;
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end if;
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end process input_ports;
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----------------------------------------------------------------------------------------------------------------------------411
-- Capture processor output ports
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----------------------------------------------------------------------------------------------------------------------------413
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output_ports: process(clk_50mhz)
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begin
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if clk_50mhz'event and clk_50mhz='1' then
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if write_strobe='1' then
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-- LED register at address 01 hex
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if port_id(0)='1' then
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led <= out_port;
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end if;
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-- Counter reset controls at address 02 hex
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if port_id(1)='1' then
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a_count_rst <= out_port(0);
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b_count_rst <= out_port(1);
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end if;
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-- LCD data output and controls at address 04 hex.
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if port_id(2)='1' then
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lcd_output_data <= out_port(7 downto 4);
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lcd_drive <= out_port(3);
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lcd_rs <= out_port(2);
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lcd_rw_control <= out_port(1);
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lcd_e <= out_port(0);
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end if;
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-- Source selection and control at address 08 hex.
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if port_id(3)='1' then
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source_control <= out_port;
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end if;
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frequency_counter.vhd
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end if;
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end if;
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end process output_ports;
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----------------------------------------------------------------------------------------------------------------------------456
-- LCD interface
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----------------------------------------------------------------------------------------------------------------------------458
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-- The 4-bit data port is bidirectional.
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-- lcd_rw is '1' for read and '0' for write
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-- lcd_drive is like a master enable signal which prevents either the
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-- FPGA outputs or the LCD display driving the data lines.
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--Control of read and write signal
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lcd_rw <= lcd_rw_control and lcd_drive;
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--use read/write control to enable output buffers.
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lcd_d <= lcd_output_data when (lcd_rw_control='0' and lcd_drive='1') else "ZZZZ";
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----------------------------------------------------------------------------------------------------------------------------471
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------------------------------------------------------------------------------------------------------------------------------474
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end Behavioral;
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------------------------------------------------------------------------------------------------------------------------------478
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-- END OF FILE frequency_counter.vhd
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------------------------------------------------------------------------------------------------------------------------------482
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