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Ulinx_MB_XC3S250E

Sparatn3E
XC3S250E-PQ208
3S250E

2007.Jan.15 .V1.0

Ulinx Corp.

Ulinx

2007/2/25

Ulinx_MB_XC3S250E

UBD-Spartan3E-ST3EFPGA
.
.

Ulin_MB_XC3S250E , HUMAN_IO,
Ulinx_MB_XC3S250E_PQ208,, 1-1 .

Ulinx

2007/2/25

Ulinx_MB_XC3S250E

: Ulinx_MB_XC3S250E_PQ208
Ulinx_MB_XC3S250E_PQ208 FPGA :

25 Xilinx Spartan-3E XC3S250E FPGA PQFP 208


(XC3S250E-4-PQ208)
. 12 18K-bit Block RAMs ( 216K bits)
. 12 18x18
. 4 Digital Clock Managers (DCMs)
. 158
RS-232
PROM XCF02S-VO20
40MHz .
Socket
92 User IO, Human IO,.
8 DIP switch
8 LED
8
( +5V/ 3A )
. ( 1.2 V , 2.5 V , 3.3 V 1.8V)
JTAG

Human_IO :

Ulinx

LCD (128 x 64 Pixels)


( 16 x 2 Text Mode )
16 (4 x 4 , 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F ).
16 LED (8 LED,8 LED)
4 .
4 DIP Switch
8 .
VGA .
PS2 .
Rotary Switch .( 0,1,2,3,4,5,6,7,8,9)
4 DAC (LTC2624)
2 ADC (ADC0832)
IIC (24C02).

2007/2/25

Ulinx_MB_XC3S250E

Ulinx

2007/2/25

Ulinx_MB_XC3S250E

: Ulinx_MB_XC3S250E_PQ208
Ulinx_MB_XC3S250E_PQ208 MB_XC3S250E ,,FPGA,LED
, J1,J2 Human_IO , MB_XC3S250E
.

2-1. .
J8 5 V ,,, J8
:S10 , S10 ,;S10 ,.
Ulinx_MB_XC3S250E ,+5V +3.3V,+2.5V,+1.8V,+1.2V
,+1.8V ,+3.3V,+2.5V,+1.2V Ulinx_MB_XC3S250E
, D1,D2,D3,D4 LED .
D1: 1.2V
D2: 2.5V
D3: 3.3V
D4: 1.8V

; D1
; D2
; D3
; D4

LED
LED
LED
LED

,+5V , J4 .
J4 Connector
Pin
Pin Name
Signal
6
Ground

5
1.2V
1.2V
4
1.8V
1.8V
3
2.5V
2.5V
2
3.3V
3.3V
1
5V
5V

Ulinx

Comment

2007/2/25

Ulinx_MB_XC3S250E

2-2. RS232
RS232 Ulinx_MB_XC3S250E PC
, P2 RS232 , DB9 , 1 1 P2
PC .
NET
NET

"RS232_TX" LOC = "P45" ;


"RS232_RX" LOC = "P71" ;
MAX3221

13

Ulinx

Spartan 3E

11

P45

P71

2007/2/25

Ulinx_MB_XC3S250E

2-3. CLOCK
CLOCK , GCLK1 40MHz ,
FPGA Pin-80, GCLK2 ,
FPGA Pin-183.
NET
NET

Ulinx

"GCLK1"
"GCLK2"

LOC = "P80" ;
LOC = "P183" ;

2007/2/25

Ulinx_MB_XC3S250E

2-4. PUSH_BUTTON DIP_SWITCH


8 PUSH_BUTTON DIP_SWICTH,,
PUSH_BUTTON ,0;1
DIP_SWITCH [ON],0;[OFF].
NET "DIP_SWITCH<0>" LOC = "P159"
NET "DIP_SWITCH<1>" LOC = "P169"
NET "DIP_SWITCH<2>" LOC = "P194"
Ulinx

;
;
;

2007/2/25

Ulinx_MB_XC3S250E

NET "DIP_SWITCH<3>"
NET "DIP_SWITCH<4>"
NET "DIP_SWITCH<5>"
NET "DIP_SWITCH<6>"
NET "DIP_SWITCH<7>"

LOC = "P204" ;
LOC = "P54" ;
LOC = "P91" ;
LOC = "P101" ;
LOC = "P58" ;

NET "PUSH_BUTTON<7>"
NET "PUSH_BUTTON<6>"
NET "PUSH_BUTTON<5>"
NET "PUSH_BUTTON<4>"
NET "PUSH_BUTTON<3>"
NET "PUSH_BUTTON<2>"
NET "PUSH_BUTTON<1>"
NET "PUSH_BUTTON<0>"

LOC = "P154"
LOC = "P148"
LOC = "P142"
LOC = "P136"
LOC = "P130"
LOC = "P124"
LOC = "P118"
LOC = "P110"

FPGA PIN
P110
P118
P124
P130
P136
P142
P148
P154

SYMBOL
S2
S3
S4
S5
S6
S7
S8
S9

LABEL NAME
USER_SW8
USER_SW7
USER_SW6
USER_SW5
USER_SW4
USER_SW3
USER_SW2
USER_SW1

P159
P169
P194
P204
P54
P91
P101
P58

S1-1
S1-2
S1-3
S1-4
S1-5
S1-6
S1-7
S1-8

USER_DIP1
USER_DIP2
USER_DIP3
USER_DIP4
USER_DIP5
USER_DIP6
USER_DIP7
USER_DIP8

Ulinx

;
;
;
;
;
;
;
;

LOGIC
,0
,0
,0
,0
,0
,0
,0
,0

COMMENT

2007/2/25

Ulinx_MB_XC3S250E

2-5.

LED
8 LED LED,1,LED ,
0,LED .

NET "LED<7>"
NET "LED<6>"
NET "LED<5>"
NET "LED<4>"
NET "LED<3>"
NET "LED<2>"
NET "LED<1>"
NET "LED<0>"

FPGA PIN
P65
P62
P63
P60
P61
P55
P98
P76

Ulinx

LOC = "P76"
LOC = "P98"
LOC = "P55"
LOC = "P61"
LOC = "P60"
LOC = "P63"
LOC = "P62"
LOC = "P65"

SYMBOL
D7
D8
D9
D10
D11
D12
D13
D14

;
;
;
;
;
;
;
;

LABEL NAME
USER_LED1
USER_LED2
USER_LED3
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7

10

LOGIC
COMMENT
1D7
1D8
1D9
1D10
1D11
1D12
1D13
1D14

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Ulinx_MB_XC3S250E

2-6. J1 CONNECTOR (A2_CONNECTOR)


J1 46 /, IO ,+3.3V .
Human_IO
FPGA SYMBOL J1 J1 SYMBOL FPGA Human_IO
BOARD
PIN
PIN
BOARD
GND
1 2 +5V
7_SEG_A1
P181 A2_IO1
3 4 A2_IO2
P180
7_SEG_A2
7_SEG_A3
P186 A2_IO3
5 6 A2_IO4
P185
7_SEG_A4
7_SEG_A5
P190 A2_IO5
7 8 A2_IO6
P189
7_SEG_A6
7_SEG_A7
P193 A2_IO7
9 10 A2_IO8
P192
7_SEG_A8
7_SEG_CA
P197 A2_IO9
11 12 A2_IO10
P196
7_SEG_CB
7_SEG_CC
P200 A2_IO11
13 14 A2_IO12
P199
7_SEG_CD
7_SEG_CE
P203 A2_IO13
15 16 A2_IO14
P202
7_SEG_CF
7_SEG_CG
P206 A2_IO15
17 18 A2_IO16
P205
7_SEG_DP
P107 A2_IO17
19 20 A2_IO18
P106
LCD_RST
LCD_CS2
P109 A2_IO19
21 22 A2_IO20
P108
LCD_CS1
LCD_D7
P113 A2_IO21
23 24 A2_IO22
P112
LCD_D6
LCD_D5
P116 A2_IO23
25 26 A2_IO24
P115
LCD_D4
LCD_D3
27 28 A2_IO26
P119
P120 A2_IO25
LCD_D1
LCD_D2
P123 A2_IO27
29 30 A2_IO28
P122
LCD_D0
LCD_E
P127 A2_IO29
31 32 A2_IO30
P126
LCD_RW
LCD_IO
PS2_CLK
P129 A2_IO31
33 34 A2_IO32
P128
PS2_DATA
USER_SW1
P133 A2_IO33
35 36 A2_IO34
P132
USER_SW2
USER_SW3
P135 A2_IO35
37 38 A2_IO36
P134
USER_SW4
P138 A2_IO37
39 40 A2_IO38
P137
USER_DIP1
USER_DIP2
P140 A2_IO39
41 42 A2_IO40
P139
USER_DIP3
USER_DIP4
ROT_IN1
P145 A2_IO41
43 44 A2_IO42
P144
ROT_IN2
ROT_IN3
P147 A2_IO43
45 46 A2_IO44
P146
ROT_IN4
IIC_SCL
P151 A2_IO45
47 48 A2_IO46
P150
IIC_SDA
+2.5V
49 50 +3.3V

Ulinx

11

2007/2/25

Ulinx_MB_XC3S250E

2-7. J2 CONNECTOR(A1_CONNECTOR
J2 46 /, IO ,+3.3V .
Human_IO
FPGA SYMBOL J2 J2 SYMBOL FPGA Human_IO
BOARD
PIN
PIN
BOARD
GND
1 2 +5V
3 4 A1_IO2
P2
A1_IO1
D15( LED)
D16( LED) P3
5 6 A1_IO4
P4
A1_IO3
D13( LED)
D14( LED) P5
7
8
A1_IO6
P8
P9
A1_IO5
D11( LED)
D12( LED)
9 10 A1_IO8
P11
A1_IO7
D9 ( LED)
D10( LED) P12
11 12 A1_IO10
P15
A1_IO9
D7 ( LED)
D8 ( LED) P16
A1_IO11
13 14 A1_IO12
P18
D6 ( LED) P19
D5 ( LED)
15 16 A1_IO14
P22
A1_IO13
D3 ( LED)
D4 ( LED) P23
17 18 A1_IO16
P24
A1_IO15
D1 ( LED)
D2 ( LED) P25
KEY_IN4
P29
A1_IO17
19 20 A1_IO18
P28
KEY_IN3
KEY_IN2
P31
A1_IO19
21 22 A1_IO20
P30
KEY_IN1
KEY_OUT4
P34
A1_IO21
23 24 A1_IO22
P33
KEY_OUT3
KEY_OUT2
P36
A1_IO23
25 26 A1_IO24
P35
KEY_OUT1
EXT_OUT1
P40
A1_IO25
27 28 A1_IO26
P39
EXT_OUT2
EXT_OUT3
P42
A1_IO27
29 30 A1_IO28
P41
EXT_OUT4
EXT_IN1
P48
A1_IO29
31 32 A1_IO30
P47
EXT_IN2
EXT_IN3
P50
A1_IO31
33 34 A1_IO32
P49
EXT_IN4
ADC_CS
P187 A1_IO33
35 36 A1_IO34
P179
ADC_CLK
ADC_DO
P161 A1_IO35
37 38 A1_IO36
P160
ADC_DI
DAC_CS
P163 A1_IO37
39 40 A1_IO38
P162
DAC_CLK
DAC_DI
P165 A1_IO39
41 42 A1_IO40
P164
DAC_DO
VGA_VSYNC P168 A1_IO41
43 44 A1_IO42
P167
VGA_HSYNC
VGA_B
P172 A1_IO43
45 46 A1_IO44
P171
VGA_G
VGA_R
P178 A1_IO45
47 48 A1_IO46
P177
DAC_CLR
+2.5V
49 50 +3.3V

Ulinx

12

2007/2/25

Ulinx_MB_XC3S250E

2-8. FPGA Configuration


FPGA Configuration FPGA, FPGA
2 Download , JTAG, Master Salve .
[]: In_System Programming
JTAG ISE Impact, Download FPGA,
, DB25 , Printer
Port Ulinx_MB_XC3S250E_PQ208 P1, Impact Download.
J6 Connector 4 ,(
Parallel_Cable_III Parallel_Cavle_IV Download , J3 ,
J6 ,).

Ulinx

13

2007/2/25

Ulinx_MB_XC3S250E

[]: Master Slave

, J5 , J5 , JTAG Download , Bit


mcs .

Ulinx

14

2007/2/25

Ulinx_MB_XC3S250E

2-9. FPGA
Ulinx_MB_XC3S250E_PQ208 FPGA, Xilinx Sparatn3E XC3S250E
, PQ208,.
Pin No
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30

Ulinx

Signal Name

I/O

A1_IO2
A1_IO1
A1_IO4
A1_IO3

O
O
O
O

A1_IO6
A1_IO5

O
O

A1_IO8
A1_IO7

O
O

A1_IO10
A1_IO9

O
O

A1_IO12
A1_IO11

O
O
I

A1_IO14
A1_IO13
A1_IO16
A1_IO15

O
O
O
O

A1_IO18
A1_IO17
A1_IO20

I
I
I

FPGA Pin Name


PROG_B
IO_L01P_3
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
VCCAUX
IO_L03P_3
IO_L03N_3
GND
IO_L04P_3
IO_L04N_3
VCCINT
IP
IO_L05P_3
IO_L05N_3
GND
IO_L06P_3
IO_L06N_3
IP/VREF_3
VCCO_3
IO_L07P_3/LHCLK0
IO_L07N_3/LHCLK1
IO_L08P_3/LHCLK2
IO_L08N_3/LHCLK3/IRDY2
IP
GND
IO_L09P_3/LHCLK4/TRDY2
IO_L09N_3/LHCLK5
IO_L10P_3/LHCLK6

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Ulinx_MB_XC3S250E

Pin No

Signal Name

I/O

FPGA Pin Name

P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64

A1_IO19

A1_IO22
A1_IO21
A1_IO24
A1_IO23

O
O
O
O

IO_L10N_3/LHCLK7
IP
IO_L11P_3
IO_L11N_3
IO_L12P_3
IO_L12N_3
GND
VCCO_3
IO_L13P_3
IO_L13N_3
IO_L14P_3
IO_L14N_3
IP
VCCAUX
IO/VREF_3
VCCO_3
IO_L15P_3
IO_L15N_3
IO_L16P_3
IO_L16N_3
IP
GND
GND
IP
IO_L01P_2/CSO_B
IO_L01N_2/INIT_B
IP_L02P_2
IP_L02N_2
VCCO_2
IO_L03P_2/DOUT/BUSY
IO_L03N_2/MOSI/CSI_B
IO_L04P_2
IO_L04N_2
IO_L05P_2

Ulinx

A1_IO26
A1_IO25
A1_IO28
A1_IO27

RS232_TX
A1_IO30
A1_IO29
A1_IO32
A1_IO31

DIP_SWITCH_5
LED3

I
O

DIP_SWITCH_8

LED5
LED4
LED6
LED7

O
O
O
O

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Ulinx_MB_XC3S250E

Pin No

Signal Name

I/O

FPGA Pin Name

P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100

LED8

RS232_RX

LED1

sys_clk_pin

DIP_SWITCH_6

LED2

IO_L05N_2
VCCAUX
VCCINT
IO_L06P_2
IO_L06N_2
GND
IP_L07P_2
IP_L07N_2/VREF_2
VCCO_2
IO_L08P_2/D7/GCLK12
IO_L08N_2/D6/GCLK13
IO/D5
IO_L09P_2/D4/GCLK14
IO_L09N_2/D3/GCLK15
GND
IP_L10P_2/RDWR_B/GCLK0
IP_L10N_2/M2/GCLK1
IO_L11P_2/D2/GCLK2
IO_L11N_2/D1/GCLK3
IO/M1
GND
IO_L12P_2/M0
IO_L12N_2/DIN/D0
VCCO_2
IO_L13P_2
IO_L13N_2
IP
VCCAUX
IO_L14P_2/A23
IO_L14N_2/A22
GND
IO_L15P_2/A21
IO_L15N_2/A20
IO/VREF_2
IO_L16P_2/VS2/A19
IO_L16N_2/VS1/A18

Ulinx

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Ulinx_MB_XC3S250E

Pin No

Signal Name

I/O

FPGA Pin Name

P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136

DIP_SWITCH_7

A2_IO18
A2_IO17
A2_IO20
A2_IO19
Push_Buttons_1( S2 )

O
O
O
O
I

A2_IO22
A2_IO21

O
O

A2_IO24
A2_IO23

O
O

IP
IO_L17P_2/VS0/A17
IO_L17N_2/CCLK
DONE
GND
IO_L01P_1/A16
IO_L01N_1/A15
IO_L02P_1/A14
IO_L02N_1/A13
IP
VCCAUX
IO_L03P_1
IO_L03N_1/VREF_1
VCCO_1
IO_L04P_1
IO_L04N_1
VCCINT
IP
IO_L05P_1/A12
IO_L05N_1/A11
GND
IO_L06P_1
IO_L06N_1/VREF_1
IP
VCCO_1
IO_L07P_1/A10/RHCLK0
IO_L07N_1/A9/RHCLK1
IO_L08P_1/A8/RHCLK2
IO_L08N_1/A7/RHCLK3/TRDY1
IP
GND
IO_L09P_1/A6/RHCLK4/IRDY1
IO_L09N_1/A5/RHCLK5
IO_L10P_1/A4/RHCLK6
IO_L10N_1/A3/RHCLK7
IP/VREF_1

Ulinx

Push_Buttons_2( S3 ) I
A2_IO26
O
A2_IO25
O
A2_IO28
O
A2_IO27
O
Push_Buttons_3( S4 ) I
A2_IO30
A2_IO29
A2_IO32
A2_IO31
Push_Buttons_4( S5 )

O
O
O
O
I

A2_IO34
A2_IO33
A2_IO36
A2_IO35
Push_Buttons_5 ( S6 )

I
I
I
I
I

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Ulinx_MB_XC3S250E

Pin No

Signal Name

I/O

FPGA Pin Name

P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172

A2_IO38
A2_IO37
A2_IO40
A2_IO39

I
I
I
I

IO_L11P_1/A2
IO_L11N_1/A1
IO_L12P_1
IO_L12N_1/A0
GND
IP
VCCO_1
IO_L13P_1
IO_L13N_1
IO_L14P_1
IO_L14N_1
IP
VCCAUX
IO_L15P_1/HDC
IO_L15N_1/LDC0
IO_L16P_1/LDC1
IO_L16N_1/LDC2
IP
TMS
GND
TDO
TCK
IP
IO_L01P_0
IO_L01N_0
IO_L02P_0
IO_L02N_0/VREF_0
IO_L03P_0
IO_L03N_0
VCCAUX
IO_L04P_0
IO_L04N_0/VREF_0
IP
VCCINT
IO_L05P_0
IO_L05N_0

Ulinx

Push_Buttons_6 ( S7 ) I
A2_IO42
A2_IO41
A2_IO44
A2_IO43
Push_Buttons_7( S8 )

I
I
I
I
I

A2_IO46
A2_IO45

Push_Buttons_8( S9 ) I
TMS
TDO
TCK
DIP_Switches_1
A1_IO36
A1_IO35
A1_IO38
A1_IO37
A1_IO40
A1_IO39
A1_IO42
A1_IO41
DIP_Switch_2
A1_IO44
A1_IO43

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Ulinx_MB_XC3S250E

Pin No
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P206
P207
P208

Ulinx

Signal Name

A1_IO46
A1_IO45
A1_IO34
A1_IO2
A2_IO1

I/O

O
O

GCLK2
A2_IO4
A2_IO3
A1_IO33

O
O

A2_IO6
A2_IO5

O
O

A2_IO8
A2_IO7
DIP_Switches_3

O
O
I

A2_IO10
A2_IO9

O
O

A2_IO12
A2_IO11

O
O

A2_IO14
A2_IO13
DIP_Switches_4
A2_IO16
A2_IO15
TDI

O
O
I
O
O

FPGA Pin Name


GND
IP_L06P_0
IP_L06N_0
VCCO_0
IO_L07P_0/GCLK4
IO_L07N_0/GCLK5
IO/VREF_0
IO_L08P_0/GCLK6
IO_L08N_0/GCLK7
GND
IP_L09P_0/GCLK8
IP_L09N_0/GCLK9
IO_L10P_0/GCLK10
IO_L10N_0/GCLK11
IO
GND
IO_L11P_0
IO_L11N_0
VCCO_0
IO_L12P_0
IO_L12N_0/VREF_0
IP
VCCAUX
IO_L13P_0
IO_L13N_0
GND
IO_L14P_0
IO_L14N_0/VREF_0
VCCO_0
IO_L15P_0
IO_L15N_0
IP
IO_L16P_0
IO_L16N_0/HSWAP
TDI
GND

20

2007/2/25

Ulinx_MB_XC3S250E

: Human_IO
Human_IO MB_XC3S250E ,,,LED,
J5,J6 MB_XC3S250E J1,J2, HUMAIN_IO
.

3-1. IO_LED16
Human_IO 16 LED, 8 ,8 ,
FPGA 1(High),LED .
FPGA 0(LOW),LED .
NET "IO_LED16<0>" LOC = "P3" ;
NET "IO_LED16<1>" LOC = "P2" ;
NET "IO_LED16<2>" LOC = "P5" ;
NET "IO_LED16<3>" LOC = "P4" ;
NET "IO_LED16<4>" LOC = "P9" ;
NET "IO_LED16<5>" LOC = "P8" ;
NET "IO_LED16<6>" LOC = "P12" ;
NET "IO_LED16<7>" LOC = "P11" ;
NET "IO_LED16<8>" LOC = "P16" ;
NET "IO_LED16<9>" LOC = "P15" ;
NET "IO_LED16<10>" LOC = "P19" ;
NET "IO_LED16<11>" LOC = "P18" ;
NET "IO_LED16<12>" LOC = "P23" ;
NET "IO_LED16<13>" LOC = "P22" ;
NET "IO_LED16<14>" LOC = "P25" ;
NET "IO_LED16<15>" LOC = "P24" ;

Ulinx

21

2007/2/25

Ulinx_MB_XC3S250E

FPGA PIN
P3
P2
P5
P4
P9
P8
P12
P11

SYMBOL
A1_IO1
A1_IO2
A1_IO3
A1_IO4
A1_IO5
A1_IO6
A1_IO7
A1_IO8

LABEL NAME
D16
D15
D14
D13
D12
D11
D10
D9

LOGIC
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED

COMMENT
LED
LED
LED
LED
LED
LED
LED
LED

P16
P15
P19
P18
P23
P22
P25
P24

A1_IO9
A1_IO10
A1_IO11
A1_IO12
A1_IO13
A1_IO14
A1_IO15
A1_IO16

D8
D7
D6
D5
D4
D3
D2
D1

FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED
FPGA 1,LED

LED
LED
LED
LED
LED
LED
LED
LED

Ulinx

22

2007/2/25

Ulinx_MB_XC3S250E

3-2. IO_KEY4X4
Human_IO 4X4 , 16 ,4X4
.
NET "IO_KEYI<3>"
LOC = "P29" ;
NET "IO_KEYI<2>"
LOC = "P28" ;
NET "IO_KEYI<1>"
LOC = "P31" ;
NET "IO_KEYI<0>"
LOC = "P30" ;
NET "IO_KEYO<3>"
LOC = "P34" ;
NET "IO_KEYO<2>"
LOC = "P33" ;
NET "IO_KEYO<1>"
LOC = "P36" ;
NET "IO_KEYO<0>"
LOC = "P35" ;
.

PIN 1

Ulinx

23

2007/2/25

Ulinx_MB_XC3S250E

FPGA PIN
P35
P36
P33
P34

SYMBOL
A1_IO24
A1_IO23
A1_IO22
A1_IO21

LABEL NAME
KEY4X4_PIN1
KEY4X4_PIN2
KEY4X4_PIN3
KEY4X4_PIN4

LOGIC
1
2
3
4

COMMENT
LED
LED
LED
LED

P30
P31
P28
P29

A1_IO20
A1_IO19
A1_IO18
A1_IO17

KEY4X4_PIN5
KEY4X4_PIN6
KEY4X4_PIN7
KEY4X4_PIN8

1
2
3
4

LED
LED
LED
LED

Ulinx

24

2007/2/25

Ulinx_MB_XC3S250E

3-3. DIFFERENTIAL LINE RECEVIER & LINE DRIVER


Human_IO 4 Differential Line Driver 4 Differential Line Receiver,
Differential . P2 JP1,.
JP1 PIN1 PIN2
NET "IO_MC3487_O<0>"
NET "IO_MC3487_O<1>"
NET "IO_MC3487_O<2>"
NET "IO_MC3487_O<3>"
NET "IO_MC3486_I<0>"
NET "IO_MC3486_I<1>"
NET "IO_MC3486_I<2>"
NET "IO_MC3486_I<3>"

LOC = "P40"
LOC = "P39"
LOC = "P42"
LOC = "P41"
LOC = "P48"
LOC = "P47"
LOC = "P50"
LOC = "P49"

;
;
;
;
;
;
;
;

FPGA PIN
P40
P39
P42
P41

SYMBOL
A1_IO25
A1_IO26
A1_IO27
A1_IO28

LABEL NAME
DIFF OUT1
DIFF OUT2
DIFF OUT3
DIFF OUT4

LOGIC
TTL DIFF OUT(5V)
TTL DIFF OUT
TTL DIFF OUT
TTL DIFF OUT

COMMENT
P2 PIN1,2
P2 PIN3,4
P2 PIN5,6
JP1 PIN1,2

P48
P47
P50
P49

A1_IO29
A1_IO30
A1_IO31
A1_IO32

DIFF IN1
DIFF IN2
DIFF IN3
DIFF IN4

TTL DIFF IN(5V)


TTL DIFF IN
TTL DIFF IN
TTL DIFF IN

P2 PIN9,10
P2 PIN11,12
P2 PIN13,14
JP1 PIN3,4

Ulinx

25

2007/2/25

Ulinx_MB_XC3S250E

3-4. ANALOG IN / ANALOG OUT


Human_IO 2 8 4 12 ,ADC
ADC0832, DAC LTC2624,:
ADC1: P1 PIN7 , 0~5V, 32us, 8
ADC2: P1 PIN8 , 0~5V, 32us, 8
DAC1: P1 PIN1 , 0~3.3V, 12
DAC2: P1 PIN2 , 0~3.3V, 12
DAC3: P1 PIN3 , 0~3.3V, 12
DAC4: P1 PIN4 , 0~3.3V, 12
ADC DAC ,, FPGA .
NET "IO_ADC_CSN"
LOC = "P187" ;
NET "IO_ADC_CLK"
LOC = "P179" ;
NET "IO_ADC_SDI"
LOC = "P135" ;
NET "IO_ADC_SDO"
LOC = "P160" ;
NET "IO_DAC_CS"
NET "IO_DAC_SCK"
NET "IO_DAC_SDI"
NET "IO_DAC_SDO"
NET "IO_DAC_CLR"
FPGA PIN
P187
P179
P135
P160
P163
P162
P165
P164
P177

Ulinx

SYMBOL
A1_IO33
A1_IO34
A1_IO35
A1_IO36
A1_IO37
A1_IO38
A1_IO39
A1_IO40
A1_IO46

LOC = "P163"
LOC = "P162"
LOC = "P165"
LOC = "P164"
LOC = "P177"
LABEL NAME
ADC_CSN
ADC_CLK
ADC_SDI
ADC_SDO
DAC_CS
DAC_SCK
DAC_SDI
DAC_SDO
DAC_CLR

;
;
;
;
;

LOGIC
ADC_CSN
ADC_CLK
ADC_SDI
ADC_SDO
DAC_CS
DAC_SCK
DAC_SDI
DAC_SDO
DAC_CLR

26

COMMENT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTOUT

2007/2/25

Ulinx_MB_XC3S250E

ADC .

DAC .

Ulinx

27

2007/2/25

Ulinx_MB_XC3S250E

"DP-CE-CF-CD-CC-CB-CA"=01101011

3-5.

Human_IO 8 , FPGA .,,


2,11011010 CA~DP,
01111111 AN1~AN8 .
AN1
0
P181

CA(1):P197
CB(1):P196
CC(0):P200
CD(1):P199
CE(1):P203
CF(0):P202
CG(1):P206
DP(0):P205

AN2
1
P180

AN4
1
P185

AN5
1
P190

AN6
1
P189

AN7
1
P193

AN8
1
P192

CA
CB

CF
CG
CE

NET "IO_DIGIT<0>"
NET "IO_DIGIT<1>"
NET "IO_DIGIT<2>"
NET "IO_DIGIT<3>"
NET "IO_DIGIT<4>"
NET "IO_DIGIT<5>"
NET "IO_DIGIT<6>"
NET "IO_DIGIT<7>"

CC
CD DP

LOC = "P181"
LOC = "P180"
LOC = "P186"
LOC = "P185"
LOC = "P190"
LOC = "P189"
LOC = "P193"
LOC = "P192"

NET "IO_SEGMENT<0>"
NET "IO_SEGMENT<1>"
NET "IO_SEGMENT<2>"
NET "IO_SEGMENT<3>"
NET "IO_SEGMENT<4>"
NET "IO_SEGMENT<5>"
NET "IO_SEGMENT<6>"
NET "IO_SEGMENT<7>"

Ulinx

AN3
1
P186

;
;
;
;
;
;
;
;

LOC = "P197"
LOC = "P196"
LOC = "P200"
LOC = "P199"
LOC = "P203"
LOC = "P202"
LOC = "P206"
LOC = "P205"

##AN1
##AN2
##AN3
##AN4
##AN5
##AN6
##AN7
##AN8
;
;
;
;
;
;
;
;

28

##CA
##CB
##CC
##CD
##CE
##CF
##CG
##DP

2007/2/25

Ulinx_MB_XC3S250E

FPGA PIN
P181
P180
P186
P185
P190
P189
P193
P192

SYMBOL
A2_IO1
A2_IO2
A2_IO3
A2_IO4
A2_IO5
A2_IO6
A2_IO7
A2_IO8

LABEL NAME
IO_DIGIT<0>
IO_DIGIT<1>
IO_DIGIT<2>
IO_DIGIT<3>
IO_DIGIT<4>
IO_DIGIT<5>
IO_DIGIT<6>
IO_DIGIT<7>

LOGIC
0,
0,
0,
0,
0,
0,
0,
0,

COMMENT
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8

P197
P196
P200
P199
P203
P202
P206
P205

A2_IO9
A2_IO10
A2_IO11
A2_IO12
A2_IO13
A2_IO14
A2_IO15
A2_IO16

IO_SEGEMENT<0>
IO_SEGEMENT<1>
IO_SEGEMENT<2>
IO_SEGEMENT<3>
IO_SEGEMENT<4>
IO_SEGEMENT<5>
IO_SEGEMENT<6>
IO_SEGEMENT<7>

1,
1,
1,
1,
1,
1,
1,
1,

U4 CA
U4 CB
U4 CC
U4 CD
U4 CE
U4 CF
U4 CG
U4 DP

Ulinx

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Ulinx_MB_XC3S250E

3-6. LCD128X64
LCD128X64 128 X 64 PIXEL ,,
,LCD128X64 ,,
,.

Net "IO_LCD128x64<0>"
Net "IO_LCD128x64<1>"
Net "IO_LCD128x64<2>"
Net "IO_LCD128x64<3>"
Net "IO_LCD128x64<4>"
Net "IO_LCD128x64<5>"
Net "IO_LCD128x64<6>"
Net "IO_LCD128x64<7>"

LOC = "P123" ;
LOC = "P119" ;
LOC = "P120" ;
LOC = "P115" ;
LOC = "P116" ;
LOC = "P112" ;
LOC = "P113" ;
LOC = "P108" ;

##LCD_DO(A2_IO27)
##LCD_D1(A2_IO26)
##LCD_D2(A2_IO25)
##LCD_D3(A2_IO24)
##LCD_D4(A2_IO23)
##LCD_D5(A2_IO22)
##LCD_D6(A2_IO21)
##LCD_D7(A2_IO20)

Net "IO_LCD128x64<10>" LOC = "P107" ; ##LCD_RST(A2_IO17)


Net "IO_LCD128x64<11>" LOC = "P106" ; ##LCD_CS2(A2_IO18)
Net "IO_LCD128x64<12>" LOC = "P109" ; ##LCD_CS1(A2_IO19)
Net "IO_LCD128x64<13>" LOC = "P122" ; ##LCD_E (A2_IO28)
Net "IO_LCD128x64<14>" LOC = "P127" ; ##LCD_RW(A2_IO29)
Net "IO_LCD128x64<15>" LOC = "P126" ; ##LCD_DI(A2_IO30)

Ulinx

30

2007/2/25

Ulinx_MB_XC3S250E

FPGA PIN
P123
P119
P120
P115
P116
P112
P113
P108
P107
P106
P109
P122
P127
P126

Ulinx

SYMBOL
A2_IO27
A2_IO26
A2_IO25
A2_IO24
A2_IO23
A2_IO22
A2_IO21
A2_IO20
A2_IO17
A2_IO18
A2_IO19
A2_IO28
A2_IO29
A2_IO30

LABEL NAME
IO_LCD128X64<0>
IO_ LCD128X64<1>
IO_ LCD128X64<2>
IO_ LCD128X64<3>
IO_ LCD128X64<4>
IO_ LCD128X64<5>
IO_ LCD128X64<6>
IO_ LCD128X64<7>
IO_ LCD128X64<10>
IO_ LCD128X64<11>
IO_ LCD128X64<12>
IO_ LCD128X64<13>
IO_ LCD128X64<14>
IO_ LCD128X64<15>

31

LOGIC
FPGA_LCD_D0
FPGA_LCD_D1
FPGA_LCD_D2
FPGA_LCD_D3
FPGA_LCD_D4
FPGA_LCD_D5
FPGA_LCD_D6
FPGA_LCD_D7
FPGA_LCD_RST
FPGA_LCD_CS2
FPGA_LCD_CS1
FPGA_LCD_E
FPGA_LCD_RW
FPGA_LCD_DI

COMMENT
U13_PIN7
U13_PIN8
U13_PIN9
U13_PIN10
U13_PIN11
U13_PIN12
U13_PIN13
U13_PIN14
U13_PIN17
U13_PIN16
U13_PIN15
U13_PIN6
U13_PIN5
U13_PIN4

2007/2/25

Ulinx_MB_XC3S250E

3-7. LCD16X2
LCD16X2 , ASCII LCD16X2 ,
, 16 ,.

Net "IO_LCD16x2<0>"
Net "IO_LCD16x2<1>"
Net "IO_LCD16x2<2>"
Net "IO_LCD16x2<3>"
Net "IO_LCD16x2<4>"
Net "IO_LCD16x2<5>"
Net "IO_LCD16x2<6>"
Net "IO_LCD16x2<7>"

LOC = "P123" ;
LOC = "P119" ;
LOC = "P120" ;
LOC = "P115" ;
LOC = "P116" ;
LOC = "P112" ;
LOC = "P113" ;
LOC = "P108" ;

##LCD_DO(A2_IO27)
##LCD_D1(A2_IO26)
##LCD_D2(A2_IO25)
##LCD_D3(A2_IO24)
##LCD_D4(A2_IO23)
##LCD_D5(A2_IO22)
##LCD_D6(A2_IO21)
##LCD_D7(A2_IO20)

Net "IO_LCD16x2<13>" LOC = "P122" ; ##LCD_E (A2_IO28)


Net "IO_LCD16x2<14>" LOC = "P127" ; ##LCD_RW(A2_IO29)
Net "IO_LCD16x2<15>" LOC = "P126" ; ##LCD_DI(A2_IO30)

Ulinx

32

2007/2/25

Ulinx_MB_XC3S250E

FPGA PIN
P123
P119
P120
P115
P116
P112
P113
P108
P122
P127
P126

Ulinx

SYMBOL
A2_IO27
A2_IO26
A2_IO25
A2_IO24
A2_IO23
A2_IO22
A2_IO21
A2_IO20
A2_IO28
A2_IO29
A2_IO30

LABEL NAME
IO_LCD16X2<0>
IO_ LCD16X2<1>
IO_ LCD16X2<2>
IO_ LCD16X2<3>
IO_ LCD16X2<4>
IO_ LCD16X2<5>
IO_ LCD16X2<6>
IO_ LCD16X2<7>
IO_ LCD16X2<13>
IO_ LCD16X2<14>
IO_ LCD16X2<15>

33

LOGIC
FPGA_LCD_D0
FPGA_LCD_D1
FPGA_LCD_D2
FPGA_LCD_D3
FPGA_LCD_D4
FPGA_LCD_D5
FPGA_LCD_D6
FPGA_LCD_D7
FPGA_LCD_E
FPGA_LCD_RW
FPGA_LCD_DI

COMMENT
U12_PIN7
U12_PIN8
U12_PIN9
U12_PIN10
U12_PIN11
U12_PIN12
U12_PIN13
U12_PIN14
U12_PIN6
U12_PIN5
U12_PIN4

2007/2/25

Ulinx_MB_XC3S250E

3-8. PS2
PS2 PC .

Net "IO_PS2_DATA" LOC = "P129" ; ##A2_IO31


Net "IO_PS2_CLK"
LOC = "P128" ; ##A2_IO32

FPGA PIN SYMBOL


P129
A2_IO31
P128
A2_IO32

Ulinx

LABEL NAME
PS2_DATA
PS2_CLK

34

LOGIC

COMMENT
U3_PIN1
U3_PIN5

2007/2/25

Ulinx_MB_XC3S250E

3-9. VGA
PS2 PC VGA , 8 .

Net "IO_VGA_VSYNC"
Net "IO_VGA_HSYNC"
Net "IO_VGA_B"
Net "IO_VGA_G"
Net "IO_VGA_R"

Ulinx

LOC = "P168" ;
LOC = "P167" ;
LOC = "P172" ;
LOC = "P171" ;
LOC = "P178" ;

##A1_IO41
##A1_IO42
##A1_IO43
##A1_IO44
##A1_IO45

35

2007/2/25

Ulinx_MB_XC3S250E

FPGA PIN
P168
P167
P172
P171
P178

Ulinx

SYMBOL
A1_IO41
A1_IO42
A1_IO43
A1_IO44
A1_IO45

LABEL NAME
IO_VGA_VSYNC
IO_VGA_HSYNC
IO_VGA_B
IO_VGA_G
IO_VGA_R

36

LOGIC
VSYNC
HSYNC
BLUE
GREEN
RED

COMMENT
U8_PIN14
U8_PIN13
U8_PIN3
U8_PIN2
U8_PIN1

2007/2/25

Ulinx_MB_XC3S250E

3-10. PUSH BUTTON


HUMAN_IO DIP_SWICTH,,
PUSH_BUTTON ,0;1
DIP_SWITCH [ON],0;[OFF].
NET "IO_DIP_SWITCH<0>" LOC = "P138" ;
NET "IO_DIP_SWITCH<1>" LOC = "P137" ;
NET "IO_DIP_SWITCH<2>" LOC = "P140" ;
NET "IO_DIP_SWITCH<3>" LOC = "P139" ;
NET "IO_PUSH_BUTTON<0>"
NET "IO_PUSH_BUTTON<1>"
NET "IO_PUSH_BUTTON<2>"
NET "IO_PUSH_BUTTON<3>"

LOC = "P133"
LOC = "P132"
LOC = "P135"
LOC = "P134"

;
;
;
;

FPGA PIN
P138
P137
P140
P139

SYMBOL
IO_DIP1
IO_DIP2
IO_DIP3
IO_DIP4

LABEL NAME
USER_SW1
USER_SW2
USER_SW3
USER_SW5

LOGIC
ON ,0
ON ,0
ON ,0
ON ,0

COMMENT
IO_S1_1
IO_S1_2
IO_S1_3
IO_S2_4

P133
P132
P135
P134

IO_SW1
IO_SW2
IO_SW3
IO_SW4

USER_DIP1
USER_DIP2
USER_DIP3
USER_DIP4

,0
,0
,0
,0

IO_S5
IO_S4
IO_S3
IO_S2

Ulinx

37

2007/2/25

Ulinx_MB_XC3S250E

3-11. ROTARY
HUMAN_IO ROTARY SWICTH,
NET "IO_ROTARY<0>" LOC = "P145" ;
NET "IO_ROTARY<1>" LOC = "P147" ;
NET "IO_ROTARY<2>" LOC = "P144" ;
NET "IO_ROTARY<3>" LOC = "P146" ;
FPGA PIN

SYMBOL

P145
P147
P144
P146

IO_ROTARY<0>
IO_ROTARY<1>
IO_ROTARY<2>
IO_ROTARY<3>

LABEL
NAME
A2_IO41
A2_IO42
A2_IO43
A2_IO44

LOGIC

COMMENT

IO_S3
IO_S2

ROTARY 0~9 ,IO_ROTARY<0> ~ IO_ROTARY<3>


,
POSITION IO_ROTARY<3>
IO_ROTARY<2> IO_ROTARY<1>
IO_ROTARY<1>
1
1
1
1
0
1
1
1
0
1
1
1
0
1
2
1
1
0
0
3
1
0
1
1
4
1
0
1
0
5
1
0
0
1
6
1
0
0
0
7
0
1
1
1
8
0
1
1
0
9

Ulinx

38

2007/2/25

Ulinx_MB_XC3S250E

3-12. IIC
HUMAN_IO IIC FLASH, 24C02
NET "IO_IIC_SCL" LOC = "P151" ;
NET "IO_IIC_SDA" LOC = "P150" ;
FPGA PIN

SYMBOL

P151
P150

IO_IIC_SCL
IO_IIC_SDA

Ulinx

LABEL
NAME
A2_IO45
A2_IO46

39

LOGIC

COMMENT
U7_PIN6
U7_PIN5

2007/2/25

Ulinx_MB_XC3S250E

: Ulinx_MB_XC3S250E_PQ208

4-1. ISE , CD .
4-2.,.
4-2-1. DB25 1 1 PC_Printer_Port XC3S250E
P1(JTAG)
4-2-2. (DC+5V/3A) ULINX_MB_XC3S250E . J8 +5V
4-2-3. RS232 , 1 1 DB9 COM Port
( [][] Baud:9600,Data:8,Stop:1,No Parity.)

4-2-4. .
J6 : (4 pin)
J5 : (4 pin)
J4 : 1,2 ().
open
4-2-5. R8,R9 VR ;

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4-2-6. S10 , DC+5V/3A , LED .


D1/1.2V :
D2/2.5V :
D3/3.3V :
D4/1.8V :

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4-3. Impact
4-3-1. [][][Xilinx ISE 8.1i][Accessories] [Impact]
[Cancel],

4-3-2. [File][New] [Cancel]


[Edit][Launch Wizard] [Configure Device using
Boundary-Scan(JTAG)]
[Finish]

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4-3-3. JTAG XCF02 XC3S400 ,,


XCF08 XC3S250E_test.mcs
XC3S250E [Bypass].

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[Note]: [

].

4-3-4.(XCF02), XCF02 ,,

[Verify] [Erase Before Programming] [OK]


***[Note]: , [Erase Before Programming]

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4-3-5.

4-3-6..

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4-4..
4-4-1 ,.D6/Done
4-4-2. R10() , LCD .LCD
( R9 , ).

Rot=0
KeyBoard = ?
SW=11111111 1111
DP =11111111 1111

4-4-3. FPGA [S2],[S3],[S4],[S5],[S6],[S7],[S8],[S9] LCD SW 8


0
4-4-4. HUMAN_IO [S1],[S2],[S3],[S4] LCD SW 4
0
4-4-5. FPGA S1
S1-1 [ON] , LCD DP : 11111110 1111
S1-2 [ON] , LCD DP : 11111101 1111
S1-3 [ON] , LCD DP : 11111011 1111
S1-4 [ON] , LCD DP : 11110111 1111
S1-5 [ON] , LCD DP : 11101111 1111
S1-6 [ON] , LCD DP : 11011111 1111
S1-7 [ON] , LCD DP : 10111111 1111
S1-8 [ON] , LCD DP : 01111111 1111

4-4-6. HUMAN_IO S1
S1-1 [ON] , LCD
S1-2 [ON] , LCD
S1-3 [ON] , LCD
S1-4 [ON] , LCD

Ulinx

DP : 11111111 1110
DP : 11111111 1101
DP : 11111111 1011
DP : 11111111 0111

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4-4-7. KEY4X4 .
[F] LCD KeyBoard KeyBoard = F
[E] LCD KeyBoard KeyBoard = E
[D] LCD KeyBoard KeyBoard = D
[C] LCD KeyBoard KeyBoard = C
[B] LCD KeyBoard KeyBoard = B
[3] LCD KeyBoard KeyBoard = 3
[6] LCD KeyBoard KeyBoard = 6
[9] LCD KeyBoard KeyBoard = 9
[A] LCD KeyBoard KeyBoard = A
[2] LCD KeyBoard KeyBoard = 2
[5] LCD KeyBoard KeyBoard = 5
[8] LCD KeyBoard KeyBoard = 8
[0] LCD KeyBoard KeyBoard = 0
[1] LCD KeyBoard KeyBoard = 1
[4] LCD KeyBoard KeyBoard = 4
[7] LCD KeyBoard KeyBoard = 7
4-4-8. ,
00000000 => 00010001 => 00020002 => 00030003 ..
4-4-9. HUMAN_IO ROTARY.
0 LCD Rot Rot = 0
1 LCD Rot Rot = 1
2 LCD Rot Rot = 2
3 LCD Rot Rot = 3
4 LCD Rot Rot = 4
5 LCD Rot Rot = 5
6 LCD Rot Rot = 6
7 LCD Rot Rot = 7
8 LCD Rot Rot = 8
9 LCD Rot Rot = 9

4-4-10. FPGA HUMAN_IO LED 24 LED,,


.

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4-4-11.

RS232

4-4-12. Finished!

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