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GENERAL DESCRIPTION
The W29C020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C020 results in fast write (erase/program) operations with extremely low current consumption compared to other comparable 5-volt flash memory products. The device can also be written (erased and programmed) by using standard EPROM programmers.
FEATURES
Single 5-volt write (erase and program)
Software and hardware data protection Low power consumption Active current: 25 mA (typ.) Standby current: 20 A (typ.)
operations
Fast page-write operations
128 bytes per page Page write (erase/program) cycle: 10 mS (max.) Effective byte-write (erase/program) cycle time: 39 S Optional software-protected data write
Fast chip-erase operation: 50 mS Two 8 KB boot blocks with lockout Typical page write (erase/program) cycles:
100/1K/10K
Read access time: 70/90/120 nS Ten-year data retention
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W29C020
PIN CONFIGURATIONS BLOCK DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
VDD WE A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
32-pin DIP
26 25 24 23 22 21 20 19 18 17
A0 . . DECODER
CORE ARRAY
8K Byte Boot Block (Optional)
A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
A 1 5 3
A 1 6 2
N C
V / D W D E
A 1 7
. A17
29 28 27 A14 A13 A8 A9 A11 OE A10 CE DQ7
1 32 31 30
32-pin PLCC
26 25 24 23 22 21
14 15 16 17 18 19 20
PIN DESCRIPTION
SYMBOL A0A17
32 31 30 29 28 27
D Q 1
D G Q N 2 D
D Q 3
D Q 4
D Q 5
D Q 6
PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
32-pin TSOP
26 25 24 23 22 21 20 19 18 17
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W29C020
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C020 is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the read cycle timing waveforms for further details.
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W29C020
will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. For information about specific codes, see the Command Codes for Software Data Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below.
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W29C020
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W29C020 provides another method for determining the end of a write cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. See Toggle Bit Timing Diagram.
Product Identification
The product ID operation outputs the manufacturer code and device code. The programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed through software or by hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts.
MODE CE Read Write Standby Write Inhibit Output Disable 5-Volt Software Chip Erase Product ID VIL VIL VIH X X X VIL VIL VIL OE VIL VIH X VIL X VIH VIH VIL VIL WE VIH VIL X X VIH X VIL VIH VIH AIN AIN X X X X AIN
PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code DA (Hex) Device Code 45 (Hex) DQ.
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W29C020
Command Codes for Software Data Protection
BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS DATA 5555H AAH 2AAAH 55H 5555H A0H TO DISABLE PROTECTION ADDRESS DATA 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H
Pause 10 mS
Exit
Pause 10 mS
Exit
Notes for software program code: Data Format: DQ7DQ0 (Hex) Address Format: A14A0 (Hex)
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W29C020
Command Codes for Software Chip Erase
BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H
Pause 50 mS
Exit
Notes for software chip erase: Data Format: DQ7DQ0 (Hex) Address Format: A14A0 (Hex)
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W29C020
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE SEQUENCE ALTERNATE PRODUCT (7) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 5555 2AAA 5555 Pause 10 S DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 10 S DATA AAH 55H 80H AAH 55H 60H SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT ADDRESS 5555H 2AAAH 5555H Pause 10 S DATA AAH 55H F0H -
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
(2)
Read address = 00000 data = DA
(2)
Read address = 00001 data = 45
(4)
Read address = 00002 data = FF/FE
(5)
Read address = 3FFF2 data = FF/FE
Pause 10 S
Pause 10 S
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7DQ0 (Hex); Address Format: A14A0 (Hex) (2) A1A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns to standard operation mode. (7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used.
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W29C020
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ON FIRST 8K ADDRESS BOOT BLOCK ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write 5555H 2AAAH 5555H 5555H 2AAAH 5555H 00000H Pause 10 mS DATA AAH 55H 80H AAH 55H 40H 00H BOOT BLOCK LOCKOUT FEATURE SET ON LAST 8K ADDRESS BOOT BLOCK ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H 3FFFFH Pause 10 mS DATA AAH 55H 80H AAH 55H 40H FFH
Pause 10 mS
Pause 10 mS
Notes for boot block lockout enable: 1. Data Format: DQ7DQ0 (Hex) 2. Address Format: A14A0 (Hex) 3. If you have any questions about this commend sequence, please contact the local distributor or Winbond Electronics Corp.
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W29C020
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Except A9 Transient Voltage (<20 nS ) on Any Pin to Ground Potential Voltage on A9 and OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
UNIT
ICC
mA
Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS
ISB1
mA A A A V V V V V
CE = VDD -0.3V, all DQs open VIN = GND to VDD VIN = GND to VDD IOL = 2.0 mA IOH = -400 A IOH = -100 A; VCC = 4.5V
20 -
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W29C020
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
CAPACITANCE
(VDD = 5.0V, TA = 25 C, f = 1 MHz)
MAX. 12 6
UNIT pF pF
AC CHARACTERISTICS
AC Test Conditions
(VDD = 5.0V 10% for 90 nS and 120 nS; VDD = 5.0V 5% for 70 nS)
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V <5 nS 1.5V/1.5V
CONDITIONS
1.8K
D OUT
1.3K
Input
3V 1.5V 0V Test Point
Output
1.5V
Test Point
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W29C020
AC Characteristics, continued
PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE High to High-Z Output OE High to High-Z Output Output Hold from Address change
W29C020-70 W29C020-90 W29C020-12 MIN. 70 0 MAX. 70 70 35 25 25 MIN. 90 0 MAX. 90 90 40 25 25 MIN. 120 0 MAX. 120 120 50 30 30 -
UNIT nS nS nS nS nS nS nS
Note: All AC timing signals observe the following guideline for determining setup and hold times: Reference level is VIH for high-level signal and VIL for low-level signal.
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W29C020
AC Characteristics, continued
Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters.
Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters.
TIMING WAVEFORMS
Read Cycle Timing Diagram
OE
T OE
T OHZ VIH WE TOH DQ7-0 High-Z Data Valid T AA Data Valid T CHZ
High-Z
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W29C020
Timing Waveforms, continued
CE
TCS TOES
TCH T OEH
OE TWP TWPH
WE
TAS
T AH
T WC
TOEH TCH
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W29C020
Timing Waveforms, continued
DQ7-0
CE
TBLC
Byte 1
Byte 2
Byte N
Address A15-0
WE
TWR
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W29C020
Timing Waveforms, continued
WE
CE OE
TWR
DQ6
Three-byte sequence for software data protection mode Address A15-0 5555 2AAA 5555
TWC
DQ7-0
AA
55
A0
CE
TBLC
SW1
SW2
Word 0
Word N-1
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W29C020
Timing Waveforms, continued
Six-byte sequence for resetting software data protection mode Address A15-0 5555 2AAA 5555 5555 2AAA 5555
TWC
DQ7-0
AA
55
80
AA
55
20
CE
OE WE
TBLC
SW1
SW2
SW3
SW4
Six-byte code for 5V-only software chip erase Address A15-0 5555 2AAA 5555 5555 2AAA 5555
TWC
DQ7-0 CE
AA
55
80
AA
55
10
OE WE
TBLC
SW1
SW2
SW3
SW4
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W29C020
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 POWER SUPPLY CURRENT MAX. (mA) 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 STANDBY VDD CURRENT MAX. (A) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE CYCLING
W29C020-70A W29C020-90A W29C020-12A W29C020S-70A W29C020S-90A W29C020S-12A W29C020T-70A W29C020T-90A W29C020T-12A W29C020P-70A W29C020P-90A W29C020P-12A W29C020-70 W29C020-90 W29C020-12 W29C020S-70 W29C020S-90 W29C020S-12 W29C020T-70 W29C020T-90 W29C020T-12 W29C020P-70 W29C020P-90 W29C020P-12 W29C020-70B W29C020-90B W29C020-12B W29C020S-70B W29C020S-90B W29C020S-12B W29C020T-70B W29C020T-90B W29C020T-12B W29C020P-70B W29C020P-90B W29C020P-12B
600 mil DIP 600 mil DIP 600 mil DIP 450 mil SOP 450 mil SOP 450 mil SOP Type one TSOP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 32-pin PLCC 600 mil DIP 600 mil DIP 600 mil DIP 450 mil SOP 450 mil SOP 450 mil SOP Type one TSOP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 32-pin PLCC 600 mil DIP 600 mil DIP 600 mil DIP 450 mil SOP 450 mil SOP 450 mil SOP Type one TSOP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 32-pin PLCC
100 100 100 100 100 100 100 100 100 100 100 100 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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W29C020
PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in inches
Dimension in mm
Symbol
D
32 17
E1
A A1 A2 B B1 c D E E1 e1 L
a
16
eA S Notes:
E c
A A2 L B B1
A1
e1
eA
1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches. 6.General appearance spec. should be based on final visual inspection spec.
Dimension in Inches
Dimension in mm
Symbol
32 17
Min.
0.004 0.101 0.014 0.006
Nom.
Max.
0.118
Min.
0.10
Nom.
Max.
3.00
e1
E HE
L
Detail F
1
16
A A1 A2 b c D E e HE L LE S y Notes:
c
0.111 0.020 0.012 0.817 0.450 0.056 0.556 0.039 0.063 0.036 0.004
2.82 0.51 0.31 20.75 11.43 1.42 14.38 0.99 1.60 0.91 0.10
10
10
e1
A2 S y e
A1
LE
See Detail F
Seating Plane
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec.
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W29C020
Package Dimensions, continued
32-pin PLCC
HE E
32
30
Symbol
5 29
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom.
Max.
0.140
Min.
0.50
Nom.
Max.
3.56
GD D HD
13
21
14
20
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
10
10
L A2 A
Seating Plane
b b1 G
E
A1 y
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc.
32-pin TSOP
HD
Symbol
D c
A A1 A2
__
0.002 0.037 0.007 0.005 0.720 0.311 0.780
__ __
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031 0.006 0.041 0.009 0.007 0.728 0.319 0.795
__
0.05 0.95 0.17 0.12 18.30 7.90 19.80
__ __
1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80
e E
b c D
0.10(0.004)
E HD e L L1
A A2 L L1 A1
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
__
3
__
3
Y
Note:
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W29C020
VERSION HISTORY
VERSION A1 A2 DATE Apr. 1997 Nov. 1997 4, 8 9 15 1, 18 A3 Feb. 1998 6 7 8 1, 18 PAGE Initial Issued Correct the address from 3FFF2 to 7FFF2 Correct the boot block from 8K to 16K Modify page write cycle timing diagram waveform Delete cycling 100K item Add. pause 10 mS Add. pause 50 mS Correct the time from 10 mS to 10 S Add. cycling 100 item DESCRIPTION
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5796096 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 408-9436666 Voice & Fax-on-demand: 886-2-27197006 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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