Diamond Lewis Homework 2 CS 458 6/11/12 In electronics, a hardware description language or HDL is any language from a class of computer

languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most commonly, digital logic. Verilog was the first modern hardware description language to be invented. It was created by Phil Moorby and Prabhu Goel during the winter of 1983/1984. Verilog was intended to describe and allow simulation; only afterwards was support for synthesis added. It was purchased by Cadence Design Systems in 1990. With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the originalVerilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001. Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system tasks. And finally, a few syntax additions were introduced to improve code readability. Verilog most commonly used in the design, verification, and implementation of digital logic chips at the transfer of data between hardware registers while hiding information from the user. Verilog Hello World Example
module main; initial begin $display("Hello world!"); $finish; end endmodule

A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and bidirectional ports. Sequential statements are placed inside a begin/end block and executed in sequential order with system tasks (i.e $display, $finish) within the block. However, the blocks themselves are executed concurrently, making Verilog a dataflow language.

VHDL (Very-High-Speed Integrated Circuit HDL) was originally developed by the U.S Department of Defense in order to document the behavior of circuit chips that had particular use rather than general-purpose use. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details. The idea of being able to simulate this documentation, logic simulators were developed that could read the VHDL files. The next step was the development of tools that read the VHDL, and output a definition of the physical implementation of the circuit. VHDL borrows heavily from the Ada programming language in both concepts and syntax. VHDL Hello World Example
entity hello_world is end; architecture hello_world of hello_world is begin stimulus : process begin assert false report "Hello World By Diamond" severity note; wait; end process stimulus; end hello_world;

VHDL is commonly used to write text models that describe a logic circuit. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. VHDL starts with reserved word entity <entity_name>. Architecture is body for entity, which implements the functionality for entity. The key advantage of VHDL, when used for systems design, is that it allows the behavior of the system to be modeled and simulated before synthesis tools translate the design into real hardware. Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects, memory size, element base, block composition and interconnection.VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies. http://en.wikipedia.org/wiki/Verilog; http://en.wikipedia.org/wiki/VHDL;