1

3
/
4

0 1

+ < =

Tco
(Tco=Tsetpup+Thold)Tdelay
Tsetup D
Tco Tdelay

TcoTdelayTsetup Tmin =TcoTdelay

Tsetup Fmax =1/TminFPGA
Fmax Tco Tsetup
Tdelay

""
N

FPGA/CPLD PAD PAD

TO PAD

9
12

3 FPGA/CPLD

10FPGA
SOPC I/O
FPGA

bug bug

 FPGA
alteraxilinx
IO FPGA
xilinx v2pro
11

1
2,3 FIFO
DPRAM
12FPGA CPLD
CPLD

FPGA

Product term Look up Table

EEPROM/FLASH

SRAM EEPROM

PLLRAM

13latchflip-flop

14FPGA
FPGA BLOCK RAM, LUT
RAMBLOCK RAM
BLOCK RAM BLOCK
RAM
15

0
16FPGA

FPGA

FPGA PLL,DLL
DCM D
17FPGA
buffer

18FPGA RAM/ROM/CAM
BLOCK RAMFFLUT

1 RAM BLOCK RAM

BLOCK RAM FF 4-LUT BLOCK RAM
BLOCK RAM
LUT REGISTER

2 FPGA BLOCK RAM

3 BLOCK RAM BLOCK RAM
4 RAM DISTRIBUTE RAM
19Xilinx DLL
Xilinx
IBUFG,IBUFGDS,BUFG,BUFGP,BUFGCE,BUFGMUX,BUFGDLL,DCM
FPGA p50
20HDL
HDL

RTL ()
21
look-up-table LUTLUT RAM FPGA
4 LUT LUT 4 16x1 RAM
HDL PLD/FPGA
RAM,

22IC EDA

2Fabless
systemC
systemC CoCentric Visual Elite
3HDL ultra visual VHDL
4modelsim
5synplify
6synopsys Prime Time
7Synopsys Formality.
23 IC IC

PCB

SMT
24 flip-flop logic-gate 1 carryin current-stage
carryout next-stage
carryout=carryin*current-stage
next-stage=carryin*current-stage+carryin*current-stage;
module(clk,current-stage,carryin,next-stage,carryout);
input clk, current-stage,carryin;
output next-stage,carryout;
always@(posedge clk)
carryout<=carryin&current-stage;
nextstage<=
25 10 5 10
1. fsm
2. verilog FPGA
3.

1A=1 10 B=1 5 Y=1 Z=1

2S0 S1 5
3
module sell(clk,rst,a,b,y,z);
begin
input clk,rst,a,b;
next_state=s0; y=1;
output y,z;
end
parameter s0=0,s1=1;
else
reg state,next_state;
next_state=s0;
always@(posedge clk)
begin
if(!rst)
state<=s0;
else
state<=next_state;
end

s1: if(a==1&&b==0)
begin
next_state=s0;y=1;
end
else if(a==0&&b==1)
begin
next_state=s0; y=1;z=1;
end
always@(a or b or cstate)
else
begin
next_state=s0;
y=0;z=0;
default: next_state=s0;
case(state)
endcase
s0: if(a==1&&b==0) next_state=s1;
end
else if(a==0&&b==1)
endmodule

1 A=1 B=1 Y=1 Z=1

2 S0 S1 S2
Verilog

26"",,?

, oc ,
oc ,. oc
od
27???

123

Y=A+A Y=AA

28?TTL COMS
TTLCMOSLVTTLLVCMOSECLEmitter Coupled LogicPECL
Pseudo/Positive Emitter Coupled LogicLVDSLow Voltage Differential Signaling
GTLGunning Transceiver LogicBTLBackplane Transceiver LogicETLenhanced
transceiver logicGTLPGunning Transceiver Logic PlusRS232RS422RS485
12V5V3.3V
12V5V3.3V
TTL CMOS TTL 0.3-3.6V CMOS 12V
5V CMOS TTL TTL CMOS
5V 12V
CMOS TTL;,TTL CMOS.

1 TTL COMS TTL COMS

3.5V TTL
2OC
3
4 COMS

6
7

:
1
2
3, 1k 10k

OC
OC 1
OC LED

29IC

30MOORE MEELEY
Moore ,
Mealy ,
31,

FIFO
32

33 Mux, timing.

34,,,,

35 P N ?
P N
N P P

36 mos
<> 92

37 NOT,NAND,NOR ,, transistor level

<> 117 134
38
CMOS , tow-to-one mux gate.( VIA 2003.11.06 )
Y=SA+SB Y=((SA)*(SA))

39 mux inv
:B A A ,F ,
().
Y=BA+BA
4 1 F(x,y,z)=xz+yz'
F(x,y,z)=xyz+xyz+xyz'+xyz=xy0+xyz+xyz+xy1
Y=ABD0+ABD1+ABD2+ABD3
D0=0D1=zD2=zD3=1

40 CMOS , Y=A*B+C(D+E).()
Y=A*B+C CMOS Y=A*B+C*D CMOS

Y=A*B+C(D+E)=((AB)(CD)(CE))
Y=A*B+C=((AB)C)
Y=A*B+C*D=((AB)(CD))
41
192

42A,B,C,D,E ,, F( A,B,C,D,E 1 0 ,
F 1, F 0),,-

43 CMOS D

CMOS
44LATCH DFF
45latch register , register. latch
latch register register
latch
latch
46 D
module div2(clk,rst,clk_out);
input clk,rst;
output reg clk_out;
always@(posedge clk)

begin
if(!rst)
clk_out <=0;
else
clk_out <=~ clk_out;
end
endmodule
DCM DCM

Q
47

48 7 ,15
module counter7(clk,rst,load,data,cout);
input clk,rst,load;
input [2:0] data;
output reg [2:0] cout;
always@(posedge clk)
begin
if(!rst)
cout<=3d0;
else if(load)
cout<=data;
else if(cout>=3d6)
cout<=3d0;
else
cout<=cout+3d1;
end
endmodule
49
PALPLAGALCPLDFPGA

50 Verilog VHDL , glitch

module(clk,data,q_out)
input clk,data;
output reg q_out;
reg q1;
always@(posedge clk)
begin
q1<=data;
q_out<=q1;
end
endmodule
51SRAM,FALSH MEMORY,DRAMSSRAM SDRAM ?
SRAM DRAM
REFRESH(CACHE)
FLASH
DRAM(REFRESHED)
SRAM

SSRAM SSRAM /

SDRAM
52
FDMATDMA
CDMAWDMA
53ASIC Setup time violation Hold time violation?
setup hold time violation
VIA2003.11.06

violation
54

1
2
3

55

1
2 FF
3
4
56

57

58
RL C
RC

59 reg setuphold delay

Tdelay < Tperiod - Tsetup Thold
Tperiod > Tsetup + Thold +Tdelay
Tco= Tsetup + Thold
60 T, D1 Tco T1max
T1min T2max, T2min D2
T3
T3setup>T+T2max T

T3hold>T1min+T2min
T1min+T2min
61 TsetupTdelayTck->qTco clock
delay,
T+Tclkdealy>Tsetup+Tco+Tdelay;
Thold>Tclkdelay+Tco+Tdelay;
623/2
2 3 JK-FF 3
D-FF 3 2
NOR Q2Q1=11B
H FF1 FF2 Fi
Q2Q1=11B
Q1
Q2 D-FF 3 AND Q2Q1

63
CMOSComplementary Metal Oxide Semiconductor
CMOS
MCU(Micro Controller Unit)(Single Chip
Microcomputer) CPU
RAMROM I/O

RISCreduced instruction set computer

80 MIPS RISC RISC
RISC
MIPS

CISC Complex Instruction Set Computer

DSPdigital signal processor

0 1

FPGAFieldProgrammable Gate Array PALGAL

CPLD ASIC

ASIC:

ASIC(Application Specific IC)

PCI(Peripheral Component Interconnect) Intel 1991

ECC Error Correcting CodeECC

ECC

DDR=Double Data Rate DDR DDR

SDRAM DDRSDRAM Synchronous Dynamic Random Access
Memory
IRQ Interrupt Request IRQ IRQ

USB , Universal Serial BUS

BIOS "Basic Input Output System""

" ROM

64

65Please show the CMOS inverter schematic, layout and its cross section with P-well
process. Plot its transfer curve (Vout-Vin) and also explain the operation region of PMOS
and NMOS for each segment of the transfer curve? circuit
design-beijing-03.11.09
66To design a CMOS inverter with balance rise and fall time, please define the ration of
channel width of PMOS and NMOS and explain? P N
67Please draw the transistor level schematic of a CMOS 2 input AND gate and explain
which input has faster response for output rising edge.(less delay time)
circuit
design-beijing-03.11.09
68 Y=AB+AB+CD
1INV 2AND 3OR 4NAND 5NOR 6XOR NAND
69 D

70DFF

D
71 D VIA 2003.11.06

D D

 D D
72 DFF , verilog
module dff(clk,d,qout);
input clk,d;
output qout;
reg qout;
always@(posedge clk)
begin
if(!reset)
qout<=0;
else
qout<=d;
end
endmodule
73 CMOS D

D
74 filp-flop logic-gate 1 carryin current-stage
carryout next-stage.

75 D 4

1
2
3
4
5
P314
76 N Johnson Counter, N=5
78 Verilog/VHDL
79 HDL 5
module adder4(a,b,ci,s,co);
input ci;
input [3:0] a,b;
output co;
output [3:0] s;
assign {co,s}=a+b+ci;
endmodule
module div5(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg [3:0] count;
always@(posedge clk)
begin
if(!rst)
begin
count<=0;
clk_out=0;
end
else if(count==3d5)
begin
count<=0;
clk_out=~clk_out;
end
else
count<=count+1;
end
endmodule

 50%
module div7 ( clk, reset_n, clkout );
input
clk,reset_n;
output
clkout;
reg [3:0] count;
reg
div1;
reg
div2;
always @( posedge clk )
begin
if ( ! reset_n )
count <= 3'b000;
else
case ( count )
3'b000 : count <= 3'b001;
3'b001 : count <= 3'b010;
3'b010 : count <= 3'b011;
3'b011 : count <= 3'b100;
3'b100 : count <= 3'b101;
3'b101 : count <= 3'b110;
3'b110 : count <= 3'b000;
default :
count <= 3'b000;
endcase
end
always @( posedge clk )
begin
if ( ! reset_n )
div1 <= 1'b0;
else if ( count == 3'b000 )
div1 <= ~ div1;
end
always @( negedge clk )
begin
if ( ! reset_n )
div2 <= 1'b0;
else if ( count == 3'b100 )
div2 <= ~ div2;
end
assign clkout = div1 ^ div2;
endmodule

80 VERILOG VHDL 10
module counter10(clk,rst,count);
input clk,rst;
output [3:0] count;
reg [3:0] count;
always@(posedge clk)
begin
if(!rst)
count<=0;
else if(count>=4d9)
count<=0;
else
count<=count+1;
end
endmodule
81

82 125 5
1 1 A=1 2 B=1 5 C=1 Y=1
2 S0 1 S1
2 S2 3 S3 4 S4
3 verilog
83 soda

1 fsm2 verilog fpga

84 10 5 10 1
fsm2 verilog fpga 3

1 A=1 5 B=1 10 Y=1 Z=1

2 S0 5 S1
85 10010 , verilog
1 data1 0 Y=1 10010
2 S0 0 S1,10 S2,010 S3,0010 S4
86 FSM 101101
a b a 101101 b 1 0
a 0001100110110110100110

b 0000000000100100000000
state machine RTL state machine
0 S01 S101 S2,101 S3,1101 S401101
S5 verilog

87 DRAM

88 OTP (OTP)

OTP OTP
OTP
OTP
OTP
(In System Programming) OTP Bonding

OTP OTP
I/O
ISP OTP
89
90
--------
-
91
TTLCMOS TTL CMOS
CMOS -
----

92 FPGA
FPGA/CPLD 7 ASIC
1.Verilog VHDL
2.ASCI
Sign-offPLD
3.
()
()
4.

5.
6.ASCI
Signoff
7. ASCI PLD

93 IC eda
--------(RTL )--
--()----)-(SDF )--(
)--------SDF ------
------

foundry fabless
IC zz
1.()

2. C/C++
MATLABSPW

3.
SystemC

4.RTL HDL RTL

VHDL Verilog HDL
5. RTL RTL RTL

6. RTL
7.

8. Floorplanning
PlacementRouting
9.
10.

11.
12.
IC
1. Cadance SE Foundry
I/O Pad ,,.lef.tlf .v
,
.gcf Pad DEFDesign Exchange Format( synopsys
Astro , , SDC ,Pad
--tdf

, .tf --technology file, Foundry I/O Pad

FRAM, CELL view, LM view (Milkway and DB, LIB file)

2.I/O Pad I/O Pad ,
,,
,Core ,Row Ring Strip
, PNA(power network analysis--IR drop and EM .
3. Placement -,I/O Pad
, SESilicon Ensemble DEF PC(Physical Compiler),PC
.DB ,
PC +Astro write_milkway, read_milkway
4. (CTS Clock tree synthesis),
,,

5. STA ,,
Global Route ,SE .V .SDF
PrimeTime ,
Astro , detail routing , starRC XT , E.V .SDF

 PrimeTime ,
6. ECO(Engineering Change Order),
.
7. filler (pad fliier, cell filler)Filler I/O Pad
,,I/O Pad I/O Pad ,
, DRC
8.(Routing)Global route-- Track assign --Detail routingRouting optimization
,
I/O Pad ,(Timing driven )
,--Timing report clear
9. Dummy Metal Foundry ,,
Dummy
Metal
10. DRC LVSDRC (spacing ,width),
,LVS ,
DRC LVS --EDA Synopsy hercules/
mentor calibre/ CDN Dracula .Astro also include LVS/DRC check commands.
11. Tape out GDS Foundry

94 RTL synthesis tape out flow, tool.

---

tapeout

In electronics, tape-out is the name of the final stage of the design of an integrated
circuit such as a microprocessor; the point at which the description of a circuit is sent for
manufacture.
95

1 foundry Pad
2
3 timing setup
4 100%
5 clock skew buffer
6
7 design rule foundry
dummy
Synopsys ASTROCadence SEISEQuartus II

96 0.25,0.18

/0.13,90,65
0.18 0.13
cpu 0.18 0.13 cpu
cpu 0.18
cpu 0.13 cpu 0.18

97
98
N P N

99 CMOS
CMOS
NMOS P N PMOS n-p-n-p

N
ESD latch-up

EOS
100 latch-up Antenna effect .
(polysilicon)

MOS