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Atlas
Programming Guide
Preliminary Revision 0.6, April 2003
1999-2003 Centrality Commnications, Inc. 2520 Mission College Blvd. Suite #103, Santa Clara, CA 95054
Table of Contents
1 Introduction ..........................................................................................................................................7 1.1 Documentation Conventions ........................................................................................................ 7 1.2 Referenced Documents................................................................................................................ 8 1.3 Architectural Overview.................................................................................................................. 9 1.4 Key Features .............................................................................................................................. 11 RISC Subsystem................................................................................................................................12 2.1 Operation Overview.................................................................................................................... 12 2.2 RISC Address Mapping .............................................................................................................. 12 2.3 Boot-up Control .......................................................................................................................... 14 2.4 Wait State Control ...................................................................................................................... 15 2.5 Write Pulse Control..................................................................................................................... 16 2.6 Timeout Control .......................................................................................................................... 17 DSP Subsystem.................................................................................................................................18 3.1 Operation Overview.................................................................................................................... 18 3.2 DSP Memory Address Mapping ................................................................................................. 19 3.3 DMA Operation........................................................................................................................... 20 3.3.1 Setting Memory Status ........................................................................................................ 20 3.3.2 Starting DMA Transfer......................................................................................................... 20 3.3.3 Endian Mode for DMA ......................................................................................................... 21 3.3.4 Byte Select Mode ................................................................................................................ 21 3.4 Controlling Peripherals ............................................................................................................... 23 3.5 DSP and RISC Cooperation ....................................................................................................... 24 3.5.1 RISC Control DSP by Interrupt ........................................................................................... 24 3.5.2 Data exchange between the RISC and the DSP ................................................................ 26 3.6 Differences between the DSP and ADIs ADSP2181................................................................. 27 3.6.1 Memory ............................................................................................................................... 27 3.6.2 Instructions .......................................................................................................................... 27 3.6.3 Biased-rounding mode ........................................................................................................ 27 3.6.4 Non-memory mapped registers........................................................................................... 27 3.6.5 Memory mapped registers................................................................................................... 27 3.6.6 Critical path limitation .......................................................................................................... 27 Dynamic Memory Interface ................................................................................................................29 4.1 Operation Overview.................................................................................................................... 29 4.2 Pin Sharing ................................................................................................................................. 30 4.3 Normal Operation ....................................................................................................................... 31 4.4 Wake-up Operation .................................................................................................................... 33 4.5 Clock Switching Operation ......................................................................................................... 34 4.6 Self-refresh Mode ....................................................................................................................... 35 Static memory Interface .....................................................................................................................36 5.1 Operation Overview.................................................................................................................... 36 5.2 Instruction Access Mode ............................................................................................................ 36 5.3 Direct Access Mode.................................................................................................................... 38 5.4 DMA Access Mode ..................................................................................................................... 39 5.4.1 DMA read ............................................................................................................................ 39 5.4.2 DMA write ............................................................................................................................ 40 Clocks and Power Manager...............................................................................................................47 6.1 Operation Overview.................................................................................................................... 47 6.2 Change Clock Source................................................................................................................. 48 6.3 Change Clock Ratio.................................................................................................................... 49 6.3.1 Change the System and I/O Clock Ratio ............................................................................ 49 6.3.2 Change the External Memory Clock Ratio .......................................................................... 49 6.4 Change PLL Frequency.............................................................................................................. 51 6.5 Power Mode ............................................................................................................................... 52
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 6.5.1 Normal Mode....................................................................................................................... 52 6.5.2 Turbo Mode ......................................................................................................................... 52 6.5.3 Idle Mode............................................................................................................................. 52 6.5.4 Standby Mode ..................................................................................................................... 53 6.5.5 Sleep Mode ......................................................................................................................... 53 7 GPIO ..................................................................................................................................................55 7.1 Operation Overview.................................................................................................................... 55 7.2 Configure GPIO Pin Sharing ...................................................................................................... 56 7.3 Configure GPIO as Input ............................................................................................................ 57 7.4 Configure GPIO as Output ......................................................................................................... 58 7.5 Configure GPIO as Open-Drain ................................................................................................. 59 7.6 Configure GPIO as Wake-up Source ......................................................................................... 60 7.7 Configure GPIO to be Accessed by DSP ................................................................................... 61 8 Resource Sharing Controller .............................................................................................................62 8.1 Operation Overview.................................................................................................................... 62 8.2 DMA Channel Sharing................................................................................................................ 63 8.3 External Pin Multiplex ................................................................................................................. 64 9 DMA Controller ..................................................................................................................................66 9.1 Operation Overview.................................................................................................................... 66 9.2 Initialization ................................................................................................................................. 67 9.3 DMA Interrupt Handling .............................................................................................................. 69 9.4 Single and Burst DMA ................................................................................................................ 70 9.5 1-D and 2-D DMA ....................................................................................................................... 71 9.6 Loop DMA................................................................................................................................... 73 9.7 DSP Control of DMA................................................................................................................... 76 10 PCMCIA Interface ..............................................................................................................................77 10.1 Operation Overview ................................................................................................................ 77 10.2 Pin-mux Programming ............................................................................................................ 78 10.3 M6730 Register Programming................................................................................................ 79 10.4 Power Logic Register Programming ....................................................................................... 81 10.5 Memory Window Configuration............................................................................................... 82 10.6 I/O Window Configuration ....................................................................................................... 83 10.7 Timing Control......................................................................................................................... 84 10.8 Management Interrupt Operation............................................................................................ 84 10.9 Card Interrupt Operation ......................................................................................................... 86 10.10 Socket Initialization Sequence................................................................................................ 87 11 Extension port ....................................................................................................................................88 11.1 Operation Overview ................................................................................................................ 88 11.2 Pin-mux Programming ............................................................................................................ 89 11.3 Timing Register Programming ................................................................................................ 90 11.4 Fixed Latency Access ............................................................................................................. 91 11.5 Variable Latency Access......................................................................................................... 92 11.6 DSP Access ............................................................................................................................ 93 12 Universal Serial Port ..........................................................................................................................94 12.1 Operation Overview ................................................................................................................ 94 12.2 USP Reset and Power up ....................................................................................................... 95 12.3 USP Initialization..................................................................................................................... 96 12.3.1 USP Work Mode Initialization.............................................................................................. 96 12.3.2 Sample Code of USP Initialization ...................................................................................... 99 12.4 USP Transmitting Operation ................................................................................................. 105 12.4.1 I/O Mode Transmit by Interrupt ......................................................................................... 105 12.4.2 I/O Mode Transmit by Polling FIFO Status ....................................................................... 105 12.4.3 DMA Transmitting Mode.................................................................................................... 105 12.5 USP Receiving Operation ..................................................................................................... 107 12.5.1 I/O Mode Receiving by Interrupt ....................................................................................... 107 Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE -2-
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 12.5.2 I/O Mode Receiving by Polling FIFO Status...................................................................... 107 12.5.3 DMA Recieving Mode........................................................................................................ 108 12.6 Interralation of Transmitting and Receiving .......................................................................... 109 12.6.1 Independent Operation for Transmitting and Receiving ................................................... 109 12.6.2 concurrent Operation for Transmitting and Receiving ...................................................... 109 12.6.3 Alternate Operation for Transmitting and Receiving ......................................................... 109 12.7 Pin I/O Mode Operations ...................................................................................................... 109 12.8 USP Reconfiguration ............................................................................................................ 111 12.9 SIB Initialization .................................................................................................................... 112 12.10 SIB Operations...................................................................................................................... 114 12.10.1 Register Writing ............................................................................................................. 114 12.10.2 Register Reading ........................................................................................................... 114 12.10.3 Audio Data Transfer....................................................................................................... 114 12.10.4 Telecom Data Transfer .................................................................................................. 115 13 Audio CODEC Interface...................................................................................................................116 13.1 Operation Overview .............................................................................................................. 116 13.2 AudioCODEC Controller Initialization ................................................................................... 117 13.3 AC97 CODEC Configuration................................................................................................ 118 13.4 I2S CODEC Configuration .................................................................................................... 122 14 Camera Interface .............................................................................................................................124 14.1 Operation Overview .............................................................................................................. 124 14.2 Initialize Operations .............................................................................................................. 125 14.2.1 Initialize Camera Interface ................................................................................................ 125 14.2.2 Camera Interrupt Operation .............................................................................................. 125 14.3 DMA Operations ................................................................................................................... 127 14.3.1 Initialize DMA Interface ..................................................................................................... 127 14.3.2 DMA Interrupt Operation ................................................................................................... 127 14.3.3 DMA operation .................................................................................................................. 128 14.4 Sensor Operations ................................................................................................................ 129 14.4.1 Initialize Sensor Control Module ....................................................................................... 129 14.4.2 Sensor Clock Operation .................................................................................................... 129 14.4.3 Capture Image Operation.................................................................................................. 129 14.4.4 Slave Mode Operation....................................................................................................... 130 14.4.5 Pixel Data Shift Operation................................................................................................. 131 14.4.6 Inverse Control Operation ................................................................................................. 132 14.4.7 Sample Pixel Clock Operation .......................................................................................... 132 14.4.8 Master Mode Operation..................................................................................................... 133 14.5 I2C Master Operations.......................................................................................................... 135 14.5.1 Initialize Unit ...................................................................................................................... 135 14.5.2 Write n Bytes to External Device....................................................................................... 135 14.5.3 Read n Bytes from External Device .................................................................................. 136 14.6 I2C Slave Operations............................................................................................................ 137 14.6.1 Initialize Unit ...................................................................................................................... 137 14.6.2 Normal Operation .............................................................................................................. 137 14.7 Quick Reference ................................................................................................................... 138 15 USB 1.1 Device Interface ................................................................................................................139 15.1 Operation Overview .............................................................................................................. 139 15.2 Initialization ........................................................................................................................... 141 15.3 Control Transfer .................................................................................................................... 143 15.4 I/O Operation ........................................................................................................................ 145 15.5 DMA Operation ..................................................................................................................... 147 15.6 Quick Reference ................................................................................................................... 149 16 Host Port Interface ...........................................................................................................................150 16.1 Operation Overview .............................................................................................................. 150 16.2 Address Mapping .................................................................................................................. 151 Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE -3-
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 16.3 Initialization ........................................................................................................................... 152 16.4 I/O & DMA Operation ............................................................................................................ 155 16.5 Handshaking with Host ......................................................................................................... 157 17 Secure Disk (SD) / Multi-Media Card Interface (MMC) ...................................................................158 17.1 Operation Overview .............................................................................................................. 158 17.2 Internal Regsiter Programming............................................................................................. 159 17.3 I/O Operation ........................................................................................................................ 160 17.4 DMA Operation ..................................................................................................................... 161 17.5 Initialization ........................................................................................................................... 162 17.6 No Data Command/Response Transaction .......................................................................... 163 17.7 Single Block Operation ......................................................................................................... 164 17.7.1 Single Block Write ............................................................................................................. 164 17.7.2 Single Block Read ............................................................................................................. 164 17.8 Multiple Block Operation ....................................................................................................... 165 17.8.1 Multiple Block Write........................................................................................................... 165 17.8.2 Multiple Block Read........................................................................................................... 165 17.8.3 Multiple Block Write Using Number Blocks ....................................................................... 166 17.8.4 Multiple Block Read Using number Blocks ....................................................................... 166 18 Nand Flash Memory Interface .........................................................................................................167 18.1 Operation Overview .............................................................................................................. 167 18.2 Initialization ........................................................................................................................... 167 18.3 I/O Operation ........................................................................................................................ 167 18.3.1 IO Read ............................................................................................................................. 167 18.3.2 IO Write ............................................................................................................................. 168 18.4 DMA Operation ..................................................................................................................... 168 18.5 DMA read example ............................................................................................................... 169 18.6 DMA write example............................................................................................................... 169 18.7 NAND Boot-loader ................................................................................................................ 170 18.7.1 ARM Init Process............................................................................................................... 171 18.7.2 Flash Controllers global register init process ................................................................... 172 18.7.3 Read Device ID ................................................................................................................. 172 18.7.4 Search File NK.BIN......................................................................................................... 172 18.7.5 Read NK.BIN and Parse It .............................................................................................. 172 18.8 Special Notes........................................................................................................................ 173 19 LCD Controller Interface ..................................................................................................................174 19.1 Operation Overview .............................................................................................................. 174 19.2 Initialization ........................................................................................................................... 174 19.3 DMA Operation ..................................................................................................................... 176 19.4 Configuration Comparison for Different Mode ...................................................................... 177 19.5 Palette ................................................................................................................................... 178 19.5.1 Color Palette...................................................................................................................... 178 19.5.2 Grey Palette of FRC Sequence......................................................................................... 178 19.6 Special Register Configuration ............................................................................................. 179 19.6.1 Pixel Clock Divider ............................................................................................................ 179 19.6.2 FIFO Request Watermark Control .................................................................................... 179 19.7 Power Sequence / Back Light Control for LCD Displays...................................................... 179 20 Revision History ...............................................................................................................................180
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Atlas Block Diagram .......................................................................................................... 9 DSP Byte Select Mode........................................................................................................ 22 Data Mapping in 8-bit External Data Bus ............................................................................ 37 Data Mapping in 16-bit External Data Bus .......................................................................... 37 Static Memory Interface Simple WriteTiming ...................................................................... 41 Static Memory Interface Fixed Sequence WriteTiming....................................................... 43 Static Memory Interface Fixed Sequence WriteTiming....................................................... 45 Atlas Pin Multiplex Diagram............................................................................................. 64 2-D DMA.............................................................................................................................. 71 2-D DMA Wrap Around (X-Length > Width)........................................................................ 72 Loop-mode DMA ................................................................................................................. 73 NAND Boot Flow Diagram................................................................................................. 171
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List of Tables
Table 1. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Reference Documents .............................................................................................................. 8 DSP memory address mapping.............................................................................................. 19 DSP memory usage guide ...................................................................................................... 20 DSP peripheral registers address mapping ............................................................................ 23 Staitic Memory Chip Select Mapping...................................................................................... 36 Staitic Memory Chip Select Mapping...................................................................................... 39 Atlas DMA Channel Multiplex.............................................................................................. 63 Atlas Pin Multiplex ............................................................................................................... 64 Pixel Shift Number vs DMA Register Setting .................................................................... 138 USB Device Endpoint Configuration ................................................................................. 149 Differences between Master and Slave Mode .................................................................. 178 FRC Sequence Table Example......................................................................................... 178
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1 Introduction
This document detailed descriptions and examples of programming and developing using the Centrality Communications Atlas Processor. It is intended for the use of Centrality customers, partners, and other interested parties to gain a detailed understanding of Centralitys technology and architecture for design purposes. Detailed programming guide, flow chart, and sample code are contained in this manual to provide the user with a solid background.
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LCD Controller
Memory Controller
Bluetooth Baseband
GPS Baseband
Serial Ports
Camera Interface
SD/MMC Interface
PCMCIA/CF Host/Slave_
Extension Port
Bluetooth RF
GPS RF
IrDA, UART CMOS/CCD NAND Flash USB Host Sensor Smartmedia CODEC, Tch-Scrn
SD/MMC Card
Figure 1.
RISC Core Atlas has an integrated ARM922T core with the AMBA ASB bus. The RISC acts as a controller, which controls the other functional blocks via writing/reading memory-mapped registers. The RISC accesses external memory via the memory bus and acts as a bus master. DSP Core Most of the computation required for the multimedia and communication applications can be performed in the Digital Signal Processor (DSP). The advantages of using a DSP include an increase in the computation horsepower, effectiveness, and reduced memory footprint and bandwidth. The DSP operates independent from the RISC processor and contains its own program and data memory space. The DSP is also a bus master and can DMA data to/from external memory via the memory bus. However, the DSP is controlled by the RISC processor through a shared register file. The RISC processor can write commands into the register file and start/stop DSP programs. The DSP can also write to the register file and transfer data/status to the RISC. The RISC and DSP can symbiotically interrupt each other. Both the RISC and the DSP can read/write to memory-mapped control registers to configure or read the status of a peripheral block. This accesses takes place on two distinct buses, the RISC I/O Bus (RBUS) and DSP I/O Bus (DBUS). Each block has a Control Register Interface to decode the register accesses from the RISC and DSP and resolve any potential conflict. (Note: The RISC and the DSP can simultaneously read/write two separate registers, as long as they are not in the same functional block). System Memory Bus The system memory bus is a 32-bit high-performance, low-power bus. In the Atlas architecture, there are 4 bus masters: RISC, DSP, I/O Bridge, and LCD Controller. The Bus Arbitrator arbitrates requests of the four bus masters and directs the appropriate accesses to the single system memory bus slave the Memory Controller. Memory Controller
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE The Memory Controller controls all access to external memory. The Memory Controller supports SDRAM as the main memory for program and data storage during the chips normal operational mode. During boot, the RISC processor will first transfer the code stored in Flash memory to the program space in the SDRAM. After boot-up, the Flash memory can be considered as a peripheral device. Peripheral Subsystem Atlas is a multi-functional platform, so it contains several peripheral interface blocks: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 16 channel GPS baseband Bluetooth baseband USB device interface NAND Flash/Smart Media interface CMOS/CCD sensor interface NOR Flash/ROM interface Universal Serial Ports Audio CODEC interface SD/MMC interface LCD interface
All of these interface blocks have the same functionality: they each provide a means to transfer data between Atlas and an external device. There are two types of transfer: I/O read/write and DMA. Some blocks only support I/O read/write, such as the Bluetooth and GPS blocks. Some blocks support both I/O read/write and DMA, such as the serial port, CMOS sensor, NAND Flash/Smartmedia, Flash/ROM, SD/MMC and USB interface. Each peripheral has its own SRAM FIFO. The I/O read/write can be executed by either the RISC or DSP, via the RBUS or DBUS respectively. The DMA can be executed via the I/O memory bus. The peripheral blocks with DMA channel will connect to the I/O Bridge via the I/O memory bus. The I/O Bridge is responsible for the arbitration of the DMA requests from the peripherals. But it can only grant the I/O memory bus to the peripheral when it's granted the system memory bus from the Bus Arbiter.
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120MHz DSP core for optimized low-power acceleration for: MP3, Image Video compression and processing, GPS, VOIP, and MIDI o o 2Kx24bit Program Memory 3Kx16bit Data Memory
16 channel GPS baseband specific hardware Bluetooth baseband specific hardware CMOS/CCD sensor interface NAND Flash support with integrated Bootloader 100MHz SDRAM bus with support for 2.5V Mobile SDRAM Graphic LCD controller with UMA for Active TFT and monochrome LCD panels Advanced power management features including dynamic Processor Voltage Scaling, finegrained clock-gating to dynamically turn off peripherals USB 1.1 device 4 Universal serial ports Multiple card support: PCMCIA, SmartMedia, SD, MMC, Compact Flash, etc. 28 General-purpose I/O and 116 programmable I/O 291 pin TFBGA (16x16mm)1 package Low-power 0.18u CMOS
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2 RISC Subsystem
2.1 Operation Overview
The RISC Subsystem includes an ARM922T RISC core (with 8KB I-Cache and 8KB D-Cache) and a RISC interface. The RISC interface can translate the ARM922T bus cycles into Atlas internal system bus cycles. There are two types of basic bus cycle of ARM922T: I/O cycle and Memory cycle. Its decided by the address to define if a RISC bus cycle is I/O or Memory cycle. The I/O cycle will be transferred to the internal RISC I/O bus (RBUS). And the Memory cycle will be transferred to the internal system memory bus (MBUS). All buses mentioned above are in 32-bit.
Table 2.
System Memory Mapping Address Range Usage E800_0000~FFFF_FFFF Reserved E000_0000~E7FF_FFFF Zero Bank C000_0000~DFFF_FFFF System Memory 8000_0000~BFFF_FFFF Internal Registers 5000_0000~7FFF_FFFF Reserved 4800_0000~4FFF_FFFF DSP Shared Memory 4000_0000~47FF_FFFF Extension Port 3000_0000~3FFF_FFFF PCMCIA Socket 1 2000_0000~2FFF_FFFF PCMCIA Socket 0 0000_0000~1FFF_FFFF Flash/ROM
Resource Size 384MB 128MB 512MB 1GB 768MB 128MB 128MB 256MB 256MB 512MB
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Among those groups, WS0~WS3 are used to insert wait states for the blocks in system clock domain. While WS4~6 are used to insert wait states of the blocks in I/O clock domain. WS7 is used for only Bluetooth Baseband because its the only asynchronous device of the whole chip. Because each group of wait state register bits are shared among several devices (except for WS7), those devices will always have the same wait states setting. That is to say, if user want to increase wait states for one block, then the other blocks in the same group will all have more wait states.
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3 DSP Subsystem
3.1 Operation Overview
The DSP used in Atlas processor acts as a acceleration computational parts for GPS, MP3, Image processing etc. The DSP core is provided by Faraday Technology Corp. and is instruction compatible with ADIs ADSP2181 except for minor differences. The DSP is an independent processor. It has its own program and data memory. The RISC core can read/write data throught its IDMA port and can interrupt the DSP. The DSP can do data exchange between its data or program memory and SDRAM by operating the DMA controller of DSP interface. It can also control some of the peripherals such as DMA controller, serial port interface, interrupt controller, GPIO and extension interface by accessing the peripherals registers.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE NOTE3: X length is count of double word. But for PM, a 24bit WORD is treated as a 32bit double word and valid data is in lower 24 bits. A serial of macros can be defined to simplify programming. The following is an example to do DMA between DMX-swap and SDRAM without waiting it completed. { do DMA transfer without waiting it complete} { syntax: transfer_dm_nowait(READ_DM/WRITE_DM, sdram_hi, sdram_lo, sram, xlen, ylen); } { READ_DM is defined as 13 (2b1101), WRITE_DM is defined as 5 (2b0101) } .macro transfer_dm_nowait(%0, %1, %2, %3, %4, %5); i0 = DSPDMA_LENGTH_X; dm(i0, m1) = %4; { xlength } dm(i0, m1) = %5; { ylength } dm(i0, m1) = %2; { SDRAM address low } dm(i0, m1) = %1; { SDRAM address high } ar = %3; { SRAM address } dm(DMX_START_ADD) = ar; ar = %0; dm(DSPDMA_MODE) = ar; { do transfer } .endmacro; The following macro waits the DMA completed. { wait for transfer complete } .macro wait_trans; .local transfer_loop; transfer_loop: ar = dm(DSPDMA_MODE); ar = tstbit 0 of ar; if ne jump transfer_loop; .endmacro;
{ completed? }
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE the lowest 2 bit of SDRAM address as byte selection, load data from the selected byte address and read four bytes each time. It will use the following method (assume lowest two bit of SDRAM address is 01): First, four bytes aligned to DWORD boundary will be read in as A0 A1 A2 A3, A0 will be discarded and last three bytes A1 A2 A3 will be put into storage registers S0 S1 S2. Then the second DWORD B0 B1 B2 B3 will be read in, B0 will concatenate to the storage registers to form a four-bytes DWORD and be written into DMX-swap, last three bytes B1 B2 B3 will be put into storage registers. And this process continuous with third read in DWORD appends C0 to B1 B2 B3 then store C1 C2 C3 etc. The total result is x length multiply 4 numbers of bytes transfered to DMX from SDRAM at address which contains data A1. If the lowest 2 bit of SDRAM is 10, data will transfer to DMX-swap from A2, if the lowest 2 bit of SDRAM is 11, data will transfer to DMX-swap from A3. This method is useful while loading data from unaligned address. When lowest two bit is 00, it will act as byte select not enabled, when lowest two bit is not 00, x length should be increased by 1 to ensure actual number of DWORD written to DMX-swap is x length. Data In: A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3
Discarded (Optional)
S0 S1 S2
S0 S1 S2
S0 S1 S2
A1 A2 A3 B0 Data In: A0 A1 A2 A3 D0 D1 D2 D3 G0 G1 G2 G3 Data out: A1 A2 A3 B0 D1 D2 D3 E0 G1 G2 G3 H0 B1 B2 B3 C0 E1 E2 E3 F0 H1 H2 H3 I0 C1 C2 C3 X0 F1 F2 F3 Y0 I1 I2 I3 Z0 S0 S1 S2 DSP Byte Select Mode = Storage registers B0 B1 B2 B3 E0 E1 E2 E3 H0 H1 H2 H3 C0 C1 C2 C3 F0 F1 F2 F3 I0 I1 I2 I3 B1 B2 B3 C0
Figure 2.
The discard operation after the first read is optional. Normally, the first few bytes should be discarded. But if the second DMA transfer need to concatenate data to the first DMA (for example, load data from a circular buffer in SDRAM, the first transfer passes the end of buffer and the second transfer concatenate the first one from the beginning of the buffer), the second DMA should not discard the first read in data and data in storage registers.
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NOTE: The DMA controller refers to the systems DMA controller. It is different from the DMA controller of the DSP interface which only do DMA between SDRAM and the DSPs memory. Read or write these registers with normal data memory access instructions and IO instructions. On default, peripherals are controlled by RISC. Each peripheral has its own control bit to determine whether it is controlled by the RISC or controlled by the DSP. When one peripheral is controlled by the RISC, the DSP can not access its registers. Peripheral can interrupt the DSP, the interrupt are connected to the DSPs IRQ2 input and can be set to either level trigger or edge trigger. For details of how to operate each peripheral, refer to the programming guide of corresponding peripheral.
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Following is example code of how to control the DSP // Enable DSP interrupt INT_RISC_MASK |= INT_MASK_DSP; // reset DSP interface RESET_SR |= RESET_SR_DIFACE_RST; // enable DSP core and DSP interface clock PWR_CLK_EN |= PWRCLK_DSP_EN; // reset DSP RESET_SR |= RESET_SR_DSP_RST; // release DSP reset signal RESET_SR &= ~RESET_SR_DSP_RST; // release DSP interface reset signal RESET_SR &= ~RESET_SR_DIFACE_RST; // Allow Risc access DMA register DSPREG_MODE = 1; // Set UP SRAM OE DSPDMA_MODE = 0x30000; // Allow DSP access DMA register DSPREG_MODE = 0; for (i = 1; i < pm_in_size; i ++) ProgramMemory[I] = pm_in_code[i]; WritePM(0, pm_in_code[0]); DspInt = 0; RISC_INT_DSP = (unsigned)routine_entry; while(!DspInt); The variable DspInt is a volatile variable, which should be set to no-zero in the RISCs interrupt service routine when receiving an interrupt from the DSP.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE On the DSP side, if nothing need to be done, DSP should be in IDLE mode to save power. Program should accept interrupt from the RISC and run the routine code. After it finished the routine, send an interrupt to RISC. The DSP should be programmed by the following sequence. 1. 2. 3. 4. 5. Enable interrupt of IRQ2, IRQL1 and other IRQ bits needed. Enter the IDLE mode by executing idle instruction to wait an interrupt occur. If the interrupt is from IRQL1 (eg. The RISC interrupts the DSP), jump to the subroutine with the entry address given by the RISC. After the subroutine completed, inform the RISC by sending an interrupt. Go back to IDLE mode and wait for the next interrupt.
An example is given as following. .module/ram/abs=0/seg = pm_in PM_IN_PROG; .entry Subroutine; StartDSP: nop; imask = 0x0300; ena ints; jump idle_loop;
irq2_srv: jump irq2_int_srv; nop; nop; nop; irql1_srv: ar = 1; dm(GEN_REG2_L) = ar; rti; nop; idle_loop: icntl = 0x5; /* set irq2 edge */ idle; ar = dm(GEN_REG2_L); ar = pass ar; if eq jump idle_loop; i4 = dm(RISC_INT_DSP); jump (i4); return_addr: ar = 0; dm(DSP_INT_RISC) = ar; jump idle_loop; irq2_int_srv: ena sec_reg; ar = 0; dm(GEN_REG2_L) = ar; dis sec_reg; rti; Subroutine: /* execute program */ /* when completed return by executing the following sentence */ jump return_addr; Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 25 -
.endmod NOTE: General purpose register GEN_REG2_L is used to differentiate interrupts from the RISC and from the peripheral. If the interrupt is from peripheral, when go back from the interrupt service routine, the DSP should directly go back to IDLE mode.
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3.6.1 Memory
As described above, the DSPs internal memory are divided into three separate parts. Because instructions accessing program memory are actually accessing the 16bit program-data memory, so there is no PX register. Writing to PX register is a null operation, and reading from PX register always gets 16bit zero value.
3.6.2 Instructions
Some of the ADSP2181 instructions are not supported in the DSP. These instructions will be treated as NOP. These non-supported instructions are listed in the following: Call or Jump on Flag In Modify Flag Out ENA INTS and DIS INTS
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE effective data on data bus at the next cycle of read, while it should be put on the address bus at the same cycle. The existing of critical path limites program with such instruction combination can not run over 120MHz. Programmer should eleminate critical path instructions by inserting NOP or changing instruction sequence.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 1) MEMC_SDCFG<3:0> defines the Number of chip select signals used. For example, 2 group of SDRAM are used (2 chip select): MEMC_SDCFG<3:0> = 0xC. 2) All other register are for test purpose and should be written as 0 If program is booting on static memory interface or NAND flash, the SDRAM can be configured as following. The MEMC_POWER register needs to be programmed to initialize SDRAM. //Configure System clock. MEMC_SDTIM=0xB85D7222; MEMC_CONFIG=0x200; MEMC_SDCFG=0xc; MEMC_POWER=0x4F;
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE //Change refresh period in MEMC_SDTIM for performance only.
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When powered up, the central processor will boot up from the static memory interface. It will execute boot code on the Flash or ROM. The boot code will read and copy the program from the Flash or ROM into main system memory (SDRAM). In other words, in boot-up mode, the Flash/ROM will be shadowed as part of system memory. However, after boot-up, the static memory interface can also be file related, such as a storage device. During boot-up, the static memory interface is mapped to the bottom of system address starting from 0x0000 0000. The code in the Flash or ROM should have an appropriate boot-loader at the base address. The processor will execute the boot-loader first, during which it will configure the SDRAM and initialize the hardware properly. The boot-load code will then copy the program code into system memory. Two methods are available to execute this copy: The processor can read a chunk of 32-bit word from the static memory interface directly and then it write the word to the system memory. -- or -The processor can configure the static memory interface into DMA mode and wait until DMA finishes.
After boot-up, the static memory interface can be considered a simple I/O device. It has a dedicated DMA channel for data transfer to/from SDRAM. Most operations related to static memory will be act like "file related" operations. For example, the system can save an image file into the Flash, just like it would a regular storage device. Besides access through DMA, the processor may still be able to access the static memory interface via memory mapped addresses. This comes in extremely useful since some FAT related operations do not need to be done through DMA. In summary, the static memory interface will have two operation modes after boot-up: memory mapped access ( direct access) and DMA. The static memory interface register should be properly programmed for these different operational modes. In DMA mode, the static memory interface uses DMA channel 4.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Chip select 2 Chip select 3 0x1800_0000 ~ 0x1bFF_FFFF 0x1C00_0000 ~ 0x1FFF_FFFF
After reset, the address space from 0x0000_0000~0x0FFF_FFFF is shadowed with 0x1000_0000 ~ 0x1FFF_FFFF. RISC will fetch the first instruction from address 0x0000_0000. When NAND_BOOT is pulled-low, it is redirect to Static memory chip select 0. In this mode, all the read are 32-bit wide. For different Static Memory Interface bit width, the 32-bit DWORD is mapped as little endian, which is shown in the following figures:
D<31:24> {A<23:2>, 2b00} D<23:16> D<31:24> D<23:16> D<15:8> D<7:0 > D<15:8> D<7:0 > Internal Data Bus (32-bit) {A<23:2>, 2b10} {A<23:2>, 2b01} {A<23:2>, 2b00} {A<23:2>, 2b11}
Figure 3.
{A<23:2>, 2b00} D<31:24> D<23:16> D<15:8>
Figure 4.
In Instruction Access Mode any write command from RISC is ignored by the Static Memory Interface.
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For 8bit width Static Memory Interface, user can only use 8-bit access in software, other access will cause unknown operation on the Static Memory Interface. For 16bit width Static Memory Interface, user can only use 16-bit access in software, other access will cause unknown operation on the Static Memory Interface. The mapping from internal data access to static memory is the same in Instruction Access mode. Following sample code is used to access 8-bit width FLASH. char FlashData; int FlashAddress; // Configure chip select 1 as direct access mode, 8 bit width ROM_CFG_CS01= ROM_CFG_CS01 &0xFFFCFFFF; FlashAddress=0x1; // Direct read data from offset 0x01 in chip select 1 FlashData = (*((volatile unsigned char *)(0x14000000 + FlashAddress))); // Perform a direct write to offset 0x01 in chip select 1 (*((volatile unsigned char *)(0x14000000+ FlashAddress))) = FlashData ; Following sample code is used to access 16-bit width FLASH. In 16-bit access, the offset address should be multiple of 2, because the address 0 is always zero in 16-bit width mode. short FlashData; int FlashAddress; // Configure chip select 2 as direct access mode, 8 bit width ROM_CFG_CS23 = (ROM_CFG_CS23 & 0xFFFFFFFC ) | 0x1 ; // Direct read data from offset 0x02 in chip select 2 FlashAddress=0x2; FlashData = (*((volatile unsigned short *)(0x18000000 + FlashAddress))); // Perform a direct write to offset 0x01 in chip select 1 (*((volatile unsigned short *)(0x18000000 + FlashAddress)))= FlashData ;
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//configure dma and start dma,(the rom is not started yet, so no problem) DMA_WIDTH0 = 0xfff;//using DMA_WIDTH0 DMA_CH4_XLEN = 32; //Transfer 32 DWORD DMA_CH4_YLEN = 0x00; DMA_CH4_CTRL = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_TO_SDRAM); DMA_CH4_ADDR = (0x200000); //DMA start address in SDRAM //configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 39 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE // Chip Select 1 use 16 bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; ROM_DMA_IO_LEN_REG = 32*2; //16 bit width , Transfer 32 DWORD ROM_START_ADD = 0x2000000 ; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x06;// DMA, FLUSH // This is the FIFO_CTRL register setting for Static Memory Interface ROM_FIFO_CTRL_REG=0xFC; // set FIFO level check ROM_FIFO_LEVEL_CHK_REG = ( ( 0xa << 20 ) | ( 0x8 << 10 ) | ( 0x4 ) ); //start read DMA ROM_FIFO_OP_REG=0x01; //wait for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 );
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X_FCE_B
FWE_B
FA FD
SA1 FD1
Figure 5.
Notes: SA0, SA1 are address from ROM_START_ADDR. FD0, FD1 are data from FIFO. Depending on Interface Width, one 32-bit data in FIFO will be splitted into 2 or 4 FD. The data in FIFO is ordered as little endian. Following sample code is for DMA Simple Write. #define DMA_MASK_BURST #define DMA_MASK_WIDTH_0 #define DMA_MASK_FROM_SDRAM unsigned int twc; DMA_WIDTH0 = DMA_CH4_XLEN DMA_CH4_YLEN DMA_CH4_CTRL DMA_CH4_ADDR 0xfff; //using DMA_WIDTH0 only = 32; = 0x00; = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_FROM_SDRAM); = 0x100000;//Start address of dat in SDRAM; 0x08 0x00 0x04
//configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register // Chip Select 1 use 16-bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; ROM_DMA_IO_LEN_REG = 32*2; //16 bit width, Transfer 32 DWORD ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory , no flush ROM_FIFO_CTRL_REG=0x00; ROM_FIFO_LEVEL_CHK_REG=(0xb);//fifo level check //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff; Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 41 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE ROM_WRITE_CTRL= ( ((0)&(0x3))<<12 | ((0)&(0x1))<<11 | ((1)&(0x7))<<8 | (twc)&(0xff) ); //start dma ROM_FIFO_OP_REG=0x1; //waiting for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 ) { }; }
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X_FCE_B
FWE_B
FA FD
SEQ0
SEQ1
SA0
SEQ0
SEQ1
SA1
SEQ0
SEQ1
FD0
SEQ0
SEQ1
FD1
T twc
Figure 6.
Notes: SEQ0, SEQ1 are data and address from ROM_WRITE_SEQ0, ROM_WRITE_SEQ1 SA0, SA1 are address from ROM_START_ADDR. FD0, FD1 are data from FIFO. Depending on Interface Width, one 32-bit data in FIFO will be splitted into 2 or 4 FD. The data in FIFO is ordered as little endian. User needs to change the configure of ROM_WRITE_CTRL In the previos sample code. And add the configuration of registers ROM_WRITE_SEQ<1:0>. #define DMA_MASK_BURST #define DMA_MASK_WIDTH_0 #define DMA_MASK_FROM_SDRAM unsigned int twc; DMA_WIDTH0 = DMA_CH4_XLEN DMA_CH4_YLEN DMA_CH4_CTRL DMA_CH4_ADDR 0xfff; //using DMA_WIDTH0 only = 32; = 0x00; = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_FROM_SDRAM); = 0x100000;//Start address of dat in SDRAM; 0x08 0x00 0x04
//configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register // Chip Select 1 use 16-bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; ROM_DMA_IO_LEN_REG = 32*2; //16 bit width, Transfer 32 DWORD ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory , no flush Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 43 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE ROM_FIFO_CTRL_REG=0x00; ROM_FIFO_LEVEL_CHK_REG=(0xb);//fifo level check //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff; ROM_WRITE_CTRL= (((2)&(0x3))<<12 | ((0)&(0x1))<<11 | ((3)&(0x7))<<8 | (twc)&(0xff)); ROM_WRITE_SEQ0 = sequence0; ROM_WRITE_SEQ1 = sequence1; //start dma ROM_FIFO_OP_REG=0x1; //waiting for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 );
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X_FCE_B
FWE_B
FA FD
FA0
FA1
FA3
FA4
FA5
FA6
FD0
FD1
FD3
FD4
FD5
FD6
T twc
Figure 7.
Notes: FA0 FA6, FD0 .. FD6 are data from FIFO. Each 32-bit data in FIFO only contain only FA or on FD. ROM_START_ADDR, ROM_WRITE_SEQ<2:0> registers will not be used in this mode. Their value will be unknown. Following code is the sample for DMA variable sequence write. #define DMA_MASK_BURST #define DMA_MASK_WIDTH_0 #define DMA_MASK_FROM_SDRAM unsigned int twc; DMA_WIDTH0 = DMA_CH4_XLEN DMA_CH4_YLEN DMA_CH4_CTRL DMA_CH4_ADDR 0xfff; //using DMA_WIDTH0 only = 32; = 0x00; = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_FROM_SDRAM); = 0x100000;//Start address of dat in SDRAM; 0x08 0x00 0x04
//configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register // Chip Select 1 use 16-bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; //16 bit width, Transfer 32 DWORD, both data and address are get from FIFO ROM_DMA_IO_LEN_REG = 32*2*2; ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory, no flush ROM_FIFO_CTRL_REG=0x00; Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 45 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE ROM_FIFO_LEVEL_CHK_REG=(0xb);//fifo level check //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff; ROM_WRITE_CTRL= (((0)&(0x3))<<12 | ((1)&(0x1))<<11 | ((3)&(0x7))<<8 | (twc)&(0xff)); //start dma ROM_FIFO_OP_REG=0x1; //waiting for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 );
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During the Atlas boot-up, the following clock switching steps need to be followed: After reset, both PLL1 and PLL2 are in power-down mode, and will be bypassed by the system clock. The clock will use the 12MHz oscillator by default. The boot-up program will set up the clock configuration registers (PWR_PLL1_CONFIG) and turn on the PLL. After the PLL is stable, the boot-up program will switch the clock from the 12MHz oscillator to the PLL.
NOTE: Before switch the clock source to PLL, make sure the PLL has already powered up and stable. Here is an example to switch the clock source to PLL1: //All clocks switch to pll1 PWR_CLK_SWITCH = 0x55; for (i=1;i<=10;i++); NOTE: Its suggested to delay for several cycles for the operations for waiting the clock switch finishes. In some cases, the whole system can run from a single clock source and the other unused PLL(s) can be powered down to save power.
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ARM922T has three different clocking modes: Fast Bus mode, Synchronous mode, and Asynchronous mode. Please refer to the ARM922T datasheet for more details.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE The capability of changing the clock ratio provides a further tunning of performance/power ratio. For example, for those applications do not need high memory bandwidth but has intensive DSP calculations, then we can configure the memory clock to be half of the system clock. NOTE: To change the external memory clock ratio must be done when program is running either on Flash/ROM or in Instruction Cache. Otherwise, unexpected result may happen.
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Here is a basic example showing the above programming steps: // Switch the clock source to PLL2 PWR_CLK_SWITCH=0xAA; for(i=1;i<=10;i++); // Stop PLL1 PWR_CLK_CTRL = 0x2; // Configure PLL1 PWR_PLL1_CONFIG = 0x3099; // Start PLL1 PWR_CLK_CTRL = 0x03; for(i=1;i<=40;i++); // Switch back to PLL1 PWR_CLK_SWITCH=0x55; for(i=1;i<=10;i++); NOTE: Due to the PLL limitation, the output frequency has to be the multiple of 6 MHz (half of the 12 MHz Crystal input). Or, in another words, the pre-divider (MS<5:0>) has to be set to 1 or 2. //150Mhz
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The Atlas contains power management logic that controls the transition between all these different modes of operations. This part of logic can only be controlled by the RISC but not DSP Core.
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Idle mode allows software to put each block into idle, even the RISC itself. When RISC is in idle, it continues to monitor interrupt service requests on or off-chip. When an interrupt occurs, the RISC is reactivated. The RISC enters the idle mode by executing a three-instruction sequence consisting of the CP15 instruction disable clock switching, a load from non-cacheable memory location (C=B=0), and the CP15 instruction wait for interrupt. Following are the code example of force RISC into idle mode: ldr mcr ldr mcr nop nop mcr r1, =0xA8000000 p15, 0, r0, c15, c2, 2 r0, [r1] p15, 0, r0, c15, c8, 2 p15, 0, r0, c15, c1, 2 ; just an arbitrary uncachable location ; disable clock switching ; go idle ; (re)enable clock switching
The RISC can also put other blocks into idle, including the DSP Core1, by programming a corresponding register bit in PWR_CLK_EN to disable or enable the clock of that block. Here is an example: // enable all block's clock PWR_CLK_EN = 0x1FFFF;
Enable 12MHz Oscillator power down in sleep mode (PWR_CONFIG) only when if needed
The DSP Core has its own 'idle' mode too. By issuing IDLE instruction, the DSP Core will wait indefinitely in a low power state until an interrupt to DSP occurs. That 'idle' is in different level with this idle mode. Please refer to the DSP section for more details.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Set wakeup event (PWR_WAKEUP_EN) o It can be waked up by GPIO, or, o It can be waked up by Real-time Clock Alarm Set wakeup wait time for power ramp and Oscillator stable (PWR_WAIT_TIME) Set force sleep bit (PWR_CTRL)
Here is an example of the software sleep: #define #define #define #define RTC_DIVISION ALARM_VALUE WAIT_OOK_TIME WAIT_OPU_TIME 1000 1000 0xff 0xff
// Enable 12MHz crystal power down in sleep mode PWR_CONFIG=0x01; // Set real-time clock division RTC_DIV = RTC_DIVISION; RTC_COUNTER = 0x0; // Set Alarm value RTC_ALARM = ALARM_VALUE; // alarm value
// Set wakeup event PWR_WAKEUP_EN = 0x80000000; // wakeup by alarm PWR_WAIT_TIME = (WAIT_OOK_TIME | (WAIT_OPU_TIME << 16)); // Enter sleep mode PWR_CTRL=0x01; While the hardware sleep is for another usage: when the system battery or power source is fail to provide enough current to Atlas, the Atlas will go to sleep mode automatically to save the power consumption. This is done by the BATT_FAULT or VDD_FAULT pin. The power-down sequence is almost the same as the software sleep, except user does not need to set the force sleep bit in PWR_CTRL register. When Atlas is waked up from the sleep mode, user can read the PWR_SLEEP_STATUS register to find out if its a wakeup from software sleep or hardware sleep.
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7 GPIO
7.1 Operation Overview
The Generous Purpose Input Output (GPIO) logic of the Atlas processor controls 28 pins through the use of 16 registers which control the pin direction (input or output) pin function, pin state (outputs only), pin level detection (inputs only). Some of the GPIOs can be used to bring the Atlas processor out of Sleep mode. In all the following configurations, PWR_PIN_RELEASE must be set to 1 so that Resource Sharing Controller does not control GPIO pins anymore.
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By default DMA Channel 6&7 are occupied by CODEC, and Channel 9&10 are occupied by USP0. When other USP needs to use DMA, it needs to change the RSC_DMA_MUX register as following: RSC_DMA_MUX = 0x3C // USP3 occupy DMA channel 6&7 The reason why USP3 may needs at most 4 DMA channels is: the USP3 has a special SIB bus mode, which the other USPs do not have. In this mode, there are both Audio data and Telecommunication data need to be transferred in the same frame. And both data transfers are bi-directional. NOTE: Please make sure the related DMA channels are in idle state when programming this register.
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Second Function CMOS/CCD Sensor LCD controller Serial Port 0 TIC Audio CODEC Bluetooth SPI JTAG Host port
PCMCIA interface Extension port PCMCIA interface NOR Flash/ROM interface SD interface SmartMedia/NAND Flash interface
The following figure shows how the Atlas pins are multpiexed: 1st Function
Figure 8.
1
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Basically each bit in RSC_PIN_MUX register controls the multiplex of two groups of pins. But there are some special cases: 1. Some pins are used for TIC/BIST1, JTAG, or Scan chain test besides of the functions listed above. Among those functions, the TIC/BIST, JTAG, or Scan chain has the highest priority. When Atlas is configured to those special test modes, those pins cannot be used by the normal functions any more. 2. Host Port and Extension port are all shared pin with PCMCIA interface. So bit<3> and <4> should be set to 1b1 at the same time. But if user writes 1b1 to both two bits, the bit<4> (HOST_EN) has higher priority than bit<3> (EXT_EN). In another words, if bit<4> is set to 1b1, then Host Port will occupy those pins no matter bit<3> is 1b1 or 1b0. Besides, the RSC_PIN_MUX and PWR_PIN_RELEASE register have to work together with the PWR_CLK_EN register to decide the pin multiplex. If user wants the pins to be enabled for a dedicated block, then he needs to enable the clock of that block too. Otherwise, the pins are still controlled by Resource Sharing Controller. For example, to enable the pins for Camera port: // set PIN_RELEASE PWR_PIN_RELEASE = 1; // enable Camera clock PWR_CLK_EN |= 0x80; // enable Camera port RSC_PIN_MUX |= 0x400; NOTE: On the other side, if the block is not using pins, then please turn off its clock. Otherwise, it will still consuming power and unkown result may occur.
TIC is the abbreviation of Test Interface Controller, which is for testing ARM922T.
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9 DMA Controller
9.1 Operation Overview
The DMA controller consists of 12 independent DMA channels. Each channel can be programmed to execute certain DMA operations independently. The DMA transfer can be in single mode or burst mode. In single mode, each data transfer is only 1DWORD. But in burst mode, each data transfer will be 4-DWORD long. According to the DMA addressing modes, the DMA operations can be divided into 1-D and 2-D operations. The 2-D operation mode is more suitable for image processing (like Camera) applications. Normally DMA has a start address and length. When the specified number of data is transferred, the DMA will stop. But there are some applications need to transfer data to a specified memory area repeatedly without stop (like Audio). So Atlas DMA Controller has a special loop mode for this type of applications.
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9.2 Initialization
In order to setup a DMA, the programmer needs to know a few things: 1) 2) 3) 4) 5) Is this a read from memory or write to memory? Where to get the data? Where to put the data? How to get the data (i.e. consecutively, or with jumps in between)? What is the priority of this transfer?
These parameters are defined by a series of registers that the programmer must set in order to setup a DMA properly. Each of the channels listed above has its own registers, which means that DMAs for different channels can co-exist at the same time. Each set of the registers defines the following values (Note: registers for DMA channel 0 is used as an example here. All the channels have the same register definitions): Starting Address This is a 25-bit address that defines the starting address of the DMA transfer in System Memory (i.e. either SDRAM or SRAM). If SRAM is used, then the top bits are ignored. The starting address is defined in register: DMA_CH0_ADDR (Note: DMA_CH0_ADDR1 will trigger the start of a DMA and must be set AFTER all the other registers). The Starting Address is a DWORD address. X value This is a 16-bit value which defines how many consecutive DWORDs to access per line of DMA. This value is in the register DMA_CH0_XLEN. Y value This a 16-bit value which defines how many lines of DMA to perform. The actual line number of DMA is Y+1. For example, to DMA one line, Y = 0; to DMA 10 lines, Y = 9. This value is in register DMA_CH0_YLEN. DMA width This is a 10-bit value which specifies the spacing between two lines (in DWORD). For example, if the width = 100, X = 10, and Y = 5, then each time when the DMA gets 10th DWORD, it will jump 90 DWORDs to reach the start of the next line. Since width registers are often fixed for a particular application, the Palm-2 provides a set of 4 width values (DMA_WIDTH0, DMA_WIDTH1, etc.) that can be pre-initialized. A particular DMA only needs to specify which of the 4 registers to use in the DMA_CH0_CTRL register.
Both RISC and DSP can start the DMA. Before user starts the DMA, it needs to configure the DMA_CH_DSP_CTRL register to determine either RISC or DSP will have the control of each DMA channel. Some most commonly used parameters must be set up in the initialization routine1. The common parameters include: Width registers (DMA_WIDTH0, DMA_WIDTH1, etc) Interrupt enable register (DMA_INT_EN) Direction, mode, width selection, etc. (DMA_CHx_CTRL) Loop enable if needed (DMA_CH_LOOP_CTRL) Horizontal length (DMA_CHx_XLEN)
The Vertical length (DMA_CHx_YLEN) needs to be set up every time user wants to start a new DMA. If user wants to start a 1-D DMA, then this register does not need to be set up. Besides of the above register set up, user also needs to set up some peripheral FIFO parameters such as:
1
Some of these registers have defaults values that can already be used.
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DMA or I/O mode selection Bit width selection (byte/word/dword) FIFO request level FIFO interrupt threshold
As for the detail about the FIFO initialization, please refer to the section describes peripheral FIFO. To start the DMA, user just needs to write to the DMA_CHx_ADDR register1. Here is a simple example for 1-D DMA from SDRAM to Flash Memory (DMA channel 4) initialization: #define #define #define #define #define #define BURST DIR WIDTH XLEN YLEN SDRAM_ADDR 1 1 0 0x10 0 0x100000
// set dma width registers DMA_WIDTH0 = 0x1; DMA_WIDTH1 = 0x4; DMA_WIDTH2 = 0x8; DMA_WIDTH3 = 0xc; //set dma int enable DMA_INT_EN = DMA_CH4_INT; //clear all dma interrupts DMA_CH_INT = 0xffff; //configure and start dma DMA_CH4_CTRL = ((BURST<<3) | (DIR<<2) | WIDTH); DMA_CH4_XLEN = XLEN; DMA_CH4_YLEN = YLEN; DMA_CH4_ADDR = SDRAM_ADDR;
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if((DMA_CH4_CTRL & 0x04) == DMA_MASK_TO_SDRAM) { bDMAWriteDone = 1; } if((DMA_CH4_CTRL & 0x04) == DMA_MASK_FROM_SDRAM) { bDMAReadDone = 1; } } } The interrupt handling for loop mode DMA is a little bit different. Please refer to section 9.6 for the details. }
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Start Address
Y length
If the user specifies the Y length as 0 or X length equals to the DMA Width, then this 2-D DMA will actually has the same effect as 1-D DMA. If user set up the X length greater than DMA Width, then the extra data will be wrapped around to the next data line. It will corrupt the DMA transfer for multiple-line 2-D DMA. But if its 1-D DMA, then there is no problem. The following diagram shows the wrap around of the extra data in case of X length greater than DMA Width.
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Figure 10.
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BUFA Y-LENGTH
BUFB
Figure 11.
Loop-mode DMA
As shown in the above figure, the DMA address will keep increasing, until reaching the end of a loop area whose size is defined by (DMA_WIDTH * Y_LENGTH). Then the DMA address will go back to the beginning of this area. If Y_LENGTH or DMA_WIDTH is equal to 0, then the DMA address will not change at all. And the DMA will keep transferring the data to the same DMA address until user force to stop it. In loop mode, the DMA data region is always divided into two halves: BUFA and BUFB. The DMA controller will generate interrupt twice during each loop: one time is when the DMA address reaches the end of BUFA; the other time is when the DMA address reaches the end of the BUFB. And of course the interrupt can only be generated when the corresponding interrupt enable (DMA_INT_ENABLE) bit is set. Each half (BUFA & BUFB) has its own buffer valid register bit, which can be programmed by user. The loop DMA will not be really started until the current buffer valid register bit is asserted. For example, if when the DMA goes to the end of BUFA and the valid bit of BUFB is not set, then the DMA will stop at the end of BUFA until the valid bit of BUFB is set. Here is a simple example showing the loop DMA from SDRAM to Flash Memory: //configure and start dma Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 73 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE DMA_CH4_CTRL = ((BURST<<3) | (DIR<<2) | WIDTH); DMA_CH4_XLEN = 0; DMA_CH4_YLEN = 0; DMA_CH4_ADDR = SDRAM_ADDR; DMA_CH_LOOP_CTRL = 0x100010; And the interrupt handling of the loop mode DMA is a little different with normal DMA. The following example shows how to handle the loop mode DMA interrupt: #define DMA_CH4_INT #define DMA_MASK_TO_SDRAM #define DMA_MASK_FROM_SDRAM volatile int bDMAReadDone; volatile int bDMAWriteDone; void __irq Irq_Handler() { int iStatus; iStatus = INT_PENDING; if(iStatus & INT_MASK_DMA_CTRL) { if(DMA_CH_INT & DMA_CH4_INT) { DMA_CH_INT = DMA_CH4_INT ; // clear the DMA interrupt if((DMA_CH4_CTRL & 0x04) == DMA_MASK_TO_SDRAM) { bDMAWriteDone = 1; if (DMA_CH_LOOP_CTRL & 0x10) { // if in loop mode, swap the buffer valid DMA_CH_LOOP_CTRL &= 0xfff0eff; DMA_CH_LOOP_CTRL |= 0x100000; } else if (DMA_CH_LOOP_CTRL & 0x100000) { DMA_CH_LOOP_CTRL &= 0xfef0fff; DMA_CH_LOOP_CTRL |= 0x10; } } if((DMA_CH4_CTRL & 0x04) == DMA_MASK_FROM_SDRAM) { sim_step(19); bDMAReadDone = 1; if (DMA_CH_LOOP_CTRL & 0x10) { // if in loop mode, swap the buffer valid DMA_CH_LOOP_CTRL &= 0xfff0fef; DMA_CH_LOOP_CTRL |= 0x100000; } else if (DMA_CH_LOOP_CTRL & 0x100000) { DMA_CH_LOOP_CTRL &= 0xfef0fff; DMA_CH_LOOP_CTRL |= 0x10; } } } Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 74 0x10 0x00 0x04
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE } } To finish a loop DMA, user needs to write the DMA_CH_VALID register. For example, if user wants to stop the DMA channel 4 which is a loop-mode DMA: // stop loop mode DMA DMA_CH_VALID = 0x10;
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10 PCMCIA Interface
10.1 Operation Overview
AtlasTM PCMCIA interface is compliant with PC Card Standard 2.1, PCMCIA 2.1 and JEIDA 4.1. The application typically access PC card through the socket/card services software interface. The PCMCIA interface operates in 32-bit mode, even when supporting 8-bit or 16-bit PC card, PCMCIA has the logic to route 32-bit operation to narrow bus operation. On PC card side, PCMCIA interface support Socket or Card interrupt (activated by PC card) and Management interrupt ( invoked by PC card status change). PCMCIA I/F also provide timing control register to accormodate interface to slower PC card or other I/O interface. The PCMCIA interface operation includes: Pin_mux programming M6730 Register programming Power logic register programming Memory window configuration I/O window configuration Timing control Management interrupt operation Card interrupt operation Card initialization sequence
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value_short = register_index | (((unsigned short)register_data)<<8); *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned short)value_short; 2. For register read operation, a) write index to base address 0x2000_0000 in byte mode first; b) Read base address 0x2000_0000 in word mode; c) Extract the high byte of read data. *((volatile unsigned char *) PCMCIA_IO_PHYSICAL_BASE ) = (unsigned char)register_index; value_short = *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE); register_data = (value_short & 0xFF00) >>8; 3. For extended register write operation a) Write extended index to extended index register (0x2E) b) Write register value to extended data register (0x2F) value_short = 0x2E | (((unsigned short)extended_index)<<8); *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned short)value_short; value_short = 0x2F | (((unsigned short)extended_data)<<8); *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned short)value_short; 4. For extended register read operation a) Write extended index to extended index register (0x2E) b) Read extended data register(0x2F). value_short =
0x2E | (((unsigned short)extended_index)<<8);
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned short)value_short; *((volatile unsigned char *) PCMCIA_IO_PHYSICAL_BASE ) = (unsigned char) 0x2F; value_short = *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE); register_data = (value_short & 0xFF00) >>8;
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The memory window programming can be in the following steps: 1. Program the memory window Start Address Register, End Address Register, Upper Address Register and Offset Address Register to decide the range of memory window. 2. Select the memory window bus size; 3. Set the memory window attribute; 4. Select the timing control register; 5. Configure the Mapping Enable Register (index 0x06) to enable the corresponding memory window.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE There are two interrupt modes in M6730: PCI interrupt signaling and External interrupt signaling mode. But AtlasTM only supports external interrupt signaling mode, and the irq10 is assigned to M6730 management interrupt. During initializing PCMCIA I/F, the card detect interrupt needs to be initialized. The initialization sequence is: 1. Set bit 6 of MISC CONTRL 2 register (index is 0x1E) to enable debounce for card detect. 2. Set external interrupt mode in MISC CONTROL3 (extended register, extended index is 0x25); 3. Set bit 3 of Management Interrupt Configuration register (index 0x05) to enable card detect interrupt. 4. Program management IRQ in Management Interrupt Configuration register, by default management IRQ is set to be 4hA. 5. Clear bit4 of Interrupt And General Control Register (index 0x03) to enable M6730 mamgement interrupt. 6. Set bit 6 of PCMCIA Interrupt Mask Register (PCMCIA I/F register, 0x0018) to enable PCMCIA Management interrupt 7. Set bit11 of INTR_RISC_MASK register (See Interrupt Controller section for details) to enable PCMCIA interrupt. For memory type PCMCIA card, management interrupts include card detect interrupt, battery warning interrupt, battery dead interrupt and ready status change interrupt. For I/O type PCMCIA card, management interrupts includes card detect interrupt and card status change interrupt. For each management interrupt, there is corresponding interrupt enable bit in Management Interrupt Configuration, the step 3 is different for different management interrupt, all the other steps should be same. After the PCMCIA interrupt is triggered, the handling of management interrupt must be the following steps: 1. 2. 3. 4. 5. Disable PCMCIA interrupt in INTR_RISC_MASK register; Check Bit 7 of PCMCIA_STATUS register to see whether its M6730 management interrupt who triggers the PCMCIA interrupt; If Bit 7 is 1b1, there is pending M6730 management interrupt; write 1b1 to Bit 7 of PCMCIA_STATUS to clear PCMCIA interrupt, then go to step 4. If Bit 7 is 1b0, there is other pending interrupt. Read M6730 Card Status Change register (index 0x04) to judge the source of management interrupt. The register is cleared to be 0x0 after reading. If bit 3 of Card Status Change register is 1b1, it indicates that card status changes. The Card Status Change register indicates the source of a management interrupt generated by the M6730. For the management interrupts to be generated, the corresponding enables should be set in the Management Interrupt Configuration register. So is the other management interrupt.
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10.10
For PCMCIA interface, the socket initialization sequence is: 1. Provide clock to PCMCIA interface and enable PCMCIA pin 2. Enable card detect interrupt 3. Configure one memory window to be attribute memory windows. 4. After the card insertion is detected, program the power logic registers and provide power to PC card (Section 10.4) 5. Read PC card CIS information to decide the card type, if I/O type PC card is detected, set Card_is_IO is Interrupt and General Control register. 6. Allocate resource to PC card according to CIS information; configure the I/O windows or memory windows. 7. Configre the timing registers and select the right timer for windows. 8. If I/O card is detected, enable card interrupt; if memory card is detected, enable battery warning and other management interrupt. PCMCIA can also connect to variable latency I/O device, when PCMCIA is used to access those device, they are generally accessed through PCMCIA attribute memory, the steps are: 1. Provide clock to PCMCIA interface and enable PCMCIA pin 2. Program the power logic register (according to the step in section 10.4) to active the M6730 hardware logic. 3. Program the timing register according to external I/O device timing requirement. 4. Configure one memory window to be attribute memory window, the memory space is for external I/O device. 5. Select the timer for attribute memory window.
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11 Extension port
11.1 Operation Overview
AtlasTM extension port supports both I/O mode and DMA mode. Extension port I/O mode is used by AtlasTM to access the external I/Odevice in fixed-latency or variable latency mode. But the DMA mode is realizeded through Atlas internal bus protocol, external glue logic is needed to implement the DMA data transfer. Here only the I/O mode operation is described. The pin of extension port is muxed with PCMCIA and host port. The extension port programming includes: 1. Pin_mux programming 2. Timing register programming 3. Fixed latency access 4. Variable latency access 5. DSP access
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The different bus has the different operation steps, but the basic operation steps of the USP is the same as following: Reset then power up the USP USP work mode1 initialization TX FIFO/RX FIFO configuration and initializaion Transmit/Receive USP work mode2 reinitialization(if need) Reconfiguration (if need) Transmit/Receive (if need)
In some application, USP must be configure to several kind of serial bus, so before the USP is used, it need to be reconfigured to the corresponding mode.
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12.3.1.1
Firstly, set all the USP pins that will be used to USP function and the rest pin can be set to I/O mode for other usage. The default value is USP function mode. Quick Reference Mode Register 1 SCLK_PIN_MODE, RFS_PIN_MODE, TFS_PIN_MODE, RXD_PIN_MODE, TXD_PIN_MODE, SCLK_IO_MODE, RFS_IO_MODE, TFS_IO_MODE, RXD_IO_MODE, TXD_IO_MODE
12.3.1.2
The following charaterisctic is the main consideration for the SCLK. 1. Synchronous/Asynchronous mode. (If it is asynchronous mode, no sclk is need) 2. SCLK slave/master mode. 3. SCLK IDLE toggle/stop mode (the IDLE state of SCLK when the serial bus frame is in the IDLE state) 4. SCLK IDLE high/low level mode (the SCLK stop at logic 0 or logic 1 if SCLK will stop when IDLE) 5. Count the divider number from the SYSCLK according to the frequency of SCLK 6. If the SCLK is slave, decide whether the glitch-free circuit is needed to used. All the characteristics are mapped to by the fowllowing register bits. Quick Reference Mode Register 1 SYNC_MODE, CLOCK_MODE, SCLK_IDLE_MODE, SCLK_IDLE_LEVEL Mode Register 2 USP_CLK_DIVISOR Transmit Frame Control Register SLAVE_CLK_SAMPLE
12.3.1.3
If the serial bus is not asynchronous mode, software should configure the TFS with the following charateristic. 1. TFS slave/master mode 2. TFS active high/low level 3. TFS source mode (if TFS is master mode, it is generated by hardware and software) 4. The valid TFS length 5. The whole transmitting frame length Configure the TFS signal by setting the following register bits related with the the TFS
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Quick Reference Mode Register 1 TFS_ACT_LEVEL Mode Register 2 TFS_MS_MODE, TFS_SOURCE_MODE, Transmit Frame Control Register TX_SYNC_LEN, TX_FRAME_LEN
12.3.1.4
TXD is the transmitted data line. All the following characteristics must be considered and set. 1. TX data is driven by the rising/falling edge of SCLK if serial bus is synchronous mode. 2. TX data is MSB/LSB on the data line 3. TX data length in one transmitted frame 4. TX data delay length after TFS is valid or frame starts 5. TX data shifter length when transmitting 6. the last data/zero is sent out repeatedly if the underflow happens All the characteristics above are mapped to by the fowllowing register bits. Quick Reference Mode Register 1 TXD_ACT_EDGE, ENDIAN_CTRL, TX_UFLOW_REPEAT Mode Register 2 TXD_DELAY_LEN Transmit Frame Control Register TX_DATA_LEN TX_SHIFTER_LEN
12.3.1.5
Receiving operation shares the one frame synchronous signal with the transmiting usually, but in some application, especially in the RFS slave mode, they use the different ones. So in these cases, software must still configure the RFS by the following characteristics 1. RFS slave/master mode 2. RFS active high/low level 3. the whole receving frame length Configure the RFS signal by setting the following register bits related with the the RFS. Quick Reference Mode Register 1 RFS_ACT_LEVEL Mode Register 2 RFS_MS_MODE Receive Frame Control Register RX_FRAME_LEN
12.3.1.6
RXD is the received data line. All the following characteristics must be considered and set. 1. RX data is driven by the rising/falling edge of SCLK if serial bus is synchronous mode. 2. RX data length in one receiving frame 3. RX data delay length after RFS/TFS is valid or frame starts 4. RX data shifter length when receiving All the characteristics above are mapped to by the fowllowing register bits. Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 97 -
Configure the RXD signal by setting the following register bits related with the the RXD. Quick Reference Mode Register 1 RXD_ACT_EDGE Mode Register 2 RXD_DELAY_LEN Receive Frame Control Register RX_DATA_LEN, TX_SHIFTER_LEN
12.3.1.7
Till now, software has configured most mode setting register bits, but some other more register still need to setting to configure the frame completely. If the current USP is set to IrDA mode, those register bits below must be set: IrDA related register bits
Quick Reference Mode Register 1 HPSIR_EN, IRDA_WIDTH_DIV, IrDA_IDLE_LEVEL Mode Register 2 IRDA_DATA_WIDTH Software needs to enable all the interrupt that it is used by setting the Interrrupted enable register Interrupted related register bits
The last two registers bits are showed below. They are very important for controlling the transmit/receive operation sequency and continuity. Software can make the transmitting and receiving happen in the same frame or different frame, simultenuously or alternatively, etc. TX/RX work mode related register bits
Quick Reference Mode Register 2 ENA_CTRL_MODE, FRAME_CTRL_MODE Till now you have finished configure all the registers related the transmitting/receiving frame. Thereafter you must configure the TX FIFO/RX FIFO related register bits to make them work rightly.
12.3.1.8
You must first set the DMA I/O MODE register of both TX FIFO and RX FIFO to decide whether the DMA or IO control the data transmitting/receiving. After that, the data length of transmitting/receiving must be set. Then you must set the FIFO_WIDTH bit in the (TX_FIFO/RX_FIFO) control register to decide exchange a byte/word/dowrd data with the FIFO. If the DMA mode is select, FIFO_WIDTH must be set to 0x2. Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 98 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE If DMA mode is used, one more register, USP TX_FIFO level check register, must be set to decide when to apply the DMA request for the TX_FIFO/RX_FIFO. Quick Reference TX FIFO related registers: USP TX_FIFO DMA I/O MODE register USP TX_FIFO DMA I/O length register USP TX_FIFO control register USP TX_FIFO operation register USP TX_FIFO status register RX FIFO related registers: USP RX_FIFO DMA I/O MODE register USP RX_FIFO DMA I/O length register USP RX_FIFO control register USP RX_FIFO operation register USP RX_FIFO status register After finishing all the register setting, software must reset and start the TX_FIFO and RX_FIFO, and then set the USP_EN bit of the register USP0_MODE1 to enable USP transmit and receive hardware logic After configuration of USP, enable the USP transmit and receiving logic by setting the USP_EN bit in register of USP_MODE1. // fifo Start USP0_TXFIFO_OP = 0x1; USP0_RXFIFO_OP = 0x1; // fifo Start USP0_TXFIFO_OP = 0x2; USP0_RXFIFO_OP = 0x2; //enable all the transmit and receive logic USP0_MODE1 |= 0x20;
12.3.2
Have known the key factor of each pin signal of USP and the frame description, here the initialization of some kind of serial bus is introduced below. The function of following sample code is initialization of the USP to the corresponding work mode. Each section is for a kind of serial bus. All the sample code below is initialized to IO mode for both TX_FIFO and RX_FIFO.
12.3.2.1
The following code is for 1 start bit 8 data bit, 1 stop bit, and without parity bit. Because there is some state transfer on the TXD, in order to avoid the influence of it to the other device, TXD should first be set to I/O output mode and output logic 1 to it. After finishing all the initialization, set the TXD to USP function again. #define #define #define #define #define USP_LITTLE_ENDIAN USP_TXD_AS_GPIO USP_TX_IO_MODE USP_RX_IO_MODE USP_ENABLE 0x10 0x10000 0x1 0x1 0x20
// count the clock divider usp_baud_rate = (IO_CLOCK/8/baudrate + 1)/2-1; Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 99 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE // Set to RS232 asynchronous mode USP0_MODE1 = USP_LITTLE_ENDIAN | USP_TXD_AS_GPIO; USP0_PIN_IO_DATA=0x8; // output logic 1 to TXD USP0_MODE2 = 1 | (1 << 8) | (usp_baud_rate << 21); // TX and RX frame setting USP0_TX_FRAME_CTRL = 0x7 | (0x8 << 8) | (0x9 << 16) | (0x7<< 24); USP0_RX_FRAME_CTRL = 0x7 | (0x9 << 8) | (0x7 << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = (0x04 << 2); USP0_RXFIFO_CTRL = (0x0C << 2); // Enable TX and RX logic USP0_MODE1 |= USP_ENABLE; logic //enable all the transmit and receive
for(i=0; i<1000; i++); // some time delay is needed before start to work USP0_PIN_IO_DATA=0; USP0_MODE1 &= ~USP_TXD_AS_GPIO;
12.3.2.2
The following code is for 1 start bit 8 data bit, 1 stop bit, and without parity bit. The valid data pulse on the RXD is logic 0, and the data width is 1.6s on both TXD and RXD. #define #define #define #define #define USP_LITTLE_ENDIAN USP_HPSIR_EN USP_TX_IO_MODE USP_RX_IO_MODE USP_ENABLE 0x10 0x8 0x1 0x1 0x20
// count the clock divider usp_baud_rate = (IO_CLOCK/8/baudrate + 1)/2-1; irda_width_div = 16*IO_CLOCK/10000000+1; // Set to IrDA asynchronous mode USP0_MODE1 = USP_LITTLE_ENDIAN | HPSIR_EN | (1<<30) | (irda_width_div <<22); USP0_MODE2 = 1 | (1 << 8) | (usp_baud_rate << 21) | (1<<31); // TX and RX frame setting USP0_TX_FRAME_CTRL = 0x7 | (0x8 << 8) | (0x9 << 16) | (0x7<< 24); USP0_RX_FRAME_CTRL = 0x7 | (0x9 << 8) | (0x7 << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = (0x04 << 2); USP0_RXFIFO_CTRL = (0x0C << 2);
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE // Enable TX and RX logic USP0_MODE1 |= USP_ENABLE; logic for(i=0; i<1000; i++); to work // some time delay is needed before start
12.3.2.3
#define #define #define #define #define #define #define #define
//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_LITTLE_ENDIAN | USP_RX_DATA_EDGE_NEG | USP_TX_DATA_EDGE_NEG; USP0_MODE2 = 9 | (1 << 8) | (39 << 21) | USP_ENA_AUTO_CLEAR; // 1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0x11 << 8) | (0x13 << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0x7 | (0x13 << 8) | (0x7 << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = USP_TXFIFO_WIDTH_WORD | (0x04 << 2); USP0_RXFIFO_CTRL = (0x0c << 2); // Enable TX and RX USP0_MODE1 |= USP_ENABLE;
12.3.2.4
USP use the SDOFS as the Frame synchronous signal of both transmitting and receiving frame and SDOFS is feed back to SDIFS also. #define #define #define #define #define #define USP_SYNC_MODE USP_CLK_SLAVE_MODE USP_RX_SYNC_VALID_HIGH USP_TX_SYNC_VALID_HIGH USP_SCLK_IDLE_TOGGLE USP_UFLOW_RPT_ZERO 0x1 0x2 0x100 0x200 0x400 0x80000000 0x80000 0x100000 0x1 0x1 0x20
#define USP_RFS_SLAVE #define USP_TFS_SLAVE #define USP_TX_IO_MODE #define USP_RX_IO_MODE #define USP_ENABLE
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//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_CLK_SLAVE_MODE | USP_TX_SYNC_VALID_HIGH | USP_RX_SYNC_VALID_HIGH | USP_SCLK_IDLE_TOGGLE | USP_UFLOW_RPT_ZERO; USP0_MODE2 = 1 | USP_RFS_SLAVE|USP_TFS_SLAVE; // for slave tfs, delay_length-1 USP0_TX_FRAME_CTRL = 0xf | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); // Enable TX and RX USP0_MODE1 |= USP_ENABLE;
12.3.2.5
#define USP_SYNC_MODE #define USP_TX_SYNC_VALID_HIGH #define USP_SCLK_IDLE_TOGGLE #define USP_ENA_AUTO_CLEAR #define USP_TX_IO_MODE #define USP_RX_IO_MODE #define USP_ENABLE
//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_TX_SYNC_VALID_HIGH | USP_SCLK_IDLE_TOGGLE; USP0_MODE2 = 1 | (1<<8) | USP_ENA_AUTO_CLEAR | (39 << 21); ioclk USP0_TX_FRAME_CTRL = 0xf | (0x13 << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0x13 << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); // Enable TX and RX USP0_MODE1 |= USP_ENABLE;
// 1/80 of
12.3.2.6
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE #define #define #define #define #define USP_SYNC_MODE USP_RX_SYNC_VALID_HIGH USP_TX_SYNC_VALID_HIGH USP_SCLK_IDLE_TOGGLE USP_UFLOW_RPT_ZERO 0x1 0x100 0x200 0x400 0x80000000 0x80000 0x100000 0x1 0x1 0x20
#define USP_RFS_SLAVE #define USP_TFS_SLAVE #define USP_TX_IO_MODE #define USP_RX_IO_MODE #define USP_ENABLE
//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_TX_SYNC_VALID_HIGH | USP_RX_SYNC_VALID_HIGH | USP_SCLK_IDLE_TOGGLE | USP_UFLOW_RPT_ZERO; USP0_MODE2 = 1 | USP_RFS_SLAVE | USP_TFS_SLAVE | (39 << 21); 1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); // Enable TX and RX USP0_MODE1 |= USP_ENABLE;
//
12.3.2.7
#define USP_SYNC_MODE #define USP_TX_SYNC_VALID_HIGH #define USP_SCLK_IDLE_TOGGLE #define USP_RFS_SLAVE #define USP_TX_IO_MODE #define USP_RX_IO_MODE #define USP_ENABLE
//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_TX_SYNC_VALID_HIGH | USP_SCLK_IDLE_TOGGLE; USP0_MODE2 = USP_TFS_SLAVE | (39 << 21); // 1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 103 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); // Enable TX and RX USP0_MODE1 |= USP_ENABLE;
12.3.2.8
#define #define #define #define #define #define
//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_LITTLE_ENDIAN | USP_RX_DATA_EDGE_NEG | USP_TX_DATA_EDGE_NEG | USP_SCLK_IDLE_TOGGLE | USP_TX_SYNC_VALID_HIGH; USP0_MODE2 = USP_SOFT_TFS | (39 << 21); // 1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); // Enable TX and RX USP0_MODE1 |= USP_ENABLE;
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12.4.1
Before software begins to transmit, USP0_INT_MASK must be set in the INT_RISC_MASK to enable the USP0 interrupt in the interrupt controller. Then all the interrupt to be used must be enabled There are three interrupts for use, TX_DONE, TX_FIFO_EMPTY, TXFIFO_THD_REACH. Software can select one of them to use according to the application. If one data is transmitted at one time, TX_DONE interrupt is enough, if several data are needed to transmit at one time; the last two interrupts are more suitable for high efficiency. The following operation step after the USP initialization use the TX_DONE interrupt as the example, other two interrupt have the similar step. 1. 2. 3. 4. 5. 6. 7. 8. Enable the USP0 interrupt by set the INT_RISC_MASK with INT_MASK_SERIAL_0 (0x00100000) Enable TX_DONE interrupt of the USP Enable the TX_ENA bit in the TX_RX_ENABLE register RISC/DSP writes a data to be transmitted to TX_FIFO and USP will transmit the data out to TXD automatically Having finished transmitting, USP hardware will trigger TX_DONE interrupt automatically, then software will come into the ISR (Interrupt Service Routing) of TX_DONE interrupt In ths ISR, software should first clear the INT_RISC_MASK, and clear TX_DONE interrupt in the register of USP0_INT_STATUS, and then inform the end of transmitting to other routing. Before return back from the ISR, enable the INT_RISC_MASK with INT_MASK_SERIAL_0 again. If you want to continue to transmit more data, you can return to step 2 if TX_ENA is cleared automatically after transmitting the previous data, otherwise return to step 3, and then begin the new transmitting routing.
12.4.2
This work mode is similar to the first transmitting work mode. Software can poll the TX_FIFO status register. If TX_FIFO is not full, software can write new data to be transmitted to the TX_FIFO. Software can write more than one data to the TX_FIFO if it is not full. The following operation steps use the FULL flag as the sample step after the USP initialization. 1. 2. 3. 4. Enable the TX_ENA bit in the TX_RX_ENABLE register RISC/DSP read the USP0_TXFIFO_STATUS register periodely If TX_FIFO is not FULL, RISC/DSP can write one data to be transmitted to TX_FIFO, and USP will transmit the data out to TXD automatically If you want to continue to transmit more data, you can return to step 1 if TX_ENA is cleared automatically after transmitting the previous data, otherwise return to step 2, and then begin the new transmitting routing.
Software can use not only the FULL flag, but also the EMPTY, or one capacity threshold of TX_FIFO to decide whether to write new data to TX_FIFO.
12.4.3
This work mode is suitable for a large mount of data to be transmitted out
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE If DMA access the TX_FIFO, software should be careful the initialization of TX_FIFO related register in the USP initialization introduction. The sample step of DMA operation after the USP initialization is showed below Enable the USP0 interrupt by set the INT_RISC_MASK with INT_MASK_SERIAL_0 (0x00100000) 2. Enable DMA_IO_TX_DONE interrupt of the USP 3. Enable the TX_ENA bit in the TX_RX_ENABLE register, and the TX_ENA will not be cleared automatically 4. Set the DMA_WIDTH register of the DMA controller (please refer to the DMA controller) 5. Set the RSC_DMA_MUX assign DMA CH9 to USP0 TX_FIFO 6. Setup the DMA channel 9 by setting the DMA_CH9_XLEN, DMA_CH9_YLEN, DMA_CH9_CTRL 7. Reset and start the TX_FIFO 8. Assign the memory address of the data block to be transmitted to register of DMA_CH9_ADDR, which will start DMA transfer. DMA controller will write the data to TX_FIFO, and USP then transmits them out one by one after all the data have been sent out of the TXD pin, the DMA_IO_TX_DONE interrupt will be trigger by the hardware of USP. 9. In the ISR of DMA_IO_TX_DONE interrupt, software first clear the INT_RISC_MASK, and then clear DMA_IO_TX_DONE interrupt in the register of USP0_INT_STATUS, software can then inform other software routing that the current DMA transmitting finishes. 10. If software needs to start another DMA transmitting operation, it can return to step 7. 1.
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12.5.1
Before software begins to receive, USP0_INT_MASK must be set in the INT_RISC_MASK to enable the USP0 interrupt in the interrupt controller. Then all the interrupt to be used must be enabled There are three interrupts for use, RX_DONE, RX_FIFO_FULL, RXFIFO_THD_REACH. Software can select one of them to use according to the application. If RISC/DSP wants to read one data being received at one time, RX_DONE interrupt is enough, and the RX_FIFO acts as as receive register in this case. If software wants to read several data at one time, the last two interrupts are more suitable, but software must guarantee no overlow will happen to RX_FIFO. The following operation step after the USP initialization use the RX_DONE interrupt as the example, other two have the similar step. 1. 2. 3. 4. 5. 6. 7. Enable the USP0 interrupt by set the INT_RISC_MASK with INT_MASK_SERIAL_0 (0x00100000) Enable RX_DONE interrupt of the USP Enable the RX_ENA bit in the TX_RX_ENABLE register, and the RX_ENA will not be cleared automatically Rx_shifter always monitor and receive the data on the RXD. If a new valid frame is detected. After all the data bit in a valid received frame have been received, the received data is sent to RX_FIFO from the rx_shifter automatically, which will trigger the RX_DONE interrupt In the ISR of the RX_DONE interrupt, software first clear the INT_RISC_MASK, clear RX_DONE interrupt in the register of USP0_INT_STATUS, and then can read the data out from the RX_FIFO and inform the end of reading to other routing. Before return back from the ISR, enable the INT_RISC_MASK with INT_MASK_SERIAL_0 again. If you want to continue to read more data, you can return to step 3 if RX_ENA is cleared automatically after receiving the previous data, otherwise return to step 4 to wait for another receive operation
12.5.2
This work mode is similar to the first receiving work mode. Software can poll the RX_FIFO status register. If RX_FIFO is not empty, software can read new data out from the RX_FIFO. Software can also read more than one data to the TX_FIFO has morel. The following operation steps use the EMPTY flag as the sample step after the USP initialization. 1. 2. Enable the RX_ENA bit in the TX_RX_ENABLE register RISC/DSP read the USP0_RXFIFO_STATUS register periodely. Rx_shifter always monitor and receive the data on the RXD If a new valid frame is detected, after all the data bit in a valid received frame have been received, the received data is sent to RX_FIFO from the rx_shifter automatically If RX_FIFO is not empty, RISC/DSP can read one data out from RX_FIFO If you want to continue to receive more data, you can return to step 1 if RX_ENA is cleared automatically after read the previous data, otherwise return to step 2, and then begin the new receiving routing.
3. 4.
Software can use not only the EMPTY flag, but also the FULL, or one capacity threshold of RX_FIFO to decide whether to read new data from RX_FIFO.
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12.5.3
This work mode is suitable for a large mount of data to be received out. If DMA access the RX_FIFO, software should be careful the initialization of RX_FIFO related register in the USP initialization introduction. Dont forget set the flush bit in the RX_FIFO DMA I/O MODE register. The sample step of DMA receiving operation after the USP initialization is showed below Enable the USP0 interrupt by set the INT_RISC_MASK with INT_MASK_SERIAL_0 (0x00100000) 2. Enable DMA_IO_RX_DONE interrupt of the USP 3. Enable the RX_ENA bit in the TX_RX_ENABLE register 4. Set the DMA_WIDTH register of the DMA controller (please refer to the DMA controller) 5. Set the RSC_DMA_MUX assign DMA CH10 to USP0 RX_FIFO 6. Setup the DMA channel 10 by setting the DMA_CH10_XLEN, DMA_CH10_YLEN, and DMA_CH10_CTRL (Please refer to the DMA controller). 7. Reset and start the RX_FIFO 8. Assign the memory address of the memory block to store the data from the RX_FIFO to register of DMA_CH10_ADDR to start DMA transfer. DMA controller will read the data from RX_FIFO if there is some DMA request from the RX_FIFO. Of course rx_shifter always monitor and receive the data on the RXD If a new valid frame is detected, after all the data bit in a valid received frame have been received, the received data is sent to RX_FIFO from the rx_shifter automatically 9. After all the data defined by the RX_FIFO DMA I/O length register have been received in the memory, the DMA_IO_RX_DONE interrupt will be trigger by the hardware of USP. 10. In the ISR of DMA_IO_RX_DONE interrupt, software first clear the INT_RISC_MASK, and then clear DMA_IO_RX_DONE interrupt in the register of USP0_INT_STATUS, software can then inform other software routing the end of the current DMA receiving. 11. If software needs to start another DMA transmitting operation, it can return to step 7. 1.
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12.6.1
The relationship of independence between transmitting and receiving are the simplest. Software can divide the transmitting and receiving into two different section to control. Software can follow the transmitting and receiving operation step described before. Usually the TX_ENA and RX_ENA need set only once in this kind of bus, so the TX_RX_ENABLE register should not be cleared after one data is transmitted or received. BSPORT of AD6521, UART, and IrDA are this kind of bus.
12.6.2
There are two sub-types for this kind of serial bus. One is that transmiting and receiving always happen together; the other is that they sometimes happen together, sometimes only transmiting or receiving happens. PCM bus, ASPORT and VSPORT of AD 6521, the SPORT of AD73322 are in the first type, while SPI bus of PH2401, and SI bus of PBA313 are in the latter. First type is also simple. Though they are happen together, but software can treat the transmitting and receiving as independent of each other. So the TX_ENA and RX_ENA can be set to either auto-cleared mode or not. If they are cleared, they must be set each time before trasnmsitting and receiving happen. As for the second, TX_ENA and RX_ENA must be set to auto-cleared mode. If transmitting/receiving will happen next time, only set TX_ENA/RX_ENA only, otherwise set both of them before operation.
12.6.3
In some application, the transmitting and receiving will happen alternately. SPI bus of T8536 belongs to it. So the TX_ENA and RX_ENA must set to auto-cleared mode. Before transmitting happens, set the TX_ENA. After the operation finishes, TX_ENA will be cleared automatically. If the next operation is receiving, set the RX_ENA before receiving starts. So the current operation will not influence the next one. The setting of the TX_ENA or RX_ENA controls the next operation is transmitting or receiving. The complex operation of writing and reading to the external device can be realized by this method.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE The following example is set the RXD pin of USP0 to output mode After the USP is reset and set the RXD to logic 1. USP_MODE1 | = 0x2000; USP_PIN_IO_DATA | = 0x1; The following example is set the RXD pin of USP0 to input mode After the USP is reset and read value of RXD pin to a integer of rfs_in . USP_MODE1 | = 0x42000; rfs_in = USP_PIN_IO_DATA & 0x1;
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//reset and power up PWR_CLK_EN | = PWRCLK_SP3_EN; signal PWR_CLK_EN | = PWRCLK_DMA_EN; RESET_SR | = RESET_SR_SP3_RST; RESET_SR &= RESET_SR_SP3_RST; PWR_PIN_RELEASE=1; USP3_INT_STATUS = 0xffff0000;
//SIB module initialize SIB_CTRL = (0x03 << 17) | USP3_SIB_MODE_SEL; clock is 1/8 of IO_CLOCK //SIB FIFO initialize SIB_TX_DMA_IO_LEN = 0; SIB_RX_DMA_IO_LEN = 0; SIB_TXFIFO_CTRL = 0x1 | (0x04 << 2); SIB_RXFIFO_CTRL = 0x1 | (0x0c << 2); SIB_TXFIFO_OP SIB_RXFIFO_OP SIB_TXFIFO_OP SIB_RXFIFO_OP = = = = 0x1; 0x1; 0x2; 0x2; //reset //reset //start //start the the the the
//USP3 FIFO initialize Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 112 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE USP3_TX_DMA_IO_LEN USP3_RX_DMA_IO_LEN USP3_TXFIFO_CTRL = USP3_RXFIFO_CTRL = USP3_TXFIFO_OP USP3_RXFIFO_OP USP3_TXFIFO_OP USP3_RXFIFO_OP = = = = = 0; = 0; 0x1 | (0x04 << 2); 0x1 | (0x0c << 2); //reset //reset //start //start the the the the
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12.10
SIB Operations
After the SIB module is initialized, Atlas can write or read the register data of the external SIB device, UCB1200/1300 etc. The interrupt of the UCB1200 can be connected to the GPIO of Atlas.
12.10.1
1. 2. 3.
Register Writing
The operation step of register writing is showed as below write the register address, register data, write flag to SIB_EXT_DATA regsiter. the SIB logic will send data out to external device automatically. After it finishes, SIB logic will set the SIB_WRITE_END bit in the reigster of SIB_STATUS to valid. Software can poll SIB_WRITE_END bit after step 1. The SIB_WRITE_END bit is read only. If it is valid, it means that the writing operation fnishes and software can start another register writing or reading. The SIB_WRITE_END will be cleared automatically after SIB_EXT_DATA is read or written.
12.10.2
1. 2. 3.
Register Reading
The operation step of register writing is showed as below write the register address, read flag to SIB_EXT_DATA regsiter. the SIB logic will send address and command out to external device and receive the data to be read in the SIB_EXT_DATA at the same time automatically. After it finishes, SIB will set the SIB_READ_END bit in the regsiter of SIB_STATUS to valid. Software should poll this bit after step1. the SIB_READ_END bit is read only. If it is valid, it means that the writing operation fnishes. Software can read the data out of the SIB_EXT_DATA. After the data is read, the SIB_READ_END will be clear automatically and software can start another register writing or reading.
12.10.3
The DMA mode is usually used for the audio data transfering. The operations step below use the SIB FIFO for data transfering. 1. 2. 3. 4. 5. 6. 7. 8. before you start audio data transfer, you must initialize the SIB module. initialize the SIB TX_FIFO and RX_FIFO to. Be careful that both two FIFOs should be set to DMA mode, and then reset and start the two FIFO to prepare for data transfer. configure all the audio related register of the external SIB device except the register bits of AUD_IN_ENA or AUD_OUT_ENA in the audio control register with the address equal to 8 Set the DMA_WIDTH register of the DMA controller (please refer to the DMA) Set the RSC_DMA_MUX assign DMA CH6&CH7 to SIB RX_FIFO and TX_FIFO Setup the DMA channel 6 and channel 7 related register in the DMA controller, such as the DMA_CH6_XLEN, DMA_CH6_YLEN, DMA_CH6_CTRL, DMA_CH6_XLEN, DMA_CH6_YLEN, DMA_CH6_CTRL Assign the memory address of the audio data to be transmitted to register of DMA_CH7_ADDR to start DMA transmitting, and assign the memory address of the memory block to store the external audio data to register of DMA_CH6_ADDR to start DMA receiving. write 1 to both the AUD_IN_ENA and AUD_OUT_ENA bit to the audio contol register with address equal to 8, which will automatically start the both the SIB module and external device
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE to tranmsit and receive audio data on the SIB bus. The received data in the RX_FIFO will be read out by the DMA and the data written into the TX_FIFO by the DMA will be sent out by SIB automatically. 9. If the TX_FIFO/RX_FIFO DMA length register is not set to 0, after the data defined in the DMA length register has been transmitted/received, the DMA write/read will stop. Software can also use the interupt to monitor it. 10. If the TX_FIFO/RX_FIFO DMA length register is set to 0, and software want to finish the audio data transfer, it can write 0 to both the AUD_IN_ENA and AUD_OUT_ENA bit of audio control register, which will stop both side of SIB bus to stop the Audio data transfer.
12.10.4
The DMA mode is also used for the Telecom data transfering. The operations step below use the USP3 FIFO for data transfering. The whole procedure is similar to that of the Audio data. before you start telecom data transfer, you must initialize the SIB module. initialize the USP3 TX_FIFO and RX_FIFO. Be careful that both two FIFOs should be set to DMA mode, and then reset and start the two FIFOs to prepare for data transfer. 3. configure all the telecom related register of the external SIB device except the register bits of TEL_IN_ENA or TEL_OUT_ENA in the telecom contol register with the address equal to 6 4. Set the DMA_WIDTH register of the DMA controller (please refer to the DMA) 5. Set the RSC_DMA_MUX assign DMA CH9&CH10 to USP3 RX_FIFO and TX_FIFO 6. Setup the DMA channel 9 and channel 10 related register in the DMA controller, such as the DMA_CH9_XLEN, DMA_CH9_YLEN, DMA_CH9_CTRL, DMA_CH10_XLEN, DMA_CH10_YLEN, DMA_CH10_CTRL 7. Assign the memory address of the telecom data to be transmitted to register of DMA_CH10_ADDR to start DMA transmitting, and assign the memory address of the memory block to store the external telecom data to register of DMA_CH9_ADDR to start DMA receiving. 8. write 1 to both the TEL_IN_ENA and TEL_OUT_ENA bit to the telecom contol register with address equal to 6, which will automatically start the both the SIB module and external device to tranmsit and receive telecom data on the SIB bus. The received data in the RX_FIFO will be read out by the DMA and the data written into the TX_FIFO by the DMA will be sent out by SIB automatically. 9. If the TX_FIFO/RX_FIFO DMA length register is not set to 0, after the data defined in the DMA length register has been transmitted/received, the DMA write/read will stop. Software can also use the interupt to monitor it. 10. If the TX_FIFO/RX_FIFO DMA length register is set to 0, and software want to finish the telecom data transfer, it can write 0 to both the TEL_IN_ENA and TEL_OUT_ENA bit of audio control register, which will stop both side of SIB bus to stop the telecom data transfer. Audio data can select either SIB FIFO or USP3 FIFO as the data buffer, and then telecom data will use another one. 1. 2.
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2. Program RSC_PIN_MUX to enable audio CODEC pin. Since audio CODEC is pin-muxed with USP1, if audio CODEC function is selected, the pin should be configured for audio CODEC purpose. RSC_PIN_MUX | = 0x8000; 3. Program the CODEC_SHARE register to select audio CODEC modes: AC97 or I2S. If AC97 CODEC controller is selected, bit 7 of CODEC_SHARE should be 1b0; if I2S interface is selected, bit 7 of CODEC_SHARE register should be 1b1.
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3) Program CODEC_AC97_COMMAND to set the register index and written data. CODEC_AC97_COMMAND = (register_value <<16) | (register_index <<8) 4) Set bit 15 to indicate the next output frame contains valid data; Set bit 14 and bit 13 of CODEC_AC97_CONTROL, the register index and write command will be issued to AC97 audio CODEC in slot 1 and slot 2 of next output frame. CODEC_AC97_CONTROL |= 0xE000;
5) Check the bit 14 and 13 (tag bit of slot 1 and slot 2) of CODEC_AC97_CONTROL to make sure that the command has been issued. The sample code for step 3 to 5 is:
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE CODEC_AC97_CMD = ((unsigned long) data << 16) | ((unsigned long) addr << 8); CODEC_AC97_CTRL |= 0xe000; while(CODEC_AC97_CTRL & 0x4000); When reading status from AC97 audio CODEC, the step is: 1) Program CODEC_SHARE register to bring AC97 controller DA and AD channel out of ilde mode (If they are already enabled, there is no need to set them again). CODEC_AC97_CONTROL & = ~0x60;
2) Set bit 5 of CODEC_AC97_CONTROL register to start AC97; If AC97 has already been started, there is no need to set the bit again. CODEC_AC97_CONTROL |= 0x20; 3) Program CODEC_AC97_COMMAND to set the register index CODEC_AC97_COMMAND register to indicate the read operation. CODEC_AC97_COMMAND = (register_index <<8) | 0x8000; 4) Set bit 15 of CODEC_AC97_CONTROL to indicate that the next output frame is valid; Set bit 14 of CODEC_AC97_CONTROL, the read command will be issued to AC97 audio CODEC in the slot1 of next output frame; CODEC_AC97_CONTROL |= 0xC000; 5) Poll AC97_REG_RD register bit, when its asserted, it indicates the AC97 audio CODEC has return the status data. Then write 1b1 to AC97_REG_RD to clear the status 6) Read CODEC_AC97_STATUS register to get the value. register_value = (CODEC_AC97_STATUS && 0xFFFF0000) >> 16; The sample code for step 3 to step 6 is: CODEC_AC97_CMD = (0x0000ffff & (((unsigned long) addr CODEC_AC97_CTRL |= 0xc000; while(CODEC_AC97REG_OK == 0x0); CODEC_AC97REG_OK = 0x01; data = (CODEC_AC97_STATUS & 0xFFFF0000) >> 16; 3. AC97 record The following steps describe the procedures necessary for audio dual channel record program. 1) Initialize audio CODEC interface and select AC97 mode (section 13.2); 2) Initialize external AC97 audio CODEC. 3) Program AC97 audio CODEC control register to set sample frequency, gain etc. 4) DMA audio record channel (DMA channel 6) initialization; a) Program DMA channel x-length, Y-length and Width register to set transfer counter. When in loop mode, the DMA x-length will be 0, and Y-length must be a non-zero value. b) Enable DMA interrupt; (Please refer to DMA interface for more information) Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 119 | 0x80) << 8)); and set bit 15 of
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 5) Initialize AtlasTM AC97 controller interface; a) Reset and initialize audio record FIFO; b) Program CODEC_SHARE register to enable AC97 record channel; The play channel may also be enabled for AC97 codec register control. c) If interleave mode is selected, set bit 0 of CODEC_SHARE register When interleave mode is selected, in dual channel mode the 32-bit data is in L-R format. In normal mode, the 32-bit data is in R-L mode. d) Program CODEC_AC97_CONTROL register to select the left and right channel;
If dual channel record mode is selected, both the left and right record channel of CODEC_AC97_CONTROL should be enabled. AC97 controller interface receives data from input frame Slot3 and Slot4 for left and right channel respectively. In normal mode, the 32-bit audio data is saved in R-L format; when interlave mode is selected the 32-bit data is in L-R mode. CODEC_AC97_CONTROL |= 0x0C; In single channel record mode, when left channel is enabled, the left record channel of CODEC_AC97_CONTROL should be enabled and right record channel is disabled. AC97 controller only receives data from input frame Slot3, the data from Slot4 is ignored. When right channel is enabled, the right record channel of CODEC_AC97_CONTROL should be enabled and left record channel is disabled. AC97 controller only receives data from input frame Slot4, the data from Slot3 is ignored. 6) Start audio record FIFO. a) Set AC97_START bit to start AC97 interface; b) Start audio record FIFO; CODEC_RX_FIFO_OP_REG = 0x01; 7) Instruct DMA audio record channel to run by programming DMA channel 6 start address register DMA_CH6_ADDR. 4. AC97 audio play
The following steps describe the procedures necessary for audio play: 1) Initialize AtlasTM audio CODEC controller 2) Initialize AC97 audio CODEC a) Reset AC97 Codec; b) Program AC97 Codec control register to set sample frequency, gain etc. 3) DMA audio play channel (DMA channel 7) initialization; a) Program DMA channel x-length, Y-length and Width register to set transfer counter. When in loop mode, the DMA x-length will be 0, and Y-length must be a non-zero value. b) DMA interrupt enable (Please refer to DMA interface for more information) 4) Configure AtlasTM AC97 interface; a) Reset and audio play FIFO; CODEC_TX_FIFO_OP_REG = 0x02; b) Program CODEC_SHARE register to AC97 play channel; When AC97 codec status needs to be monitored, the AC97 record channel must be enabled.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE c) If interleave mode is selected, set bit 0 of CODEC_SHARE register
When interleave mode is selected, in dual channel mode the 32-bit audio data is treated as L-R format. In normal mode, the 32-bit data is treated as R-L mode. d) Program CODEC_AC97_CONTROL register to enable the left or right channel.
If dual channel play mode selected, both the left and right play channel of CODEC_AC97_CONTROL should be enabled. In normal mode, the 32-bit audio data is treated as R-L format, the high 16-bit is sent to AC97 audio CODEC through output frame Slot 4 and low 16bit is through output frame Slot3; In interlave mode the high 16-bit is for left playback channel and low 16-bit is for right play channel. In single channel play mode, when the left play channel of CODEC_AC97_CONTROL is enabled, the 32-bit digital audio data to be played is in L-L format representing 2 sample data. When right channel is enabled, the 32-bit data is in R-R format. e) Program CODEC_AC97_CONTROL register to set the tag to enable the AC-Link slots.
Bit 15 (Frame valid) of CODEC_AC97_CONTROL register must be set no matter the audio play is in stereo or mono mode. It is used to indicate AC97 audio CODEC that output frame is valid. If dual channel mode is selected, the bit 11 and 12 (output frame tag bit of slot 4 and 3) of CODEC_AC97_CONTROL register should be set. If left single channel is enabled, bit 12 (output frame tag of Slot 3) must be 1b1; if bit 11 (output frame tag of Slot 4) is also set, the audio data is also played through right channel, in this case both the left and right channel play the same mono audio data stream. If bit 11 is 0, only left channel plays the audio stream. If right single channel is enabled, bit 11 (output frame tag of Slot 4) must be 1b1; if bit 12 (output frame tag of Slot 3) is also set, the audio data is also played back through left channel, in this case both the left and right channel play the same mono audio data stream. If bit 12 is 1b0, only right channel plays the audio stream. 5) Instruct DMA audio play channel to run by writing DMA channel 7 start address register. 6) Start audio playback FIFO; Set AC97_START bit to start AC97 interface CODEC_TX_FIFO_OP_REG = 0x01; CODEC_AC97_CTRL |= AC97_START;
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE c) Program CODEC_UDA_CONTROL to set I2S word_select frequency The frequency relationship between CKO, BCK and WS is: fBCK = fIOCLOCK / 2(BCK_SET + 1); fWS = fBCK/2(WS_SET+1); fCKO = 512fws or 384fws or 256fws 3) DMA audio play channel (DMA channel 7) initialization; a) Program DMA channel x-length, Y-length and Width register to set transfer counter. When in loop mode, the DMA x-length will be 0, and Y-length must be a non-zero value. b) DMA interrupt enable (Please refer to DMA interface for more information) 4) Initialize external I2S Codec through L3 interface by programming Atlas GPIO a) Reset I2S Codec; b) Program I2S Codec control register to set gain etc. 5) Initialize I2S interface; d) Reset and initialize audio play FIFO; e) Program CODEC_SHARE register to enable UDA interface and UDA play channel; f) Program CODEC_UDA_CONTROL register to enable the left and right channel. If dual channel play mode selected, both the left and right play channel of CODEC_UDA_CONTROL should be enabled. In normal mode, the 32-bit audio data is treated as R-L format, the high 16-bit is sent to I2S audio CODEC through output frame right Slot and low 16-bit is through output frame left slot; In interlave mode the high 16-bit is for left playback channel and low 16-bit is for right play channel. In single channel play mode, when the left play channel of CODEC_UDA_CONTROL is enabled, the 32-bit digital audio data to be played is in L-L format representing 2 sample data. When right channel is enabled, the 32-bit data is in R-R format. g) Program CODEC_UDA_CONTROL register to enable the UDA left and right slots. If dual channel mode is selected, the bit 30 and 31 (right and left slot enable signals) of CODEC_UDA_CONTROL register should be set. If left single channel is enabled, bit 31 (left slot enable) must be 1b1; if bit 30 (right slot enable signal) is also set, the audio data is also played through right channel, in this case both the left and right channel play the same mono audio data stream. If bit 30 is 0, only left channel plays the audio stream. If right single channel is enabled, bit 30 (right slot enable) must be 1b1; if bit 31 (left slot enable) is also set, the audio data is also played back through left channel, in this case both the left and right channel play the same mono audio data stream. If bit 31 is 1b0, only right channel plays the audio stream. 6) Instruct DMA audio play channel to run and start audio playback FIFO; Set UDA_START bit to start UDA interface.
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14 Camera Interface
14.1 Operation Overview
In sensor control interface, support following operation mode: 1. Slave mode, external sensor provide VSYNC, HSYNC and PIXCLK to the Atlas processor. 2. Master mode, Atlas processor provides VSYNC, HSYNC and PIXCLK signal to the external sensor. 3. VSYNC, HSYNC or PIXCLK can be inversed by the internal logic for generating the needed control signal. 4. 10-bit pixel data can be shifted right or left to adapt the software operation. 5. There is an internal logic to remove the glitch signal in the pixel clock. 6. Capture the needed image with active region function. 7. Support abnormal interrupt, such as FIFO overflow. In I2C module, support following operation mode: 1. In master mode, support 7-bit SLAVE ID. 2. In master mode, support programmable I2C master clock frequency. 3. In master mode, support up to 4 bytes data transfer. 4. In slave mode, support 7-bit programmable slave ID. 5. In slave mode, support 2 bytes data transfer.
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Enable the camera interface, for it share some pins with data flash/SmartMedia interface. Supply the clock to the camera interface. Reset the camera interface. Enable the camera interrupt.
14.2.1.2
Following code gives an example: // Enable camera pins. PWR_PIN_RELEASE = 1; RSC_PIN_MUX |= 0x4000; // Enable clock of camera interface PWR_CLK_EN |= 0x80; // Reset camera interface RESET_SR |= 0x1000; RESET_SR &= (~0x1000); // Enable the camera interrupt. INT_RISC_MASK |= 0x00008000;
14.2.2
14.2.2.1
1. 2. 3. 4. 5. 6.
Check the INT_IRQ_PENDING register if this interrupt is trigged by the camera interface. Disable the camera interface interrupt to avoid the interrupt generate repeatly. Check the CAM_INT_CTRL register. Set a flag to notify the main program which interrupt happens. Clear the interrupt by setting the corresponding bit of CAM_INT_CTRL register. Enable the camera interrupt again.
14.2.2.2
Following code are used in the interrupt processing program to process the camera interrupt. // Check the interrupt source Int iStatus = INT_IRQ_PENDING; if (iStatus & 0x00008000) { // Disable the camera interrupt INT_RISC_MASK &= (~0x00008000); iStatus = CAM_INT_CTRL; // Check which interrupt happens if (iStatus & 0x01) { // Clear the interrupt Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 125 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE CAM_INT_CTRL = 0x01; } // Add similar code here to check other interrupts // Enable the camera interrupt. INT_RISC_MASK |= 0x00008000; }
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Supply the clock to DMA interface. Enable the DMA interrupt. Enable the DMA channel2 interrupt in DMA_INT_EN register. This channel is dedicated to camera interface.
14.3.1.2
Following code gives an example: // Enable clock of DMA interface PWR_CLK_EN |= 0x04; // Enable the DMA interrupt INT_RISC_MASK |= 0x02000000; // Enable DMA channel2 interrupt DMA_INT_EN |= 0x04;
14.3.2
14.3.2.1
1. 2. 3. 4. 5. 6.
Check the INT_IRQ_PENDING register if this interrupt is trigged by the DMA interface. Disable the DMA interrupt to avoid the interrupt generate repeatly. Check the DMA_CH_INT register. If this interrupt is trigged by channel2, set a flag to notify the main program DMA is done. Clear the interrupt by setting the bit2 of DMA_CH_INT register. Enable the DMA interrupt again.
14.3.2.2
It is only DMA channel2 interrupt that need to be checked. Following code are used in the interrupt processing program to process the DMA channel2 interrupt. // Check the interrupt source Int iStatus = INT_IRQ_PENDING; if (iStatus & 0x02000000) { // Disable the DMA interrupt INT_RISC_MASK &= (~0x02000000); iStatus = DMA_CH_INT; // Check which interrupt happens if (iStatus & 0x04) { // Clear the interrupt. DMA_CH_INT = 0x04; // Set a flag here such as following code. bDMADone = 1; Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 127 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE } // Enable the DMA interrupt again. INT_RISC_MASK |= 0x02000000; }
14.3.3
14.3.3.1
DMA operation
Step-by-step register programming
Following registers must be set first. 1. Set the CAM_FIFO_LEVEL_CHK to adjust the priority of channel2. 2. Select a DMA width register and set it with the needed number. 3. Configure the DMA_CH2_XLEN and DMA_CH2_YLEN register. 4. Configure the control register, work in normal mode or burst mode, transmission direction and select a width register. 5. Start the DMA channel2 operation by writing the DWORD sdram address to DMA_CH2_ADDR. 6. Wait for the DMA channel2 interrupt.
14.3.3.2
Following code gives an example base on following condition: Capture the 640*480 pixel data from external sensor and store it from the address 0x20000 using DMA width0 register. // Set the DMA_WIDTH0 register. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; // Set the YLEN, it equals to actual number - 1 DMA_CH2_YLEN = 480-1; // Set the DMA operation mode DMA_CH2_CTRL |= 0x0000; //normal DMA mode DMA_CH2_CTRL |= 0x0008; //burst DMA mode // Start dma channel2 operation, this data must be the DWORD address. DMA_CH2_ADDR = 0x20000/4;
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Write 0xFFFFFFFF to CAM_START, make active region out of possible range. Write 0x00007FFF to CAM_YINT, avoid camera interface generate too many interrupts. Set bit5 of CAM_CTRL register according the trigger type of sensor. Enable the SENSOR_INT and FIFO_OVERFLOW in the CAM_INT_EN register. Reset the FIFO before capture operation.
14.4.1.2
Following code gives an example: CAM_YINT = 0x00007FFF; CAM_START = 0xFFFFFFFF; CAM_INT_EN |= 0x21;
14.4.2
14.4.2.1
Sensor clock can be provided by the CKO of Atlas-1 except the external oscillator. If using CKO, following register must be configured. 1. 2. 3. 4. 5. Set the PWR_PLL2_CONFIG to select a need frequency. Turn on the PLL2. Set the PWR_CLK_RATIO to decide the ratio between CKO and PLL2 frequency. Set the PWR_CLK_SWITCH to switch the CKO to PLL2. Set the PWR_CLK_EN to enable the CKO output.
14.4.2.2
Following code gives an example provide a 12MHz CKO. // Set the PLL2 to 48MHz PWR_PLL2_CONFIG = 0x44; // Turn on PLL2 PWR_CLK_CTRL |= 0x02; // Wait for PLL2 work normal for(i=1;i<=300;i++); // Select CKO = PLL2/4=48M/4=12M PWR_CLK_RATIO |= 0x20; // CKO switch to PLL2 PWR_CLK_SWITCH |= 0x80; for(i=1;i<=100;i++); // Enable CKO PWR_CLK_EN |= 0x10000;
14.4.3
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14.4.3.1
1. 2. 3. 4. 5. 6. 7. 8. 9.
Set the CAM_DMA_LEN to the actual transfer byte number. This register can be used in debugging process to check the actual received bytes. Reset the FIFO through setting CAM_FIFO_OP. Configure the DMA register according to actual needed. Start the DMA operation. Configure the camera register according to actual needed. Start capturing process. Wait for the DMA interrupt. After receiving DMA interrupt, it means the receive picture has stored to SDRAM. Clear the bit0 of CAM_FIFO_OP register after the DMA interrupt received. Otherwise FIFO will overflow.
14.4.3.2
Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation. // Set the CAM_DMA_LEN to 640*480*2, for each 10-bit pixel occupis 2 bytes; CAM_DMA_LEN = 648*480*2; // Reset the FIFO through setting CAM_FIFO_OP. CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation CAM_FIFO_OP |= 0x01; After receiving DMA interrupt, it means the receive picture has stored to SDRAM.
14.4.4
14.4.4.1
1. 2.
In this mode, PIXEL clock, HSYNC and VSYNC are generated by external sensor, so set bit8,9,10 of register CAM_CTRL to 0. Capture the video image as 14.4.3 list.
14.4.4.2
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation. // Set the CAM_CTRL register, select slave mode. CAM_CTRL &= (~0x0700); // Set the CAM_DMA_LEN to 640*480*2, for each pixel occupis 2 bytes; CAM_DMA_LEN = 648*480*2; // Reset the FIFO through setting CAM_FIFO_OP. CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation CAM_FIFO_OP |= 0x01; After receiving DMA interrupt, it means the receive picture has stored to SDRAM.
14.4.5
14.4.5.1
1. 2.
Set the CAM_PIXEL_SHIFT to select the shift direction and shift number. Capture the video image as 14.4.3 list.
14.4.5.2
Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA burst mode. We only need its high eight bit from its total 10-bit pixel data, so shift right 2 bits. 4 shifted pixel data will be combined to a DWORD data. // Set the CAM_PIXEL_SHIFT. CAM_PIXEL_SHIFT = 2; // Set the CAM_DMA_LEN to 640*480; CAM_DMA_LEN = 640*480; // Reset the FIFO CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA channel2 DMA_WIDTH0 = 640/4; DMA_CH2_XLEN = 640/4; DMA_CH2_YLEN = 480-1; // Set the burst DMA mode. DMA_CH2_CTRL = 0x0008; // Start the DMA operation. DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 131 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation. CAM_FIFO_OP |= 0x01; After receiving DMA interrupt, it means the receive picture has stored to SDRAM.
14.4.6
14.4.6.1
1. 2.
In this mode, PIXCLK, HSYNC and VSYNC can be inversed separately, so set bit2 or bit3 or bit4 of CAM_CTRL register according to system needs; Capture the video image as 14.4.3 list.
14.4.6.2
Following example code are based on following conditions: Capture a (640,480) picture from (2,2) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation. The PIXCLK, HSYNC and VSYNC are inversed, this function must cooperate with your sensors timing. // Set the CAM_CTRL register. CAM_CTRL |= 0x001C; // Set the CAM_DMA_LEN to 640*480*2; CAM_DMA_LEN = 640*480*2; // Reset the FIFO CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, DMA_WIDTH0 = 640/2, DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1+2) << 16) + (640-1+2); CAM_YINT = 480-1+2; CAM_START = 0x00020002; // Start the capture operation CAM_FIFO_OP |= 0x01; After receiving DMA interrupt, it means the receive picture has stored to SDRAM.
14.4.7
1. 2.
In this mode, if the pixel clock has some glitches, we can use sample function to decrease the damage, so set bit7 of CAM_CTRL register. It must be sure that IOCLK frequency is at least 6 multiple of PIXCLK. Capture the video image as 14.4.3 list.
14.4.7.1
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation. // Set the CAM_CTRL register to enable this function. CAM_CTRL |= 0x0080; // Set the CAM_DMA_LEN to 640*480*2; CAM_DMA_LEN = 640*480*2; // Reset the FIFO. CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation. CAM_FIFO_OP |= 0x01; After receiving DMA interrupt, it means the receive picture has stored to SDRAM.
14.4.8
1. 2.
In this mode, camera interface generate PIXCLK, HSYNC and VSYNC by itself, so set bit 8,9,10 of CAM_CTRL register; Capture the video image as 14.4.3 list.
14.4.8.1
Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation. Output pixel clock equals to 3MHz (suppose IOCLK equals to 30MHz), valid HSYNC width equals to 16 pixel clocks, valid VYSNC high period equals to 38 pixel clocks plus 1 HSYNC width, a valid line include 700 pixel clocks and a whole picture include 600 lines. // Set the output VYSNC signal, 0x257 blank line + 0x1 active line = 600 lines CAM_VSYNC_CTRL = 0x02570001; // Set the output HSYNC signal, 0x2ac blank pixel clocks + 0x10 active pixel clocks = 700 pixel clocks CAM_HSYNC_CTRL = 0x02AC0010; // Set the output PIXCLK signal, (4+1)*2*output pixel clock frequency = IOCLK frequency. // Set the valid VSYNC high period equals to 38 pixel clock. CAM_PIXCLK_CTRL = 0x00240004; // Set CAM_CTRL register to enable the PIXCLK, HSYNC and VSYNC output. CAM_CTRL |= 0x0700; // Set the CAM_DMA_LEN to 640*480*2; CAM_DMA_LEN = 640*480*2; // Reset the FIFO Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 133 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2 and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation CAM_FIFO_OP |= 0x01; After receiving DMA interrupt, it means the receive picture has stored to SDRAM.
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Initialize Unit
Step-by-step register programming
Set bit6 of CAM_CTRL register to enable the I2C unit. Enable I2C master interrupt in CAM_INT_EN register. Set I2C clock period in CAM_I2C_MASTER_CLK_CTRL register.
14.5.1.2
Fowllowing example configures the I2C master clock period. Suppose IOCLK frequency = 33MHz and I2C master clock frequency = 100kHz, so the high period and low period of SCLK = 33M/ (2*100K) = 165 = 0xA5. CAM_CTRL |= 0x40; CAM_INT_EN |= 0x06; CAM_I2C_MASTER_CLK_CTRL = 0x00A500A5;
14.5.2
14.5.2.1
1. 2. 3. 4. 5.
Write n bytes (up to 4 bytes) register data to CAM_I2C_MASTER_OUT register. Write slave ID, register number, and register address to CAM_I2C_MASTER_CTRL register. R/W must be 0 for a write. Wait for I2C interrupt. If I2C success interrupt happens, set bit1 of CAM_INT_CTRL register to clear this interrupt and transmission is ok. If I2C fail interrupt happens, set bit2 of CAM_INT_CTRL register to clear this interrupt. You must check your hardware connection and try it again from step1.
14.5.2.2
Following example code are based on following conditions: Write 1 byte data to a slave device Slave device ID address = 0x33 (7b0110011) Register address = 0xAA(8b10101010) Data to write = 0xAC // Set the register data CAM_I2C_MASTER_OUT = 0xAC; // Set the control register, transfer number(1byte, 2b00)+slave address(0x33)+write bit(0)+register address(0xAA) CAM_I2C_MASTER_CTRL = 0x000066AA; Wait for I2C master success interrupt or fail interrupt. If success interrupt happens, clear this interrupt and transmission is ok. Otherwise, if fail interrupt happens, you must check your hardware connection and try it again.
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14.5.3
14.5.3.1
1. 2. 3. 4. 5.
Write slave ID, register number and register address to CAM_I2C_MASTER_CTRL register. R/W must be 1 for a read. Wait for I2C master interrupt. If I2C master success interrupt happens, set bit1 of CAM_INT_CTLR register to clear this interrupt. Read register data from CAM_I2C_MASTER_IN register. If I2C master fail interrupt happens, set bit2 of CAM_INT_CTRL register to clear this interrupt. You must check your hardware connection and try it again from step1.
14.5.3.2
Following example code are based on following conditions: Read 2 byte data from an external I2C device. Slave device ID address = 0x33 Register address = 0xAA // Set the control register, transfer number(2bytes, 2b01)+slave address(0x33)+read bit(1)+register address(0xAA) CAM_I2C_MASTER_CTRL = 0x400067AA; Waiting for I2C master success interrupt or fail interrupt. If success interrupt happens, Read data from CAM_I2C_MASTER_IN. Bit0bit15 is the valid byte. Clear I2C master success interrupt bit. If fail_interrupt happens, you must check your hardware connection and try it again.
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Initialize Unit
Step-by-step register programming
During initializing process, following register must be set first: 1. Set bit6 of CAM_CTRL register to enable the I2C unit. 2. Enable I2C slave interrupt in CAM_INT_EN register. 3. Set the SLAVE ID to the CAM_I2C_SLAVE_CTRL register.
14.6.1.2
Following code gives an example. // Enable I2C module CAM_CTRL |= 0x40; // Enable interrupt CAM_INT_EN |= 0x18; // Set slave ID (7h4c) CAM_I2C_SLAVE_CTRL = 0x9800;
14.6.2
14.6.2.1
Normal Operation
Step-by-step register programming
When I2C slave module received register address send from external I2C master device, it will generate DATA_REQ_INT interrupt to RISC, RISC must read CAM_I2C_SLAVE_ADDR register first, get the register address, then send the corresponding register data to CAM_I2C_SLAVE_CTRL register. When I2C slave module complete receive or transmit a complete register data, it will generate I2C_SLAVE_INT to notify RISC. RISC should read CAM_I2C_SLAVE_CTRL again, and overwrite the old register data with new data in CAM_I2C_SALVE_CTRL if bit8 of this register equals to 0.
14.6.2.2
Following example code are based on following conditions: Process register0x0b, suppose its default value = 0x7788. Slave ID of AtlasTM-1 is 7h4C. // Set the slave ID to I2C slave unit. CAM_I2C_SLAVE_CTRL = 0x9800; When receive DATA_REQ_INT, read CAM_I2C_SLAVE_ADDR register. Suppose it value equal to 0x0000980B. It means external master will process the register0b. // Write register data to CAM_I2C_SLAVE_CTRL register. CAM_I2C_SLAVE_CTRL = 0x7788980B; After receiving I2C_SLAVE_INT, read CAM_I2C_SLAVE_CTRL register back. If bit8 of received data equals to 1, that means external device read register of AtlasTM-1 processor. Otherwise, external device write new data to AtlasTM-1 processor, suppose it value equal to 0x6677980B, overwrite register 0x0B data from 0x7788 to 0x6677.
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15.2 Initialization
The USB device register space in Atlas is from 0x80040000. Offset 0x0~0x7c are USB core registers; 0x80~0x90 are USB interface registers; after 0xf00 are DMA FIFO control registers. Please refer to Atlas Development Manual for registers definition. All bit mask used in sample should be defined in head files. The initialization sequence is: Configure PLL2 (Make sure PLL1 already be effectived) PWR_PLL2_CONFIG = 0x44; PWR_CLK_CTRL |= 0x3; // turn on PLL2 Enable USB clock. PWR_CLK_EN |= PWRCLK_USB_EN; Enable interrupt controller INT_RISC_MASK |= INT_MASK_USB; Initialize USB interface wait counter (if IO clock more than 48MHz) USB_WS = 0x68; Enable USB. USB_USBSTS = (USB_ENABLE | USB_INTF_MODE | USB_RST_DISABLE); Clear all interrupt status USB_INTSTS1 = 0xFF; USB_INTSTS3 = 0xFF; USB_INTSTS5 = 0xFF; Enable endpoint 0, reset and suspend interrupt USB_INTEN1 = USB_EP0_TX_RX_INT_MASK; USB_INTEN3 = USB_EP0_TX_RX_INT_MASK; USB_INTEN5 = USB_RST_INT_MASK | USB_SUS_INT_MASK; Enable USB endpoint 0. USB_EP0CTL = 0x1B; Enable 3.3v supply. USB_USBSTS |= USB_SOFT_CONNECT;
Please refer to charpter 6 for details of clocks and power manager operation
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EP0 write sequence: Device generates an EP0 TX Interrupt. Select endpoint. USB_EPINDX = ep_num; Flush transmition FIFO. (if need) USB_EP0CTL |= 0x10; Write the data into USB TX data register.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE USB_EPTXDAT = data; Set EP0 control register bit2. USB_EP0CTL |= 0x20; Clears the EP0 TX interrupt bit and returns from the interrupt service routine.
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Following sequence for bulk out transfer: The host sends a OUT command. Device generates an EP1~3 RX Interrupt. Select endpoint. USB_EPINDX = ep_num; Flush and clear underflow or overflow. (if need) USB_EPRXCTL |= USB_EP_FLUSH; USB_EPRXSTS |= (USB_EP_XFER_OF | USB_EP_XFER_UF); Check valid packet received. USB_EPRXSTS; Get byte count for the data packet. pkt_len = USB_EPRXCNTL; Read data from USB. data = USB_EPRXDAT; Set RX data valid bit after read all data. USB_EPRXCTL |= USB_EP_TX_RX_VALID;
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Clears the EP1~3 RX interrupt bit and returns from the interrupt service routine.
For isochronous transfer, the sequence sames to bulk transfer except the interrupt event is SOF interrupt
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Set the DMA start address to start the DMA DMA_CH1_ADDR = (iAddr >> 2);(if IN Token) DMA_CH0_ADDR = (iAddr >> 2);(if OUT Token) Reset the DMA FSM (if need) USB_CTRL = 0x01; USB_CTRL = 0x00; Set USB interface control registers. USB_CTRL = (dma_len << 8) | 0x02;(if IN Token) USB_CTRL = (dma_len << 8) | 0x06;(if OUT Token) Set USB BULK mode registers (if USB data flow is BULK). USB_BULK_DMA = 0x01; Wait until DMA finishes (interrupt from DMA controller)
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Set data valid bit (if USB data flow is ISO) USB_EPTXCTL |= USB_EP_TX_RX_VALID; (if IN Token) USB_EPRXCTL |= USB_EP_TX_RX_VALID; (if OUT Token) Clears the SOF interrupt bit and returns from the interrupt service routine. (if USB data flow is ISO)
For ISO transfer, length of each DMA operation cannot exceed 256 bytes. Please refer to charpter 9 for details of DMA operation.
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16.3 Initialization
The initialization has two parts: one for the Atlas, the other for the external PCMCIA host. For Atlas, the initialization sequence is: Enable Host Port clock and pins #define PWRCLK_HOST_EN PWR_PIN_RELEASE = 1; PWR_CLK_EN = PWRCLK_HOST_EN; RSC_PIN_MUX |= 0x10; Reset Host Port #define RESET_SR_HOST_RST RESET_SR = RESET_SR_HOST_RST; for(i = 0; i < 10; i++); RESET_SR = 0; Enable PCMCIA mode (HP_CONTROL) #define HP_PCMCIA_ENABLE HP_CONTROL = HP_PCMCIA_ENABLE; (0x01 << 1) 0x00080000 0x00002000
Reset the Host port (if needed) and Set the interrupt type (HP_CONFIG_OPTION_x) //HP_CONFIG_STATUS_REG_0 #define PCMCIA_FUNC_ENABLE #define PCMCIA_LEVEL_REQ #define PCMCIA_SRESET #define PCMCIA_CLR_SRESET (0x01 (0x01 (0x01 (0x00 << << << << 0) 6) 7) 7)
HP_CONFIG_OPTION_0 = PCMCIA_SRESET; for(i = 0; i < 10; i++); HP_CONFIG_OPTION_0= PCMCIA_CLR_SRESET | PCMCIA_LEVEL_REQ; Initialize Wait Counter (HP_PCMCIA_WAIT) HP_PCMCIA_WAIT = 0x8; Set the ENDIAN mode HP_PCMCIA_ENDIAN = 0x3; // input/output is big-endian
Activate one function of the four (for multiple function PC Card) (HP_PCMCIA_FUNC_ACTIVE) //PCMCIA_FUNCTION_ACTIVE #define HP_PCMCIA_FUNC0_ACTIVE (0x01 << 0) HP_PCMCIA_FUNC_ACTIVE = HP_PCMCIA_FUNC0_ACTIVE;
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Set the I/O Base address registers (HP_IO_BASE_LO & HP_IO_BASE_HI) #define IO_WINDOW_START_ADDR 0x170 HP_IO_BASE_LO_0 = IO_WINDOW_START_ADDR & 0xff; HP_IO_BASE_HI_0 = (IO_WINDOW_START_ADDR >> 8) & 0xff; Set the base address for all four sets of Function Configuration Registers (HP_CONFIG_BASE_ADDRESS_x) HP_CONFIG_BASE_ADDRESS_0 HP_CONFIG_BASE_ADDRESS_1 HP_CONFIG_BASE_ADDRESS_2 HP_CONFIG_BASE_ADDRESS_3 Configure CIS #define _HOST_MODULE_BASE #define TUPLE_LENGTH 0x80090000 98 = = = = 0x100; 0x120; 0x140; 0x160;
// Tuple data constant array unsigned char test_tuple[128] = { 0x01, 0x02, 0x00, 0xff, }; int i; //set config base address to cis
for(i = 0; i < TUPLE_LENGTH; i+=4) { *(unsigned *)(_HOST_MODULE_BASE + i) = *(unsigned *)(test_tuple + i); } Enable Host port interrupt (HP_INT_EN, HP_PCMCIA_INT_EN, and HP_CONFIG_INT_EN_x) //HP_INT_STATUS #define HP_PCMCIA_RESET_INT_MASK #define HP_PCMCIA_FUNC0_INT_MASK #define HP_PCMCIA_INT_MASK //HP_PCMCIA_INT_EN masks #define HP_PCMCIA_XSFER_INT //HP_CONFIG_INT_EN masks #define HP_CONIG_INT (0x01 << 2) (0x01 << 3) (0x01 << 8) (0x01 << 7) (0x01 << 0)
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE For the external PCMCIA host, please refer to the PCMCIA hosts spec.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE HP_FIFO_OP = 0x02; HP_FIFO_OP = 0x01; HP_FIFO_INT_EN = 0x07; // reset fifo // start fifo // oflow|uflow|threshold
Wait until DMA finishes (interrupt from DMA controller) Wait until data transfer finishes (HP_PCMCIA_STATUS) while (HP_PCMCIA_STATUS & 0x1);
After that, the Host port is ready for the next DMA trasnfer.
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After DMA and FIFO register are set, the bit 0 of SD_DMA_IO_CTRL is cleared for selecting DMA mode. Then the SD interface will read or write data between DMA and FIFO. When the DMA finish the data transfer, the bit 0 of SD_INT_STATUS will be set 1. The program will set the bit 0 of SD_DMA_IO_CTRL for choosing IO mode.
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17.5 Initialization
The SD interface must be reset when it is used in first time. The reset register of AltasTM is RESET_SR. The corresponding bit of reset bit of SD is bit 21. The SD_CARD_SEL register is set to select corresponding SD card such as 0x1 for selecting card 0. The maximum data rate of the SD cards is 25Mbps and the IO clock of AltasTM is beyond 25M for example 90M. So the SD_CLK_RATE register must be set to provide the different devision of IO clock to work with the SD card. If the program wants to use the interrupt mode, the SD_INT_CNTL and the SD_INTERRUPT_MASK will be set correct value.
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17.7.2
To operate the SD Memory Card adapter to perform a single block read, the application must first send the read command itself, such as the basic no data command response transaction, with some modifications: In the BLOCK_LEN register, the number of bytes per block must be specified. In the CMD_DAT_CONT, next bits are updated: o The format of response is updated to 01h (Bits 0 & 1). o The DATA En is set to 1 (Bit 2). o The write/read bit is set to 0 (Bit 3). o The stream block is set to 0 (Bit 4). o The multiple block is set to 0 (Bit 5). o The busy is set to 0 (Bit 7). o The initial bit is set to 0 (Bit 8) (If no initialize is required). o The WB bit is set as required. After the application read the response from the response FIFO registers, it must wait for the DATA_TRAN_DONE signal in the status register, and then reads the data transfer FIFO buffer.
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17.8.2
To operate the SD Memory Card adapter to perform a multiple block read, the application must first send the read command itself, such as the basic no data command response transaction, with some modifications: In the BLOCK_LEN register, the number of bytes per block must be specified. In the CMD_DAT_CONT, next bits are updated: o The format of response is updated to 01h (Bits 0 & 1). o DATA EN is set to 1 (Bit 2). o The write/read is set to 0 (Bit 3). o The stream block is set to 0 (Bit 4). o The multiple block is set to 1 (Bit 5). o The initial bit is set to 0 (Bit 8) (If no initialize is required). After the CMD_DAT_CONT has been written, the application must wait for the bit END_CMD_RES. At this point, the application reads the response from the response FIFO. The application must wait for the FULL_FIFO signal in the status register. Then, data must be read from the data FIFO (256 words, 16 bit each). The process of waiting for the FULL_FIFO signal and reading the FIFO is repeated until the last block. Before the last block, the application informs the adapter that the next block is the last block in the BUF_RDY register. After the adapter from the card has received the last block, the adapter stops the clock. After the last data block is received, the application sends the stop transmission command.
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17.8.3
To operate the SD Memory Card adapter to perform a multiple block write, the application must first send the write command itself, such as the basic no data command response transaction, with some modifications: In the BLOCK_LEN register, the number of bytes per block must be specified. In the CMD_DAT_CONT, next bits are updated: o The format of response is updated to 01h (Bits 0 & 1). o DATA EN is set to 1 (Bit 2). o The write/read is set to 1 (Bit 3). o The stream block is set to 0 (Bit 4). o The multiple block is set to 1 (Bit 5). o The busy bit is set to 0 (Bit 7). o The initial bit is set to 0 (Bit 8) (If no initialize is required). o The NOB_ON bit is set to 1 (bit 12). After the CMD_DAT_CONT has been written, the application does exactly what it specified in the section of Multiple Block Write above, until the last block. At the last block, the application set the Buffer Ready and Last Buffer. The application waits for the end of the busy signal by waiting for the PROG_DONE signal in the status or sending the send status command to the card and checking the state of the card in the response.
17.8.4
To operate the SD Memory Card adapter to perform a multiple block read, the application must first send the read command itself, such as the basic no data command response transaction, with some modifications: In the BLOCK_LEN register, the number of bytes per block must be specified. In the CMD_DAT_CONT, next bits are updated: o The format of response is updated to 01h (Bits 0 & 1). o DATA EN is set to 1 (Bit 2). o The write/read is set to 0 (Bit 3). o The stream block is set to 0 (Bit 4). o The multiple block is set to 1 (Bit 5). o The initial bit is set to 0 (Bit 8) (If no initialize is required). o The NOB_ON bit is set to 1 (bit 12). After the CMD_DAT_CONT has been written, the application must wait for the bit END_CMD_RES. At this point, the application reads the response from the response FIFO. The application must wait for the FULL_FIFO signal in the status register. Then, data must be read from the data FIFO (256 words, 16 bit each). The process of waiting for the FULL_FIFO signal and reading the FIFO is repeated until the last block. Before the last block, the application informs the adapter that the next block is the last block in the BUF_RDY register. After the adapter from the card has received the last block, the adapter stops the clock.
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18.2 Initialization
Some registers need not to be set before every operation. WAIT_REG. This register need to be set if the IOCLK changes.
Get timing characteristic from SmartMedia/DataFlash specification tWP: WE# Pulse Width. Normally 25nS tRP: RD# Pulse Width. Normally 30nS tWH: WE# High Hold Time, Normally 15nS tREH: RD# High Hold Time, Normally 15nS tWB: WE# High to Busy. Normally 100nS tRB: Last RE# High to Busy(at sequential read). Normally 100nS IOCLK: MHz
When COMMAND ADDRESS FSM start, the Nand Flash interface first send COMMAND_REG<7:0> to DATAFLASH, then according to the value of this register, it will send LOW_ADDRESS_REG<31:0> and HIGH_ADDRESS_REG<7:0> to Nand Flash PAGESIZE_REG. This register default value is 528, which is SmartMedia page size. Only SAMSUNGs more than 128MB Nand Flash page size is 2112 bytes DIRECT_READ. This register is used for NANDBOOT, after hardware reset, the value or this register is 1, and RISC can directly read data from SmartMedia. In normal read/write this register need to be set to 0.
18.3.1
IO Read
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 1. Set DMA_IO_CTRL_REG to 5b00011 2. If you want to use interrupt, then clear interrupt by write 4b1111 to INT_STATUS_REG. And enable FIFO_THRESHOLD interrupt by setting INT_CTRL_REG to 4b1000. And set FIFO_CTRL_REG to the number of bytes you want to read every read operation. If you want to use RISC check FIFO_STATUS_REG, then disable interrupt by setting INT_CTRL_REG to 0. 3. Write LOW_ADDRESS_REG and HIGH_ADDRESS_REG according to the address you want to read. 4. Write Nand Flash read command to COMMAND_REG. This will make the interface to write command and address to Nand Flash. 5. Wait for FIFO_THRESHOLD interrupt or check FIFO_STATUS_REG register, and then read FIFO_DATA_REG register. 6. Repeat step 5.
18.3.2
IO Write
1. Set DMA_IO_CTRL_REG to 5b00001 2. If you want to use interrupt, then clear interrupt by write 4b1111 to INT_STATUS_REG. And enable FIFO_THRESHOLD interrupt by setting INT_CTRL_REG to 4b1000. And set FIFO_CTRL_REG to the number of bytes you want to read every read operation. If you want to use RISC check FIFO_STATUS_REG, then disable interrupt by setting INT_CTRL_REG to 0. 3. Write LOW_ADDRESS_REG and HIGH_ADDRESS_REG according to the address you want to read. 4. Write Nand Flash sequential data input command to COMMAND_REG. This will make the interface to write command and address to Nand Flash. 5. Repeat this step until you have write all datas, or you have write one page data(currently one page =528 bytes) 6. Set DMA_IO_CTRL_REG to 5b10000 7. Clear interrupt by write 4b1111 to INT_STATUS_REG. Set INT_CTRL_REG to 4b0010 to enable COMMAND ADREESS DONE interrupt. 8. Write Nand Flash page program command to COMMAND_REG register 9. Wait for COMMAND ADDRESS DONE interrupt.
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 4. Clear interrupt by write 4b1111 to INT_STATUS_REG. Set INT_CTRL_REG to 4b0100 to enable DMA DONE interrupt. 5. Write Nand Flash read command (or sequential data input command) to COMMAND_REG register. This will make the Nand Flash interface go into DMA transfer. 6. Wait for DMA DONE interrupt. 7. If this is DMA write operation, the following step is needed. 8. Clear interrupt by write 4b1111 to INT_STATUS_REG. Set INT_CTRL_REG to 4b0010 to enable COMMAND ADREESS DONE interrupt. 9. Write Nand Flash page program command to COMMAND_REG register 10. Wait for COMMAND ADDRESS DONE interrupt.
SMDF_DMA_IO_CTRL_REG =; SMDF_ADD_NUM_REG = 3; //assume the Nand Flash is less than 64MBytes SMDF_LOW_ADDRESS_REG = (address>>1) & 0xFFFFFF00 + address & 0xFF; //delete address bit 9 SMDF_FIFO_LEVEL_CHK_REG = 0x40200C; //set FIFO check level SMDF_FIFO_OP_REG = 1; //start FIFO SMDF_DMA_IO_LEN_REG = 528; //write 528 bytes SMDF_COMMAND_REG = 0x80; DMA_CH4_CTRL = 0xC; //DMA burst write
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE DMA_CH4_XLEN = 528>>2; DMA_CH4_ADDR = ((DWORD) ram_addr)>>2; While ((SMDF_INT_STATUS_REG &0x4)==0); //wait Nand Flash interface DMA interrupt SMDF_FIFO_OP_REG =2; //stop FIFO SMDF_INT_STATUS_REG = 2; SMDF_INT_CTRL_REG = 2; SMDF_DMA_IO_CTRL_REG = 0x10; SMDF_ADD_NUM_REG = 0; Nand Flash SMDF_COMMAND_REG = 0x10; While ((SMDF_INT_STATUS_REG &0x2)==0); //wait Nand Flash interface COMMAND ADDRESS interrupt //clear interrupt //enable interrupt //set to NO_READWRITE //did not need address when program to
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ARM init process Flash Controller's global register init process select first Nand Flash chip Read Device ID select next Nand Flash chip
NO
NO
find? YES read "NK.BIN" and parse it lauch to WinCE startup code
Figure 12. NAND Boot Flow Diagram
18.7.1
When RISC boots up, it shadows Nand flash memory space to 0, read code directly from Nand flash. In this stage, RISC performs all the initialization required before branching to the main C application code. Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 171 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE It defines the ENTRY point, initializes the Stack Pointers for each mode, copies RO code and RW data from FLASH to RAM and zero-initializes the ZI data areas used by the C code, and jump to C_Entry.
18.7.2
In this stage, a) b)
Enables the clock of Flash controller and DMA controller PWR_CLK_EN = 0x6; Commit share hardware resources to Nand flash controller PWR_PIN_RELEASE = 1; ROM_NAND_FIFO_SELECT = 1; RSC_PIN_MUX = SMDF_NAND_CS_0 | SMDF_NAND_CS_1 |SMDF_NAND_CS_2 | SMDF_NAND_CS_3 | SMDF_CKE_EN | SMDF_CSB_EN; Enable DMA interrupt INT_RISC_MASK = INT_MASK_DMA_CTRL; INT_RISC_LEVEL = 0; Change Flash controller from boot read mode to normal read mode. In boot mode, ARM can only directly read data from the controllers register, in normal mode, ARM/DMA controller can only read data from FIFO SMDF_DIRECT_READ_REG = 0; Disable Nand flashs all interrupts SMDF_INT_CTRL_REG = 0; Set Nand flashs FIFO level check register. This is set for DMA burst read. SMDF_FIFO_LEVEL_CHK_REG = 0xC02004;
c)
d)
e) f)
18.7.3
Read Device ID
In this stage, read device ID, compare it with the device ID table. If this is a valid device ID Set Nand flash controllers register: ADDRESS_NUM_REG according to the flash type. More than 32Mbyte flash need set to 4, less than 32M-byte need set to 3.
18.7.4
Search from the last block to check whether it is a good block, if it is a good block, the NK.BIN is start from this block, else read next block. If reading 5 blocks and not find good block, there is no NK.BIN in this Nand Flash chip.
18.7.5
There is 2 bytes in the page spare area to indicate the next block location, according this information read all the NK.BIN to SDRAM, then parse it. For detail Nand Boot specifacation, please read Nand Boot software document. Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 172 -
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19.2 Initialization
The LCD controller can be reset by four sources of resets. Please refer to Section 5.7 Reset Controller Overview for details. After hardware reset, the LCD controller is disabled, and the output pins are configured as GPIO pins or resource sharing pins. And after any type of reset, all LCD controller registers are reset to the default values shown in the LCD register definitions. If the LCD controller is being enabled for the first time after hardware reset, following registers must be programmed to enable the LCD controller: Configure power manager clock enable register (PWR_CLK_EN) to enable LCD controller system clock. See Developers Manual Section 5.6 Power Manager for details. Configure resource sharing pin multiplex register (RSC_PIN_MUX) for LCD controller functionality. See Developers Manual Section 5.8 Resource Sharing Controller for details. Reset the LCD controller (RESET_SR), and set the relative interrupt registers for LCD controller (such as INT_RISC_MASK/ INT_DSP_MASK and INT_RISC_LEVEL, see Developers Manual Section 5.3 Interrupt Controller for details, and LCD_INT_MASK, and so on), if needed Configure Timing Control Register (LCD_TIMCTRL) to set the LCD controller as master mode or slave mode, that is, set L_PCLK, L_LCLK or L_FCLK as outputs or inputs. Configure power manager pin release register (PWR_PIN_RELEASE) to release pins of peripherals (include LCD pins). Write color palette or grey palette (FRC sequence table) to the on-chip RAM of LCD controller for color or grey displays, if needed Program all of the LCD registers required except the DMA start registers (LCD_SCN_CUR_Y/ LCD_OSD_CUR_Y and LCD_SCN_ADDR/LCD_OSD_ADDR) and the Frame Valid bit (bit0 of DISPLAYMODE register), such as the active region registers, screen control registers, sync signal generation registers (only for master sync mode), and so on. Write 1 to DMA start registers (LCD_SCN_CUR_Y/LCD_OSD_CUR_Y and LCD_SCN_ADDR/ LCD_OSD_ADDR) to start the DMA Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 174 -
**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Write 1 to the Frame Valid bit to output the valid image frame to data pins
As L_PCLK, L_LCLK and L_FCLK can be configured as inputs or outputs, and after reset these signals are defaulted as outputs when LCD controller is enabled, the LCD_TIMCTRL register should be configured correctly before releasing pins of peripherals (PWR_PIN_RELEASE register) to avoid pin conflicts with external signals. When there is no pin conflict, the LCD_TIMCTRL register can also be configured after PWR_PIN_RELEASE registers configuration. The Frame Valid bit control the internal counters for internal valid signals, and can not be asserted too earlier before the DMA starts (otherwise, the FIFOs will underflow). So for safety, you may assert the Frame Valid bit after the DMA starts. For LCD controller interrupt, there are two levels of interrupts (one is in the level of Atlas-1Interrupt Controller, the other is in the level of LCD controller). To enable the LCD controller interrupts, both the two levels of interrupts must be enabled. Following is a typical 8-bit/pixel master mode configuration example for the 240 x 320 TFT LCD panel. #define PWRCLK_LCD_EN #define INT_MASK_LCD_CTRL #define RESET_SR_LCD_RST 0x00000008 0x01000000 0x00000020
PWR_CLK_EN |= PWRCLK_LCD_EN; /* Enable LCD controller system clock */ RSC_PIN_MUX |= 0x1; /* Enable LDD<15:8> as the LCD data pins */ PWR_PIN_RELEASE = 0x1; /* Release the peripheral pins including LCD pins */ /* Initiate interrupt controller for LCD controller */ INT_RISC_MASK |= INT_MASK_LCD_CTRL; /* Enable LCD interrupt in the level of Interrupt Controller */ /* LCD controller software reset */ RESET_SR |= RESET_SR_LCD_RST; /* Reset declare */ RESET_SR &= ~( RESET_SR_LCD_RST); /* Reset clear */ LCD_OSC_RATIO = 0x1006; /* Pixel clock is 1/7 sysclk. If system clock is 42MHz, pixel clock is 6MHz */ Write_palette ( ); /* Fill in 256 color palette for 8-bit per pixel mode */ /* SYNC_GEN (LCD_HSYNC_PERIOD, LCD_HSYNC_WIDTH, LCD_VSYNC_PERIOD, LCD_VSYNC_WIDTH) */ /* HSYNC period is 290, HSYNC pulse width is 9 pixels; VSYNC period is 332, VSYNC pulse width is 2 lines */ SYNC_GEN (288, 8, 332, 0x802); /* SCN_REGION (LCD_SCN_HSTART, LCD_SCN_VSTART, LCD_SCN_HEND, LCD_SCN_VEND) */ /* Set to display a 240x320 image, 267-28 = 239, 328-8 = 320 */ SCN_REGION (28, 8, 267, 328); LCD_BLANK = 0x01000000; /* Set blank value to all zero */ LCD_TIMCTRL = 0x52; /* Master mode Syncs and Pixclk */ LCD_DISPLAYMODE = 0x212; /* little endian, 8-bit per pixel, 5:6:5 output, Frame Valid =0 */ Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 175 -
/* Configure the FIFO High, Middle, Low Threshold */ LCD_SCNFIFO = 0x183858; /* DMA_SETUP (LCD_SCN_XSIZE, LCD_SCN_YSIZE, LCD_SCN_SKIP, LCD_SCNFIFO_SUPPRESS, LCD_SCNBASE) */ /* Line size is 15 4-DWORD bursts = 15*4*4 = 240 pixels (for 8bit/pixel mode), 320 lines, the DMA base address is 0x800000, continuous screen DMA */ DMA_SETUP (14, 319, 0x10, 0x0, 0x88000000); /* Start screen DMA channel */ LCD_SCN_CUR_Y = 0x1; LCD_SCN_ADDR = 0x1; LCD_DISPLAYMODE |= 0x1; /* Frame Valid =1 */
INT_RISC_MASK |= INT_MASK_LCD_CTRL; /* Enable LCD interrupt in the level of Interrupt Controller */ LCD_INT_MASK |= SCN_DMA_MASK; /* Enable screen DMA interrupt in the level of LCD Controller */ /* Configure the FIFO High, Middle, Low Threshold, and select the other method of request generation */ LCD_SCNFIFO = 0x1183858; Atlas Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 176 -
/* Screen DMA channel set up */ LCD_SCN_XSIZE = 29; /* Line size is 30 4-DWORD bursts, for 16bit/pixel mode, its 240 (30x4x2) pixels. */ LCD_SCN_YSIZE = 119; /* This DMA includes 120 Lines */ LCD_SCN_SKIP = 0x10; /* The DMA address generator skips 16 Bytes between lines of DMA, as the DMA unit supported is a burst, therefore it means that the beginning of the second line is continuous with the ending of the first line. */ LCD_SCNFIFO_SUPPRESS = 0x0; /* If there arent any DWORDs to be suppressed, set this register as 0x0 */ LCD_SCNBASE = 0x8000000; /* Single DMA, the DMA base address is 0x800000, pixel offset is 0. */ /* Start screen DMA channel */ LCD_SCN_CUR_Y = 0x1; LCD_SCN_ADDR = 0x1; This DMA channel will transfer 120 x 30 x 4 DWORDs data every one time. Therefore, different pixel depths and different resolutions will lead to different DMA configurations. Generally, for a DMA transfer of M pixels/Line x N Lines data block with the pixel depth of D bits/pixel, XSIZE and YSIZE are decided by following equations: XSIZE = (M x D)/(4 x 32) 1 YSIZE = N 1 Obviously, XSIZE and YSIZE must be interger. And if the XSIZE and the YSIZE are non-interger when computed by these two equations, multiple lines can be combined as one DMA line to make the XSIZE as interger. In addition, when pixel offset is non-zero, XSIZE will be increased by 1, and the SUPPRESS register should also be configured. Please refer to FIFO write suppress registers in Developers Manual Section 9.5.4 for details.
The differences between master mode and slave mode are shown in the follwing table: Table 12. Differences between Master and Slave Mode Registers Master Mode PCLK_IO = 1 (default) LCD_TIMCTRL HSYNC_IO = 1 (default) Register VSYNC_IO = 1 (default) For master pixel clock, this register LCD_OSC_RATIO should be configured to obtain the Register pixel clock from the system clock. Should be configured according to Sync Signal the LCD display requirements. generation Registers Slave Mode PCLK_IO = 0 HSYNC_IO = 0 VSYNC_IO = 0 For slave pixel clock, this register needs not to be configured. Need not to be configured.
Note that the pixel clock and the sync signals can be configured as master or slave mode independently.
19.5 Palette
The palette in the LCD controller is a 256 x 18bit RAM. And this palette can be used as color palette or grey palette of dithering sequence for FRC.
19.5.1
Color Palette
When the image data are 4bit or 8bit per pixel, the 4bit or 8bit data are directly as the index of palette entries. Basically, this color palette should be matched with the one that is provided for the image data. For example, if the image data is got from WINDOWS, then the color palette in the LCD controller should be matched with the palette that WINDOWS provides. For the 4bit/pixel data, the bottom 16 entries are used, and for the 8bit/pixel data, all the 256 entries are used.
19.5.2
The grey palette is a 16 x 32bit FRC sequence table that is located in the 256 x 18bit RAM (256 entries). Thus the FRC can support up to 16 grey scales. For 4bit/pixel mode, bits <15:0> of entry 0 and entry 16 combine as 32 bits for one gray color, and bits <15:0> of entry 1 and entry 17 as another gray color, and so on. And for 2bit/pixel mode, only entry 0~3 and entry 16~19 are used. The FRC is actually a time-based dithering, which is to turn each pixel on or off in a certain period of time to create the perception of different intensities. For every pixel, the sequence repeats itself every 32 frames. Higher 0 to 1 transition frequency within 32 frames will result in better picture quality. Following is a FRC sequence table recommended. Table 13. Index 0000 0001 0010 0011 0100 0101 0110 0111 1000 FRC Sequence Table Example Entry (16 + Index) Entry (Index) 0000,0000,0000,0000 0000,0000,0000,0000 0000,0001,0000,0001 0000,0001,0000,0001 0000,1000,0010,0001 0000,1000,0010,0001 0001,0001,0001,0001 0001,0001,0001,0001 0001,0010,0100,1001 0001,0010,0100,1001 0010,0101,0010,0101 0010,0101,0010,0101 0010,1001,0100,1010 0101,0010,1001,0101 0010,1010,0101,0101 0010,1010,0101,0101 0010,1010,1010,1010 0101,0101,0101,0101 Frequency 0/32 4/32 6/32 8/32 10/32 12/32 13/32 14/32 15/32 Intensity 0/32 4/32 6/32 8/32 10/32 12/32 13/32 14/32 15/32
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**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 1001 1010 1011 1100 1101 1110 1111 0101,0101,0101,0101 0101,0101,0101,0101 0101,0101,1010,1011 0101,1011,0101,1011 0110,1101,1011,0111 0111,0111,0111,0111 1111,1111,1111,1111 0101,0101,0101,0101 1010,1010,1010,1011 0101,0101,1010,1011 0101,1011,0101,1011 0110,1101,1011,0111 0111,0111,0111,0111 1111,1111,1111,1111 16/32 15/32 14/32 12/32 10/32 8/32 0/32 16/32 17/32 18/32 20/32 22/32 24/32 32/32
19.6.2
There are two FIFOs (Screen FIFO and OSD FIFO) for temporarily storing the image data loaded from memory in the LCD controller. Two methods of DMA requests generation are supported. The first or normal method is better used in real time environment as this method will generate DMA requests scatteredly, and every request will be deasserted after a few bursts are received. While the second method (selected when REQ_SEL=1) will generate DMA requests more centralized, and every request will be deaserted after more bursts are obtained. As the switching among different memory access masters will waste some memory bus bandwidth, centralized request method will save the bandwidth than the normal method. In addition, as there are some delays between request generation and data reception in memory controller, margins should be given to avoid FIFO underflow or overflow when set the high request watermark or the low request watermark. Dont set the high request watermark far below 0x10, and the low request watermark far beyond 0x70. Please also refer to the Developers Manual Section 9.5.4 FIFO control registers for details.
20 Revision History
REVISION 0.1 0.2 0.3 0.4 DATE 3/27/03 4/8/03 4/8/03 4/9/03 DESCRIPTION Prepare a bare-bone of the programming guide Added detail for Clocks & Power Manager, Camera, SD, and USB Added details for LCD controller Added details for RSC, DMA controller, PCMCIA, Extension Port, USP, CODEC, Host Port, and LCD controller Added details for RISC Interface, DSP Interface, Memory Interface, and GPIO Added more details for LCD controller and NAND Flash controller AUTHOR Hongyu Zhang Hongyu Zhang, Yu Li, Jinfeng Zhan, and Xianshi Cui Hongyu Zhang and Xiaoyi Qing Hongyu Zhang, Jun Mo, Lianxue Xiong, Peng Yong, and Xiaoyi Qin Hongyu Zhang, Jun Mo and Qingyi Sheng Hongyu Zhang, Xiaoyi Qin, and Tiefeng Liu
0.5 0.6
4/10/03 4/15/03
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