EASWARI ENGINEERING COLLEGE ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT LABORATORY MANUAL

ACADEMIC YEAR: 2010-2011

SUBJECT

: CS 2207 DIGITAL ELECTRONICS LAB

DEPARTMENT : CSE (III SEM)

Prepared By 1. Mrs.Jeswin Veancy 2. Mrs.D.Vydeki

Reviewed By Mr.B.Sridhar

Approved By HoD/ECE

University Syllabus
CS 2207 1. 2. DIGITAL ELECTRONICS LAB 0 0 3 2

Design and implementation of Adder and Subtractor using logic gates. Design and implementation of code converters using logic gates (i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa

3. 4. 5. 6. 7. 8. 9.

Design and implementation of 4 bit binary Adder/ subtractor and BCD adder using IC 7483 Design and implementation of 2 bit Magnitude Comparator using logic gates 8 Bit Magnitude Comparator using IC 7485 Design and implementation of 16 bit odd/even parity checker generator using IC74180. Design and implementation of Multiplexer and De-multiplexer using logic gates and study of IC74150 and IC 74154 Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147 Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters Design and implementation of 3-bit synchronous up/down counter

10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops 11. Design of experiments 1, 6, 8 and 10 using Verilog Hardware Description Language

INDEX S. No. Date Name of the Experiment Marks Sign

INDEX S. No. Date Name of the Experiment Marks Sign

Exp.No: 1 Date:

STUDY OF LOGIC GATES

AIM: To study the working of the logic gates and verify their truth tables. COMPONENTS REQUIRED: S.No. Apparatus 1. IC Trainer kit 2. Logic gate ICs 3. Logic gate ICs 4. connecting wires Specifications -IC 7404, IC 7408, IC 7432 IC 7402, IC 7400, IC 7486 -Quantity 1 no 1no each 1no each 1 set

THEORY: Positive Logic: In Positive Logic, +5 V is associated with Binary 1 while GND is associated with Binary 0. Negative Logic: In Negative Logic, +5 V is associated with Binary 0 while GND is associated with Binary 1. Gates: Electronic circuits whose terminal characteristics correspond to various Boolean operations area called as Gates. AND gate: It has one output and two or more inputs. The output will equal 0 for all combinations of input values except when all inputs equal 1. OR gate: It has one output and two or more inputs. If all inputs are caused to equal 0, the output will also equal 0. The presence of a 1 bit at one or more inputs leads to an output of 1. NOT gate: It produces the INVERT operation. This logic element has one input and one output. The output level is always opposite to the input level. Universal gates: Universal gates are the ones which can be used for implementing any Boolean function using gates like AND, OR and NOT, or any combination of these basic gates; NAND and NOR gates are universal gates. But there are some rules that need to be followed when implementing NAND or NOR based gates. NOR gate: It is simply an OR gate followed by a NOT gate. NAND gate: It is simply AND gate followed by a NOT gate.

EX-OR gate: It is expanded as Exclusive-OR gate. It has one output and two or more inputs. It produces an output of 1 if the inputs are of different logic levels and an output 0 if inputs are of the same logic level.

LOGIC GATES :
AND GATE NAND GATE

IC 7408

IC 7400

TRUTH TABLE
A 0 0 1 1 B 0 1 0 1 Y=A.B

TRUTHTABLE
A 0 0 1 1 B 0 1 0 1 Y=A.B

OR GATE

NOR GATE

IC 7432

IC 7402

TRUTH TABLE
A 0 0 1 1 B 0 1 0 1 Y=A+B

TRUTH TABLE
A 0 0 1 1 B 0 1 0 1 Y=A+B

NOT GATE

EX OR GATE

IC 7404 TRUTH TABLE A 0 0 Y=A

IC 7486 TRUTH TABLE A B 0 0 0 1 1 0 1 1 EX-NOR GATE:

TRUTH TABLE A 0 0 1 1 B 0 1 0 1

PROCEDURE: 1. Place the IC on the IC trainer kit and give the supply and ground connections. 2. Apply the inputs to the logic gates through the input switches. 3. Observe the output of the gates in the LED indicators. 4. Verify the truth table of each logic gate. RESULT: Thus the working of the logic gates was studied and their truth tables were verified.

Exp.No: 3 Date:

IMPLEMENTATION OF BOOLEAN FUNCTIONS

AIM: To implement and verify the given Boolean function using logic gates. COMPONENTS REQUIRED: S.No. 1. 2. 3. 4. Apparatus IC Trainer kit Logic gate ICs Logic gate ICs Connecting wires Specifications -IC 7404, IC 7432 IC 7408 -Quantity 1 1 2 Few

Given function is: F= TRUTH TABLE:

LOGIC DIAGRAM OF GIVEN BOOLEAN FUNCTION:

K MAP SIMPLIFICATION:

LOGIC DIAGRAM OF SIMPLIFIED BOOLEAN FUNCTION:

Procedure: 1. Draw the truth table for the given Boolean function. 2. Determine the simplified expression for the output variable using K-Map. 3. Decide the corresponding logic gates to be used to implement the Boolean function simplified using K-Map. 4. Draw the logic diagram according to simplified Boolean function. 5. Construct the logic circuit using the above gates. 6. Verify the truth table. Result: Thus, the given Boolean function is implemented and verified using logic gates. Viva Questions 1) What is K-map? 2) What is the use of K-Map 3) What are the limitations of K-Map 4) Give the other name for K-Map 5) What is a prime implicant 6) What are dont care terms 7) What is meant by an incompletely specified function 8) Distinguish between incompletely specified function and completely specified function 9) Explain the general procedure that could be adopted in reducing Boolean expression 10) List the two types of standard forms in Boolean algebra 11) Give the two canonical forms of Boolean function 12) What is a min term and max term 13) What are hybrid functions

Exp.No: 4 Date:

DESIGN AND IMPLEMENTATION OF ADDERS AND SUBTRACTOR

AIM:

a. To design a half adder / subtractor and verify the function

b. To design a full adder / subtractor and verify the function. c. Realize a full adder using two half adders and logic gates. APPARATUS REQUIRED: S.NO 1 2 3 4 COMPONENTS IC 7408 IC 7486 IC 7404 IC TRAINER KIT RANGE/TYPE AND EX-OR NOT QUANTITY 1 1 1 1 FEW

5 CONECTING WIRES THEORY:

HALF ADDER: Half adder is a circuit, which can add two numbers and produce two outputs, sum and carry. From the truth table it is clear that sum represent the logic output of an EX-OR gate and carry, that of an AND gate. Thus a half adder can be built using two gates. FULL ADDER:When the carry is generated by the addition of two bits, this has to be added to next bit sum. Half adders do not allow this. There are only two inputs present. A full adder can be used for this purpose. Here three inputs are given, addend augends and the previous carry. SUBTRACTORS:The subtraction of two binary numbers is done by either taking twos complement of subtrahend and adding the numbers or by direct method where bitsubtraction is carried out to form a difference bit and if necessary, a borrow-bit just as in adders, there are half and full subtractor. HALF SUBTRACTORS:The two inputs, minuend and subtrahend are given to get two outputs, difference and borrow. It is found that D is the same as S output of Half adder and B resemble C of half adder except that input A is complemented.

FULL SUBTRACTORS:This performs subtraction between two bits, taking into account that one may have been borrowed by a lower significant stage. Three inputs minuend, subtrahend and previous borrow to get two outputs borrow and difference.

HALF ADDER:
TRUTH TABLE:

INPUT A B 0 0 0 1 1 1 0 1

OUTPUT SUM CARRY

Logic Diagram Of Half Adder

HALF SUBTRACTOR: TRUTH TABLE:

INPUT A B 0 0 0 1 1 1 0 1

OUTPUT DIFFERENCE BORROW

Logic Diagram Of Half Subtractor

FULL ADDER: TRUTH TABLE

INPUT A B Cin 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1

OUTPUT SUM CARRY

Logic Diagram Of Full Adder

FULL SUBTRACTOR: TRUTH TABLE: A 0 0 0 0 1 1 1 1 INPUT B Cin 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 OUTPUT DIFF BORROW

Logic Diagram of Full Subtractor

PROCEDURE: 1. Draw the truth table of the respective adder/subtractor. 2. Determine the simplified expression for the output variable using K-Map. 3. Decide the corresponding logic gates to be used to implement the above expression. 4. Draw the logic diagram according to output expression. 5. Construct the adder/Subtractor circuit using the above gates. 6. Verify the truth table.

RESULT: Thus the full/half adder and subtractor circuits were designed and constructed and the truth tables were verified.

Viva Questions
1) Define half adder and full adder 2) Design half adder using only NAND gates 3) Design half adder using only NOR gates 4) Design half adder using only EX-OR and AND gates 5) Design full adder using only NOR gates 6) Distinguish between Half adder and full adder

Exp.No: 5 Date:

DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING LOGIC GATES

AIM: To design and implement the code converters using logic gates. 1. BCD to EXCESS-3 code 2. EXCESS-3 to BCD code 3. BINARY to GRAY code 4. GRAY to BINARY code APPARATUS REQUIRED: S.NO 1 2 3 4 5 6 7 COMPONENTS IC 7486 IC 7408 IC 7432 IC 74266 IC 7404 IC TRAINER KIT CONNECTING WIRES RANGE/TYPE EX-OR AND OR EX-NOR NOT QUANTITY 2 2 1 1 1 1 FEW

THEORY: BCD TO EXCESS-3 CODE CONVERTER: EXCESS-3 code is a modified form of BCD NUMBER. The EXCESS-3 code can be derived from a natural a BCD code by adding three to each coded number. BCD is a numeric code in which each digit of a decimal number is represented by a separate group of bits. The most common BCD code is 8421BCD, in which each decimal digit is represented by a four bit binary number. For eg.decimal-12 can be represented in BCD as 0001 0010. Now adding three to each digit we get EXCESS-3 code as 0100 0101.

EXCESS-3 TO BCD CODE CONVERTER: EXCESS-3 code is a modified form of BCD number. In EXCESS-3 code we get 9s complement of a number by just complementing each bit. Due to this EXCESS-3 code is called self-complementing code. The BCD code can be derived from EXCESS-3 code by subtracting three to each coded number. For eg.0100 0101(12 in decimal) EXCESS-3 Code is converted to BCD as 0001 0010 by subtracting 3 to each digit. BINARY TO GRAY CODE CONVERTER: The GRAY code is often used in digital systems because it has the advantage that only one bit in the numerical representation changes between successive numbers. The binary to gray code conversions performed by ex-ploring the present input with previous successive bit. Gray code is a unit distance code. In this the two consecutive numbers differ in only one bit position. In gray code the possibility of errors are reduced. GRAY TO BINARY CODE CONVERTER: In gray to binary code conversion, the MSB of binary number is same as the MSB of gray code number. The next binary digit is obtained by performing an ex-or operation between the previous binary bit obtained and the next gray code bit.

BCD TO EXCESS 3 CODE CONVERSIONS

TRUTH TABLE

BCD (Input) A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1

EXCESS3 (Output) W 0 0 0 0 0 1 1 1 1 1 X 0 1 1 1 1 0 0 0 0 1 Y 1 0 0 1 1 0 0 1 1 0 Z 1 0 1 0 1 0 1 0 1 0

K-map Simplification

Logic Diagram of BCD to Excess-3 Converter:

EXCESS-3 TO BCD CODE CONVERTER:

TRUTH TABLE

EXCESS3 (Input) W 0 0 0 0 0 1 1 1 1 1 X 0 1 1 1 1 0 0 0 0 1 Y 1 0 0 1 1 0 0 1 1 0 Z 1 0 1 0 1 0 1 0 1 0 A 0 0 0 0 0 0 0 0 1 1

BCD (Output) B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1

K-Map Simplification: K-map for D: K-map for C:

K-map for B:

K-map for A:

Logic Diagram of Excess-3 to BCD Converter:

BINARY TO GRAY TRUTH TABLE INPUTS(Binary Code) B3 B2 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 OUTPUTS (Gray Code) G3 G2 G1 G0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1

K-Map Simplification

Logic Diagram of Binary to Gray Converter

GRAY TO BINARY Truth Table INPUT(Gray Code) G3 G2 G1 G0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 OUTPUT (Binary Code) B3 B2 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

K-MAP SIMPLIFICATION K-Map for B0

G1G0 G1G0

K-Map for B1

K-Map for B2
G1G0 G1G0

K-Map for B3

Logic Diagram of Gray To Binary Converter

PROCEDURE: 1. Draw the truth table of the respective converter. 2. Determine the simplified expression for the output variable using K-Map. 3. Decide the corresponding logic gates to be used to implement the above expression. 4. Draw the logic diagram according to output expression. 5. Construct the converter circuit using the above gates. 6. Verify the truth table. RESULT: Thus the code converters were designed and implemented using logic gates and its truth tables were verified.

Viva Questions 1) What is code converter? 2) What is a weighted code? Give example. 3) What is a non-weighted code? Give example 4) What is the difference between binary code and BCD code? 5) Distinguish between weighted code and non-weighted code 6) Explain the uses of Excess-3 code 7) Show that Excess-3 code is self complementing 8) What is gray code 9) What are the advantages of gray code 10) What are error-detecting codes? Give example 11) What are error-correcting codes? Give example 12) Error correctable codes are Error detectable. True or False 13) Error detectable codes are Error correctable. True or False 14) What is an alpha numeric code? 15) Why ASCII code has seven bits? 16) What is Hollerith code? 17) What is Sequential code? 18) What is reflective code?