LTC1546 Software-Selectable Multiprotocol Transceiver with Termination

FEATURES
s s

DESCRIPTIO

s s s s s

Software-Selectable Transceiver Supports: RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21 TUV Telecom Services Inc. Certified NET1, NET2 and TBR2 Compliant On-Chip Cable Termination Pin Compatible with LTC1543 Complete DTE or DCE Port with LTC1544 Operates from Single 5V Supply Small Footprint

APPLICATIO S
s s s

Data Networking CSU and DSU Data Routers

The LTC1546 is a 3-driver/3-receiver multiprotocol transceiver with on-chip cable termination. When combined with the LTC1544, this chip set forms a complete softwareselectable DTE or DCE interface port that supports the RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21 protocols. All necessary cable termination is provided inside the LTC1546. In most applications, the LTC1546 replaces both an LTC1543 and an LTC1344A without any changes to the PC board. The LTC1546 runs from a single 5V supply using an internal charge pump that requires only five space-saving surface mounted capacitors. The LTC1546 is available in a 28-lead SSOP surface mount package.
, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATION
Complete DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
LL CTS DSR DCD DTR RTS RXD RXC TXC SCTE TXD

LTC1544 D4 R4 R3 R2 R1 D3 D2 D1 R3 R2

R1

18
LL A (141)

13 5
DSR B CTS B CTS A (106)

22 6
DSR A (107)

10 8
DCD B DCD A (109)

23 20 19 4
DTR B DTR A (108) RTS B RTS A (105) SHIELD (101)

1
SG (102)

16
RXD B

3
RXD A (104)

9
RXC B

17
RXC A (115)

DB-25 CONNECTOR
1546 TA01

U
LTC1546 D3 D2 D1 T T T 12
TXC B

15 11
TXC A (114) SCTE B

24 14
SCTE A (113) TXD B

2
TXD A (103)

LTC1546

ABSOLUTE
(Note 1)

AXI U

RATI GS

PACKAGE/ORDER I FOR ATIO

TOP VIEW C1 C1+ VDD VCC D1 D2 D3 R1 R2 1 2 3 4 5 D1 6 7 8 9 T R3 10 M0 11 M1 12 M2 13 DCE/DTE 14 G PACKAGE 28-LEAD PLASTIC SSOP R2 R3 T 17 R2 B 16 R3 A T 15 R3 B R1 19 D3/R1 B 18 R2 A D2 D3 T T 23 D1 B 22 D2 A 21 D2 B 20 D3/R1 A CHARGE PUMP 28 C2 + 27 C2 26 VEE 25 GND 24 D1 A

Supply Voltage ....................................................... 6.5V Input Voltage Transmitters ........................... 0.3V to (VCC + 0.3V) Receivers ............................................... 18V to 18V Logic Pins .............................. 0.3V to (VCC + 0.3V) Output Voltage Transmitters ................. (VEE 0.3V) to (VDD + 0.3V) Receivers ................................ 0.3V to (VCC + 0.3V) VEE ........................................................ 10V to 0.3V VDD ....................................................... 0.3V to 10V Short-Circuit Duration Transmitter Output ..................................... Indefinite Receiver Output .......................................... Indefinite VEE .................................................................. 30 sec Operating Temperature Range LTC1546C ............................................... 0C to 70C LTC1546I ........................................... 40C to 85C Storage Temperature Range ................ 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C

ORDER PART NUMBER LTC1546CG LTC1546IG

TJMAX = 150C, JA = 90C/ W* *JA SOLDERED TO A CIRCUIT BOARD IS TYPICALLY 60C/W

Consult factory for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS
SYMBOL Supplies ICC VCC Supply Current (DCE Mode, All Digital Pins = GND or VCC) PARAMETER

The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V (Notes 2, 3)
CONDITIONS RS530, RS530-A, X.21 Modes, No Load RS530, RS530-A, X.21 Modes, Full Load V.35 Mode V.28 Mode, No Load V.28 Mode, Full Load No-Cable Mode RS530, RS530-A, X.21 Modes, Full Load V.35 Mode, Full Load V.28 Mode, Full Load V.11 or V.28 Mode, No Load V.35 Mode V.28 Mode, with Load V.28 Mode, with Load, IDD = 10mA V.28 Mode, No Load V.28 Mode, Full Load V.35 Mode RS530, RS530-A, X.21 Modes, Full Load
q q q

MIN

TYP 14 100 126 20 35 60 410 625 150

MAX

UNITS mA mA mA mA mA A mW mW mW V V V V V V V V

q q q q

130 170 75 500

PD

Internal Power Dissipation (DCE Mode)

V+

Positive Charge Pump Output Voltage

8.0 7.0 8.0

9.3 8.0 8.7 6.5 9.6 8.5 6.5 6.0

Negative Charge Pump Output Voltage

q q q

7.5 5.5 4.5

W W

LTC1546
ELECTRICAL CHARACTERISTICS
SYMBOL fOSC tr VIH VIL IIN PARAMETER Charge Pump Oscillator Frequency Charge Pump Rise Time Logic Input High Voltage Logic Input Low Voltage Logic Input Current D1, D2, D3 M0, M1, M2, DCE = GND M0, M1, M2, DCE = VCC IO = 3mA IO = 3mA 0V VO VCC M0 = M1 = M2 = VCC, 0V VO VCC RL = 1.95k (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) VOUT = GND
VA and VB 0.25V, Power Off or No-Cable Mode or Driver Disabled q q q q q q q q q q

The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V (Notes 2, 3)
CONDITIONS No-Cable Mode/Power-Off to Normal Operation
q q q q q q q q

MIN

TYP 500 2

MAX

UNITS kHz ms V

Logic Inputs and Outputs 2 0.8 120 3 50 1 5 0.5VODO 2 0.67VODO 0.2 3 0.2 150 1 2 15 15 0 15 40 40 3 3
q q q

V A A A V V mA A V V V V V V mA A ns ns ns ns ns

75 4.5 0.3

10 30 10 0.45 50

VOH VOL IOSR IOZR V.11 Driver VODO VODL VOD VOC VOC ISS IOZ t r, t f t PLH t PHL t t SKEW VTH VTH RIN t r, t f t PLH t PHL t V.35 Driver VOD VOA, VOB VOC

Output High Voltage Output Low Voltage Output Short-Circuit Current Three-State Output Current Open Circuit Differential Output Voltage Loaded Differential Output Voltage Change in Magnitude of Differential Output Voltage Common Mode Output Voltage Change in Magnitude of Common Mode Output Voltage Short-Circuit Current Output Leakage Current Rise or Fall Time Input to Output Rising Input to Output Falling Input to Output Difference, tPLH tPHL Output to Output Skew Input Threshold Voltage Input Hysteresis Input Impedance Rise or Fall Time Input to Output Rising Input to Output Falling Input to Output Difference, tPLH tPHL Differential Output Voltage Single-Ended Output Voltage Transmitter Output Offset

100 25 65 65 12

(Figures 2, 13) (Figures 2, 13) (Figures 2, 13) (Figures 2, 13) (Figures 2, 13) 7V VCM 7V 7V VCM 7V 7V VCM 7V (Figure 3) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) Open Circuit, RL = 1.95k (Figure 5) With Load, 4V VCM 4V (Figure 6) Open Circuit, RL = 1.95k (Figure 5) RL = 50 (Figure 5)

V.11 Receiver 0.2 15 100 103 15

q q q

0.2 40

V mV ns

50 50 0 4

90 90 25 1.2 0.66 1.2 0.6

ns ns ns V V V V

0.44
q q

0.55

LTC1546

ELECTRICAL CHARACTERISTICS
SYMBOL IOH IOL IOZ ROD ROC t r , tf t PLH t PHL t t SKEW VTH VTH RID RIC t r, t f tPLH tPHL t V.28 Driver VO ISS ROZ SR t PLH t PHL VTHL VTLH VTH RIN t r , tf tPLH tPHL Output Voltage Short-Circuit Current Power-Off Resistance Slew Rate Input to Output Input to Output Input Low Threshold Voltage Input High Threshold Voltage Receiver Input Hysteresis Receiver Input Impedance Rise or Fall Time Input to Output Input to Output PARAMETER Transmitter Output High Current Transmitter Output Low Current Transmitter Output Leakage Current Transmitter Differential Mode Impedance Transmitter Common Mode Impedance Rise or Fall Time Input to Output Input to Output Input to Output Difference, tPLH tPHL Output to Output Skew Differential Receiver Input Threshold Voltage Receiver Input Hysteresis Receiver Differential Mode Impedance Receiver Common Mode Impedance Rise or Fall Time Input to Output Input to Output Input to Output Difference, tPLH tPHL

The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V (Notes 2, 3)
CONDITIONS VA, VB = 0V VA, VB = 0V
VA and VB 0.25V q q q q

MIN 13 9.0 50 135

q q q

TYP 11 11 1 100 150 5 35 35 0 4

MAX 9.0 13 100 150 165 65 65 16

UNITS mA mA A ns ns ns ns ns

2V VCM 2V (Figure 7) (Figures 8, 13) (Figures 8, 13) (Figures 8, 13) (Figures 8, 13) (Figures 8, 13) 2V VCM 2V (Figure 9) 2V VCM 2V (Figure 9) 2V VCM 2V 2V VCM 2V (Figure 10) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) Open Circuit RL = 3k (Figure 11) VOUT = GND 2V < VO < 2V, Power Off or No-Cable Mode RL = 7k, CL = 0 (Figures 11, 15) RL = 3k, CL = 2500pF (Figures 11, 15) RL = 3k, CL = 2500pF (Figures 11, 15) (Figure 12) (Figure 12) (Figure 12) 15V VA 15V CL = 50pF (Figures 12, 16) CL = 50pF (Figures 12, 16) CL = 50pF (Figures 12, 16)
q q q q q q q q

15 15

V.35 Receiver 0.2 15 90 135 103 150 15 50 50 0 4 90 90 25 10 150 300 4 1.5 1.5 1.2 2 0 3 1.2 0.05 5 15 60 160 300 300 0.3 7 30 2.5 2.5 0.8 0.2 40 110 165 V mV ns ns ns ns V V mA V/s s s V V V k ns ns ns

q q q q q q q

8.5

V.28 Receiver
q q q q

Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are referenced to device ground unless otherwise specified.

Note 3: All typicals are given for VCC = 5V, C1 = C2 = CVCC = CVDD = 1F, CVEE = 3.3F and TA = 25C.

LTC1546 TYPICAL PERFOR A CE CHARACTERISTICS

V.11 Mode Supply Current vs Data Rate
180 170 SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

150 140 130 120 110 100 90 10 100 1000 DATA RATE (kBd) 10000
1546 G01

SUPPLY CURRENT (mA) 10 100 1000 DATA RATE (kBd) 10000

1546 G02

160

V.11 Mode ICC vs Temperature

115 110 105 135
ICC (mA)

ICC (mA)

100 95 90 85 40 20

ICC (mA)

40 20 60 0 TEMPERATURE (C)

PI FU CTIO S
C1 (Pin 1): Capacitor C1 Negative Terminal. Connect a 1F capacitor between C1+ and C1. (Pin 2): Capacitor C1 Positive Terminal. Connect a 1F capacitor between C1 + and C1 . VDD (Pin 3): Generated Positive Supply Voltage for V.28. Connect a 1F capacitor to ground. VCC (Pin 4): Positive Supply Voltage Input. 4.75V VCC 5.25V. Bypass with a 1F capacitor to ground. D1 (Pin 5): TTL Level Driver 1 Input. D2 (Pin 6): TTL Level Driver 2 Input. D3 (Pin 7): TTL Level Driver 3 Input. C1 + R1 (Pin 8): CMOS Level Receiver 1 Output. R2 (Pin 9): CMOS Level Receiver 2 Output. R3 (Pin 10): CMOS Level Receiver 3 Output. M0 (Pin 11): TTL Level Mode Select Input 0 with Pull-Up to VCC. See Table 1. M1 (Pin 12): TTL Level Mode Select Input 1 with Pull-Up to VCC. See Table 1. M2 (Pin 13): TTL Level Mode Select Input 2 with Pull-Up to VCC. See Table 1. DCE/DTE (Pin 14): TTL Level Mode Select Input with PullUp to VCC. See Table 1.

U W
80

V.35 Mode Supply Current vs Data Rate

150

V.28 Mode Supply Current vs Data Rate

35

34
145

33

140

32

135

31

130

30 10 20 50 DATA RATE (kBd) 100

1546 G03

V.35 Mode ICC vs Temperature

140
40

V.28 Mode ICC vs Temperature

38

36

34

130
32

100

125 40 20

40 20 60 0 TEMPERATURE (C)

80

100

30 40 20

40 20 60 0 TEMPERATURE (C)

80

100

1546 G04

1546 G05

1546 G06

LTC1546
PI FU CTIO S
R3 B (Pin 15): Receiver 3 Noninverting Input. R3 A (Pin 16): Receiver 3 Inverting Input. R2 B (Pin 17): Receiver 2 Noninverting Input. R2 A (Pin 18): Receiver 2 Inverting Input. D3/R1 B (Pin 19): Receiver 1 Noninverting Input and Driver 3 Noninverting Output. D3/R1 A (Pin 20): Receiver 1 Inverting Input and Driver 3 Inverting Output. D2 B (Pin 21): Driver 2 Noninverting Output. D2 A (Pin 22): Driver 2 Inverting Output. D1 B (Pin 23): Driver 1 Noninverting Output. D1 A (Pin 24): Driver 1 Inverting Output. GND (Pin 25): Ground. VEE (Pin 26): Negative Supply Voltage. Connect a 3.3F capacitor to GND. C2 (Pin 27): Capacitor C2 Negative Terminal. Connect a 1F capacitor between C2 + and C2 . C2 + (Pin 28): Capacitor C2 Positive Terminal. Connect a 1F capacitor between C2 + and C2 .

BLOCK DIAGRA

CHARGE PUMP C1 C1+ VDD VCC 1 2 3 4 C1 C1+ VDD VCC 50 S1 D1 5 D1 50 23 D1B 22 D2A 50 S1 D2 6 D2 50 21 D2B D3 7 D3 10k 20k 6k S3 DCE/DTE 14 10k R1 8 R1 18 R2A 20k 10k R2 9 R2 10k 20k 16 R3A 20k 10k R3 10 R3 10k 20k
1546 BD

C2+ C2 VEE GND

28 C2+ 27 C2 26 VEE 25 GND 24 D1A

S2

125

S2

125

20 D3/R1 A 51.5 S2 S1 125 51.5 19 D3/R1 B

20k

6k 51.5 S3 S2 125 51.5 17 R2B

6k 51.5 S3 S2 125 51.5 15 R3B

LTC1546

TEST CIRCUITS
D B A VOD RL
1546 F01

RL

B A

RL 100

CL 100pF CL 100pF
1546 F02

VOC

Figure 1. V.11 Driver DC Test Circuit

IB B R IA VCM = 7V

Figure 2. V.11 Driver AC Test Circuit

B A

R CL
1546 F04

A 2(VB VA) RIN = IB IA 1546 F03

Figure 3. Input Impedance Test Circuit

VOB VOB

Figure 4. V.11, V.35 Receiver AC Test Circuit

125

50 VOD 50

RL

125 VOC

50

50

125 VCM

125

50

RL
1546 F05

50

50

50

+
1546 F07

VCM = 2V

1546 F06

VOA

VOA

Figure 5. V.35 Driver Open-Circuit Test

Figure 6. V.35 Driver Test Circuit

Figure 7. V.35 Driver Common Mode Impedance Test Circuit

51.5 125 50 50 125

VTH VCM

125

50

50

+ +

VCM = 2V

51.5

1546 F08

1546 F09

1546 F10

Figure 8. V.35 Driver AC Test Circuit

Figure 9. V.35 Receiver DC Test Circuit

Figure 10. Receiver Common Mode Impedance Test Circuit

A CL
1546 F11

A RL VA

R CL
1546 F12

Figure 11. V.28 Driver Test Circuit

Figure 12. V.28 Receiver Test Circuit

LTC1546

ODE SELECTIO

Table 1
LTC1546 MODE NAME Not Used (Default V.11) RS530A RS530 X.21 V.35 RS449/V.36 V.28/RS232 No Cable Not Used (Default V.11) RS530A RS530 X.21 V.35 RS449/V.36 V.28/RS232 No Cable M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DCE/DTE 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D1 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z D2 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z D3 Z Z Z Z Z Z Z Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z R1 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z Z Z Z Z Z Z Z Z R2 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z R3 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z

SWITCHI G TI E WAVEFOR S
5V D 0V VO BA VO A VO B t SKEW t SKEW
1546 F13

1.5V t PLH 50% tr 90% 10%

1/2 VO

Figure 13. V.11, V.35 Driver Propagation Delays

VOD2 BA VOD2 VOH R VOL

0V t PLH 1.5V

Figure 14. V.11, V.35 Receiver Propagation Delays

U
f = 1MHz : t r 10ns : t f 10ns 1.5V t PHL 90% tf 50% 10%
f = 1MHz : t r 10ns : t f 10ns INPUT 0V t PHL OUTPUT 1.5V
1546 F14

LTC1546

SWITCHI G TI E WAVEFOR S
3V D 0V VO A VO tf 1.5V t PHL 3V 0V SR = 6V tf 3V 1.5V t PLH 0V 3V tr 3V SR = 6V tr
1546 F15

Figure 15. V.28 Driver Propagation Delays

VIH A VIL VOH R VOL 1.3V t PHL 1.7V t PLH 2.4V 0.8V
1546 F16

Figure 16. V.28 Receiver Propagation Delays

APPLICATIO S I FOR ATIO

Overview

The LTC1546 and LTC1544 form a complete softwareselectable DTE or DCE interface port that supports the RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21 protocols. Cable termination is provided on-chip, eliminating the need for discrete termination designs. A complete DCE-to-DTE interface operating in EIA530 mode is shown in Figure 17. The LTC1546 half of each port is used to generate and appropriately terminate the clock and data signals. The LTC1544 is used to generate the control signals along with LL (Local Loopback). Mode Selection The interface protocol is selected using the mode select pins M0, M1 and M2 (see Table 1). For example, if the port is configured as a V.35 interface, the mode selection pins should be M2 = 1, M1 = 0, M0 = 0. For the control signals, the drivers and receivers will operate in V.28 (RS232) electrical mode. For the clock and data signals, the drivers and receivers will operate in V.35

W
U

U U

electrical mode. The DCE/DTE pin will configure the port for DCE mode when high, and DTE when low. The interface protocol may be selected simply by plugging the appropriate interface cable into the connector. The mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable as shown in Figure 18. The internal pull-up current sources will ensure a binary 1 when a pin is left unconnected. The mode selection may also be accomplished by using jumpers to connect the mode pins to ground or VCC. When the cable is removed, leaving all mode pins unconnected, the LTC1546/LTC1544 will enter no-cable mode. In this mode the LTC1546/LTC1544 supply current drops to less than 500A and the LTC1546/LTC1544 driver outputs are forced into a high impedance state. At the same time, the R2 and R3 receivers of the LTC1546 are differentially terminated with 103 and the other receivers on the LTC1546 and LTC1544 are terminated with 30k to ground.

LTC1546

APPLICATIO S I FOR ATIO

DTE
SERIAL CONTROLLER TXD D1 LTC1546

SCTE

D2

D3

TXC

R1

103

RXC

R2

103

RXD

R3

103

LTC1544 RTS D1 RTS

DTR

D2

D3

DCD

R1

DSR

R2

CTS

R3

LL

D4 R4

Figure 17. Complete Multiprotocol Interface in EIA530 Mode

Cable Termination Traditional implementations used expensive relays to switch resistors or required the user to change termination modules every time a new interface standard was selected. Switching the terminations with FETs is difficult because the FETs must remain off when the signal voltage is beyond the supply voltage. Alternatively, custom cables

10

U
DCE
LTC1546 TXD 103 R3 SERIAL CONTROLLER TXD SCTE 103 R2 SCTE R1 TXC D3 TXC RXC D2 RXC RXD D1 RXD LTC1544 R3 RTS DTR R2 DTR R1 DCD D3 DCD DSR D2 DSR CTS LL R4 D4
1546 F17

U U

D1

CTS

LL

may contain termination in the cable head or route signals to various terminations on the board. The LTC1546/LTC1544 chipset solves the cable termination switching problem by automatically providing the appropriate termination and switching on-chip for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols.

LTC1546

APPLICATIO S I FOR ATIO

(DATA) M0 LTC1546 M1 M2 DCE/DTE 11 12 13 14

DCE/DTE M2 LTC1544 M1 M0 (DATA)

14 13 12 11
1546 F18

Figure 18: Single Port DCE V.35 Mode Selection in the Cable
BALANCED INTERCONNECTING CABLE

V.10 (RS423) Interface All V.10 drivers and receivers necessary for the RS449, EIA530, EIA530-A, V.36 and X.21 protocols are implemented on the LTC1544. A typical V.10 unbalanced interface is shown in Figure 19. A V.10 single-ended generator with output A and ground C is connected to a differential receiver with input A' connected to A, and ground C' connected via the signal return to ground C. Usually, no cable termination is required for V.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in Figure 20. The V.10 receiver configuration in the LTC1544 is shown in Figure 21. In V.10 mode, switch S3 inside the LTC1544 is turned off. The noninverting input is disconnected inside the LTC1544 receiver and connected to ground. The cable termination is then the 30k input impedance to ground of the LTC1544 V.10 receiver. V.11 (RS422) Interface A typical V.11 balanced interface is shown in Figure 22. A V.11 differential generator with outputs A and B and ground C is connected to a differential receiver with input A' connected to A, input B' connected to B, and ground C' connected via the signal return to ground C. The V.11
GENERATOR

U
CONNECTOR NC NC CABLE
LOAD CABLE TERMINATION A A' RECEIVER C C'
1546 F19

U U

Figure 19. Typical V.10 Interface

IZ

3.25mA

10V

3V VZ 3V 10V

1546 F20

3.25mA

Figure 20. V.10 Receiver Input Impedance

11

LTC1546

APPLICATIO S I FOR ATIO

A' A R8 6k S3 R5 20k R6 10k RECEIVER LTC1544

B' C'

B GND

R4 20k

R7 10k

1546 F21

Figure 21. V.10 Receiver Configuration

BALANCED INTERCONNECTING CABLE

GENERATOR

LOAD CABLE TERMINATION RECEIVER

A' 100 MIN

B C

B' C'

Figure 22. Typical V.11 Interface

interface has a differential termination at the receiver end that has a minimum value of 100. The termination resistor is optional in the V.11 specification, but for the high speed clock and data lines, the termination is essential to prevent reflections from corrupting the data. The receiver inputs must also be compliant with the impedance curve shown in Figure 20. In V.11 mode, all switches are off except S1 of the LTC1546s receivers which connects a 103 differential termination impedance to the cable as shown in Figure 231. The LTC1544 only handles control signals, so no termination other than its V.11 receivers 30k input impedance is necessary. V.28 (RS232) Interface A typical V.28 unbalanced interface is shown in Figure 24. A V.28 single-ended generator with output A and ground C is connected to a single-ended receiver with input A'
there is no switch S1 in receivers R2 and R3. However, for simplicity, all termination networks on the LTC1546 can be treated identically if it is assumed that an S1 switch exists and is always closed on the R2 and R3 receivers.
1Actually,

12

U
A' R1 51.5 S1 S2 R2 51.5 R8 6k S3 R5 20k R6 10k R3 124 RECEIVER LTC1546 B' C' R4 20k R7 10k GND
1546 F23

U U

Figure 23. V.11 Receiver Configuration

connected to A and ground C' connected via the signal return to ground C. In V.28 mode, S3 is closed inside the LTC1546/LTC1544 which connects a 6k (R8) impedance to ground in parallel with 20k (R5) plus 10k (R6) for a combined impedance of 5k as shown in Figure 25. Proper termination is only provided when the B input of the receivers is floating, since S1 of the LTC1546s R2 and R3 receivers remains on in V.28 mode1. The noninverting input is disconnected inside the LTC1546/LTC1544 receiver and connected to a TTL level reference voltage to give a 1.4V receiver trip point.
GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION A A' RECEIVER

1546 F22

C'

1546 F24

Figure 24. Typical V.28 Interface

A' R1 51.5 S1 S2 R2 51.5 R8 6k S3 R5 20k R6 10k RECEIVER LTC1546

R3 124

B'

R4 20k

R7 10k

C'

GND

1546 F25

Figure 25. V.28 Receiver Configuration

LTC1546

APPLICATIO S I FOR ATIO

V.35 Interface

A typical V.35 balanced interface is shown in Figure 26. A V.35 differential generator with outputs A and B and ground C is connected to a differential receiver with input A' connected to A, input B' connected to B, and ground C' connected via the signal return to ground C. The V.35 interface requires a T or delta network termination at the receiver end and the generator end. The receiver differential impedance measured at the connector must be 100 10, and the impedance between shorted terminals (A' and B') and ground (C') must be 150 15. In V.35 mode, both switches S1 and S2 inside the LTC1546 are on, connecting a T network impedance as shown in Figure 27. The 30k input impedance of the receiver is placed in parallel with the T network termination, but does not affect the overall input impedance significantly. The generator differential impedance must be 50 to 150 and the impedance between shorted terminals (A and B) and ground (C) must be 150 15.
GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION A 50 A' 50 RECEIVER

125

125

5V

4 C4 1F

VCC

GND

25

50 B C B' C'

50

1546 F26

Figure 28. Charge Pump

Figure 26. Typical V.35 Interface

A' R1 51.5 S1 S2 R2 51.5 R8 6k S3 R5 20k R6 10k R3 124 RECEIVER LTC1546

Receiver Fail-Safe All LTC1546/LTC1544 receivers feature fail-safe operation in all modes. If the receiver inputs are left floating or are shorted together by a termination resistor, the receiver output will always be forced to a logic high. DTE vs DCE Operation The DCE/DTE pin acts as an enable for Driver 3/Receiver 1 in the LTC1546, and Driver 3/Receiver 1 and Driver 4/ Receiver 4 in the LTC1544. The INVERT pin in the LTC1544 allows the Driver 4/Receiver 4 enable to be high or low true polarity.

B'

R4 20k

R7 10k

C'

GND

1546 F27

Figure 27. V.35 Receiver Configuration

U
No-Cable Mode The no-cable mode (M0 = M1 = M2 = 1) is intended for the case when the cable is disconnected from the connector. The charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 200A. Note that the LTC1546s R2 and R3 receivers continue to be terminated by a 103 differential impedance. Charge Pump The LTC1546 uses an internal capacitive charge pump to generate VDD and VEE as shown in Figure 28. A voltage doubler generates about 8V on VDD and a voltage inverter generates about 7.5V on VEE. Four 1F surface mounted tantalum or ceramic capacitors are required for C1, C2, C3 and C4. The VEE capacitor C5 should be a minimum of 3.3F. All capacitors are 16V and should be placed as close as possible to the LTC1546 to reduce EMI.
3 C3 1F 2 C1 1F 1 C2 + C2 LTC1546 C1 VEE 26 C5 3.3F 28 27 C2 1F VDD C1+
1546 F28

U U

13

LTC1546

APPLICATIO S I FOR ATIO

The LTC1546/LTC1544 can be configured for either DTE or DCE operation in one of two ways: a dedicated DTE or DCE port with a connector of appropriate gender or a port with one connector that can be configured for DTE or DCE operation by rerouting the signals to the LTC1546/LTC1544 using a dedicated DTE cable or dedicated DCE cable. A dedicated DTE port using a DB-25 male connector is shown in Figure 29. The interface mode is selected by logic outputs from the controller or from jumpers to either VCC or GND on the mode select pins. A dedicated DCE port using a DB-25 female connector is shown in Figure 30. A port with one DB-25 connector, that can be configured for either DTE or DCE operation is shown in Figure 31. The configuration requires separate cables for proper signal routing in DTE or DCE operation. For example, in DTE mode, the TXD signal is routed to Pins 2 and 14 via the LTC1546s Driver 1. In DCE mode, Driver 1 now routes the RXD signal to Pins 2 and 14. Multiprotocol Interface with RL, LL, TM and a DB-25 Connector If the RL, LL and TM signals are implemented, there are not enough drivers and receivers available in the LTC1546/ LTC1544. In Figure 32, the required control signals are handled by the LTC1545. The LTC1545 has an additional single-ended driver/receiver pair that can handle two more optional control signals such as TM and RL.

14

U
Cable-Selectable Multiprotocol Interface A cable-selectable multiprotocol DTE/DCE interface is shown in Figure 33. The select lines M0, M1 and DCE/DTE are brought out to the connector. The mode is selected by the cable by wiring M0 (connector Pin 18) and M1 (connector Pin 21) and DCE/DTE (connector Pin 25) to ground (connector Pin 7) or letting them float. If M0, M1 or DCE/ DTE is floating, internal pull-up current sources will pull the signals to VCC. The select bit M2 is hard wired to VCC. When the cable is pulled out, the interface will go into the no-cable mode. Compliance Testing The LTC1546/LTC1544 chipset has been tested by TUV Telecom Services Inc. and passed the NET1, NET2 and TBR2 requirements. Copies of the test reports are available from LTC or TUV Telecom Services. The titles of the reports are: NET1 and NET2: Test Report No. NET2/091301/99. TBR2: Test Report No. CRT2/091301/99. The address of TUV Telecom Services Inc. is: TUV Telecom Services Inc. Type Approval Division 1775 Old Highway 8, Ste 107 St. Paul, MN 55112 USA TEL: +1 (612) 639-0775 FAX: +1 (612) 639-0873

U U

LTC1546

TYPICAL APPLICATIO S
VCC 5V 3 C3 1F 1 C1 1F 2 4 C5 1F TXD 5 LTC1546 D1 T CHARGE PUMP 28 27 26 25 C4 3.3F C2 1F

24 23 22

SCTE

D2

21

7 D3 8 T 20 TXC R1 19 18 RXC 9 R2 T 17 16 RXD 10 11 12 13 14 M0 M1 M2 DCE/DTE 7 1 R3 T 15 15 12 17 9 3 16 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B SG SHIELD

C10 1F

C9 1F

VCC 1 VCC 2 VDD 3 D1

VEE GND

28 27 26 C11 1F 4 19 20 23

RTS

25 24

DTR

D2

23

D3 LTC1544 22 21 20 R2 19 18 R3 17 16 8 10 6 22 5 13 18

DCD

6 7

R1

DSR

CTS

8 10 9

LL

R4 D4 M0 M1 M2 DCE/DTE INVERT

M0 M1 M2

11 12 13 14

15

NC

Figure 29. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector

2 14 24 11

TXD A (103) TXD B SCTE A (113) SCTE B

DB-25 MALE CONNECTOR

RTS A (105) RTS B DTR A (108) DTR B

DCD A (109) DCD B DSR A (107) DSR B CTS A (106) CTS B LL A (141)

1546 F29

15

LTC1546

TYPICAL APPLICATIO S
VCC 5V 3 C3 1F 1 C1 1F 2 4 C5 1F RXD 5 LTC1546 D1 T CHARGE PUMP 28 27 26 25 C4 3.3F C2 1F

24 23 22

RXC

D2

21

7 D3 8 T 20 TXC R1 19 18 SCTE 9 R2 T 17 16 TXD 10 11 12 13 NC 14 M0 M1 M2 DCE/DTE 7 1 R3 T 15 15 12 24 11 2 14 TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B SGND (102) SHIELD (101)

C10 1F

C9 1F

VCC 1 VCC 2 VDD 3 D1

VEE GND

28 27 26 C11 1F 5 13 6 22

CTS

25 24

DSR

D2

23

D3 LTC1544 22 21 20 R2 19 18 R3 17 16 8 10 20 23 4 19 18

DCD

6 7

R1

DTR

RTS

8 10 9

LL

R4 D4 M0 M1 M2 DCE/DTE INVERT

M0 M1 M2 NC

11 12 13 14

15

NC

Figure 30. Controller-Selectable DCE Port with DB-25 Connector

16

3 16 17 9

RXD A (104) RXD B RXC A (115) RXC B

DB-25 FEMALE CONNECTOR

CTS A (106) CTS B DSR A (107) DSR B

DCD A (109) DCD B DTR A (108) DTR B RTS A (105) RTS B LL A (141)

1546 F30

LTC1546

TYPICAL APPLICATIO S
VCC 5V 3 C3 1F 1 C1 1F 2 4 C5 1F DTE_TXD/DCE_RXD 5 LTC1546 D1 T CHARGE PUMP 28 27 26 25 C4 3.3F DTE TXD A TXD B SCTE A SCTE B DCE RXD A RXD B RXC A RXC B C2 1F

24 23 22

DTE_SCTE/DCE_RXC

6 7

D2

21

D3 8

T 20 15 12 17 9 3 16 7 1 TXC A TXC B RXC A RXC B RXD A RXD B SG SHIELD TXC A TXC B SCTE A SCTE B TXD A TXD B

DTE_TXC/DCE_TXC

R1

19 18

DTE_RXC/DCE_SCTE

R2

17 16

DTE_RXD/DCE_TXD

10 11 12 13 14 M0 M1 M2

R3

15

DCE/DTE

C10 1F

C9 1F

VCC 1 VCC 2 VDD 3 D1

VEE GND

28 27 26 C11 1F 4 19 20 23

DTE_RTS/DCE_CTS

25 24

DTE_DTR/DCE_DSR

D2

23

D3 LTC1544 22 21 20 R2 19 18 R3 17 16 8 10 6 22 5 13 18

DTE_DCD/DCE_DCD

6 7

R1

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

8 10 9

DTE_LL/DCE_LL

R4 D4 M0 M1 M2 DCE/DTE INVERT

M0 M1 M2 DCE/DTE

11 12 13 14

15

NC

Figure 31. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

2 14 24 11

DB-25 CONNECTOR

RTS A RTS B DTR A DTR B

CTS A CTS B DSR A DSR B

DCD A DCD B DSR A DSR B CTS A CTS B LL A

DCD A DCD B DTR A DTR B RTS A RTS B LL A

1546 F31

17

LTC1546

TYPICAL APPLICATIO S
VCC 5V 3 C3 1F 1 C1 1F 2 4 C5 1F DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC 5 LTC1546 D1 T CHARGE PUMP 28 27 26 25 24 23 22 D2 7 D3 8 T 20 DTE_TXC/DCE_TXC R1 19 18 DTE_RXC/DCE_SCTE 9 R2 T 17 16 DTE_RXD/DCE_TXD 10 11 12 M0 R3 T 15 15 12 17 9 3 16 7 1 TXC A TXC B RXC A RXC B RXD A RXD B SG SHIELD TXC A TXC B SCTE A SCTE B TXD A TXD B T 21 C4 3.3F DTE TXD A TXD B SCTE A SCTE B DCE RXD A RXD B RXC A RXC B C2 1F

M1 13 M2 14 DCE/DTE

C10 1F

VCC 5V

C9 1F

1,19 VCC 2,20 VDD 3 D1

VEE GND

36 35 34 C11 1F 4 19 20 23

DTE_RTS/DCE_CTS

33 32

DTE_DTR/DCE_DSR

D2

31

D3 LTC1545 30 29 28 R2 27 26 R3 D4 R4 R5 D5 M0 M1 M2 DCE/DTE
1546 F32

DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR

6 7 8 9 10 17 18 11 12 13 14

R1

DTE_CTS/DCE_RTS DTE_LL/DCE_RI DTE_RI/DCE_LL DTE_TM/DCE_RL DTE_RL/DCE_TM M0 M1 M2 DCE/DTE

25 24 23 22 21 D4ENB R4EN 15

16

Figure 32. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and DB-25 Connector

18

2 14 24 11

DB-25 CONNECTOR

RTS A RTS B DTR A DTR B

CTS A CTS B DSR A DSR B

8 10 6 22 5 13 18 * 25 21

DCD A DCD B DSR A DSR B CTS A CTS B LL RI TM RL

DCD A DCD B DTR A DTR B RTS A RTS B RI LL RL TM

*OPTIONAL NC

LTC1546

TYPICAL APPLICATIO S
VCC 5V 3 C3 1F 1 C1 1F C5 1F DTE_TXD/DCE_RXD 5 2 4 LTC1546 D1 T CHARGE PUMP 28 27 26 25 C2 1F C4 3.3F DTE TXD A TXD B SCTE A SCTE B DCE RXD A RXD B RXC A RXC B

24 23 22

DTE_SCTE/DCE_RXC

6 7

D2

21

D3 8

T 20 15 12 17 9 3 16 7 1 TXC A TXC B RXC A RXC B RXD A RXD B SG SHIELD DB-25 CONNECTOR TXC A TXC B SCTE A SCTE B TXD A TXD B

DTE_TXC/DCE_TXC

R1

19 18

DTE_RXC/DCE_SCTE

R2

17 16

DTE_RXD/DCE_TXD

10 11 12 NC 13 14 M0 M1 M2

R3

15

DCE/DTE

C10 1F

C9 1F

VCC 1 VCC 2 VDD 3 D1 VEE GND 28 27 26 C11 1F

DTE_RTS/DCE_CTS

25 24

DTE_DTR/DCE_DSR

D2

23

D3 LTC1544 22 21 20 R2 19 18 R3 17 16 CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 RS449, V.36 NC PIN 7 RS232 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION 15 NC MODE DTE DCE PIN 25 PIN 7 NC
1546 F33

DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR

6 7

R1

DTE_CTS/DCE_RTS

10 9 11 12 NC 13 14 M0 M1 M2

R4 D4

DCE/DTE INVERT

Figure 33. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

2 14 24 11

25 DCE/DTE 21 M1 18 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B

CTS A CTS B DSR A DSR B

8 10 6 22 5 13

DCD A DCD B DSR A DSR B CTS A CTS B

DCD A DCD B DTR A DTR B RTS A RTS B

19

LTC1546

PACKAGE DESCRIPTIO

5.20 5.38** (0.205 0.212)

0.13 0.22 (0.005 0.009)

0.55 0.95 (0.022 0.037)

NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

RELATED PARTS
PART NUMBER
LTC1321 LTC1334 LTC1343 LTC1344A LTC1345 LTC1346A LTC1543 LTC1544 LTC1545

DESCRIPTION
Dual RS232/RS485 Transceiver Single 5V RS232/RS485 Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Cable Terminator Single Supply V.35 Transceiver Dual Supply V.35 Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver

20

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com

Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)

10.07 10.33* (0.397 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15

7.65 7.90 (0.301 0.311)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.73 1.99 (0.068 0.078)

0 8

0.65 (0.0256) BSC

0.25 0.38 (0.010 0.015)

0.05 0.21 (0.002 0.008)

G28 SSOP 1098

COMMENTS
Two RS232 Driver/Receiver Pairs or Two RS485 Driver/Receiver Pairs Two RS232 Driver/Receiver or Four RS232 Driver/Receiver Pairs 4-Driver/4-Receiver for Data and Clock Signals Perfect for Terminating the LTC1543 (Not Needed with LTC1546) 3-Driver/3-Receiver for Data and Clock Signals 3-Driver/3-Receiver for Data and Clock Signals Terminated with LTC1344A for Data and Clock Signals, Companion to LTC1544 or LTC1545 for Control Signals Companion to LTC1546 or LTC1543 for Control Signals Including LL 5-Driver/5-Receiver Companion to LTC1546 or LTC1543 for Control Signals Including LL, TM and RL

sn1546 1546fs LT/LCG 1200 4K PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1999