Q

1
( )
=
A g
m
R
1
=
1
1
R
1
C
1

=
0
1
R
1
R
2
C
1
C
2

=
Ideal Transfer Function
V
o
V
i
1 R
2
R
1
+ ( ) C
2
s + R
1
R
2
C
1
C
2
s
2
+

1
]
=
1
s

,
2
s

0
1
Q
+ 1 +
=
Units/Constants/Model File
Constants
Units
useful functions and identities
Fig. 3: Differential Voltage-Driven Sallen-Key Filter
Fig. 2: Single-Ended Sallen-Key Filter w/ Emitter Follower
C
2
/2
R
1
C
1
R
2
R
1
C
1
R
2
R
1
C
1
C
2
R
2
G(V

)
I
V

V
x
V
y
V
o
v
o
v
x
R
1
C
1
C
2
R
2
R
1
C
1
C
2
R
2
C

G(V

)
I
V

s*I
C
*
F
Note: This routine is a reduction of a more complex version. This reduction is still taking place, so please
excuse the current mess.
Fig. 1: Single-ended Sallen-Key filter
v
o
v
i
v
x
R
1
C
1
C
2
R
2
G
V
nOA
Sallen-Key Low Pass Filter
Design Routine
1
2
C
2
R
2 _ 1 1
V
x
V
o
G
V
n
+

R
2
V
o
G
V
n
+

,
C
2
s = KCL @ Node Vo/G
V
i
V
x

R
1
V
x
V
o
G
V
n
+

1
1
]
R
2
V
x
V
o
( ) C
1
s + = KCL @ Node Vx
First Use KCL to solve for the transfer functions for the system
Derivation
0 2 4 6 8 10 12 14 16 18 20
0
20
40
NoiseBW Q
val
i
( )
Q
val
i

Q
val
i
Q
val
i
i 1
num 1
20 0.1 ( ) 0.1 + :
Index Vector for Plotting i 1 num .. :
Number of Points for Plotting num 100 :
NoiseBW Q ( )
0
10000
f H
LPF
1 2 f 1 , 2 , Q , ( ) ( )
2

d :
Frequency Response - General LPF Representation (no zeros): H
LPF
s G ,
0
, Q , ( )
G
s

,
2
s

0
1
Q
+ 1 +
:
Equivalent Noise Bandwidth
Attenuation of the Notch A
notch
1
A
:
Frequency of the Notch f
notch

0
A =
Maximum Attenuation with a fast transistor A
max
1
1
Q

1
g
m
R
1
+

,
=
A
1
s ( )
1
s
1

0
2

,
+

1
1
1
]
s
A
1

1 +

1
1
1
]
1
s
Q
0

,
s
A
1

Den s ( ) +

1
1
]
=
Den 1
1

0
Q
s +
s

,
2
+ = g
m
I
C
V
T
= V
T
25.899mV V
T
k Temp
q
:
Q
C
2

0
R
1
R
2
+ ( )
=
2
P
jammer
30dBm :
Power of the Jammer
P
signal
80dBm : Power of the Desired Signal
f
jammer
900kHz : Frequency of Jammer
f
jammer2
1700kHz : Frequency of Second Jammer (for Two-Tone
Analysis)
Optional Inputs
V
DSsat
0.3V : V
DSsat
of Op-Amp Input
R
maxdes
400k : Maximum Desired Resistor
Calculations

0
2 f
0
:
Effective Noise Bandwidth
NoiseBW Q ( ) 1.111
V
inswing
V
DD
2 V
DSsat
: V
inswing
2.1V
V
outswing
V
inswing
H
LPF
j 2 f
jammer
G ,
0
, Q , ( ) : V
outswing
0.885V
V
rms
V
inswing
2 2
: V
rms
0.742V
V
o
R
1
C
1
R
2
C
2
s
2

C
2
C
1
R
2
R
1
1 +

,
1 +

1
1
]
R
1
C
1
s + 1 +

1
1
]

R
1
C
1
R
2
C
2
s
2

C
2
C
1
R
2
R
1
1 +

,
1 G +

1
1
]
R
1
C
1
s + 1 +
G V
n

G V
i

R
1
C
1
R
2
C
2
s
2

C
2
C
1
R
2
R
1
1 +

,
1 G +

1
1
]
R
1
C
1
s + 1 +
+
... =

0
1
R
1
C
1
R
2
C
2

=
Q

0
1
R
1
C
1

1
R
2
C
1

+
1 G
R
2
C
2

+
= Q
1
C
2
C
1
R
2
R
1
1 +

,
1 G +

1
1
]
R
1
C
1

0

=
V
neq
2
4 k Temp R
1
R
2
+ ( ) V
n
2
+ =
V
oeq
2
V
neq
2
H
LPF
s G ,
0
, Q , ( ) ( )
2
=
What is important is the integrated noise.
V
oeq
2
V
neq
2
f
0
NoiseBW G
2
=
V
neq
2
V
oeq
2
f
0
NoiseBW G
2

=
Inputs
f
0
1.227MHz
2
: f
0
613.5kHz Center Frequency
Q 0.7071 : Desired Q
SNR 80dB : Minimum Signal to Noise Ratio
V
DD
2.7V : Supply Voltage
Temp 300K : Temperature Range
G 1 : Gain
3

1r
2
433.814kHz

0r
1
R
1r
R
2r
C
1r
C
2r

:

0r
2
613.5kHz
Q
r

0
1
R
1r
C
1r

1
R
2r
C
1r

+
1 G
R
2r
C
2r

+
: Q
r
0.707
The following current should be sized much higher to reduce the distortion of the amplifier.
Voutswing_t V
outswing
2 f
jammer
:
Crude Estimate of Load Capacitance
C
Leff
C
1r
: C
Leff
3.669pF Estimated Load Capacitance
I
slewr
C
Leff
Voutswing_t : I
slewr
0.018mA Required Current to Slew Output
I
noiser
4 k Temp
V
T
2

1
1
]
V
n
2
: I
noiser
0.106A
I
r
if I
slewr
I
noiser
> I
slewr
, I
noiser
, ( ) : I
r
0.018mA
I
r
if I
r
I
min
< I
min
, I
r
, ( ) :
g
mr
I
r
V
T
: g
mr
0.709
mA
V

A
r
g
mr
R
1r
: A
r
70.887
V
neq
V
rms
10
SNR
20
1
f
0
NoiseBW Q ( )
: V
neq
89.943
nV
Hz

V
oeq
V
neq
2
f
0
NoiseBW Q ( ) G
2
: V
oeq
74.246V
V
n
V
neq
4
: V
n
44.971
nV
Hz

Solving Assumption Number 1: R

1
=R
2
G
thresh
1
8 Q
2

1 + : G
thresh
1.25 G should be less than or equal to one
valid
r
G
1
8 Q
2

1 + :
valid
r
1
R
V
neq
2
V
n
2

2 4 k Temp
: R 182.794k
R if R 100k > 100k , R , ( ) : R 100k
R
1r
R :
R
2r
R :
C
2r
1 1 8 Q
2
G 1 ( )

1
]
+
4 Q
0
R
: C
2r
1.834pF
Problem with the R
1
=R
2
architecture. C1 blows up for large Q's.
C
1r
1

0
2
R
2
C
2r

: C
1r
3.669pF

1r
1
R
1r
C
1r

:
4
Solving Assumption Number 2: C
1
=C
2
G
thresh
1.25 G should be greater than 2
G
thresh
1
1
Q
+
1
2 Q
2

:
Problem with C1=C2 architecture: Cannot be used with an emitter follower unless Q<1/2.
valid
c
G 1
1
Q
+
1
2 Q
2

: valid
c
0
All G's can be used with Q
5
8
<
V
neq
V
n

4 k T
Q 1 G ( ) Q R
1
+

1
1
]
2
R
1
R
1
V
neq
2
V
n
2

4 k Temp

,
+ 0 =
R
1c
1
2
Q
2
1 G ( )
1 G ( )
2
Q
2
1 +

1
1
1
1
]
V
neq
2
V
n
2

4 k Temp
1 1
1
1
2 Q
Q 1 G ( )

1
1
]
2

1
1
1
1
]
:
R
1c
182.794 182.79i k
R
2c
V
neq
2
V
n
2

4 k Temp
R
1c

,
: R
2c
182.794 182.79i + k
C
1
R
1c
R
2c
+ 1 G ( ) R
1c
+

1
]
Q
0

:
C 1.004pF
C
1c
C :
C
2c
C :

0c
1
R
1c
R
2c
C
1c
C
2c

:

0c
2
613.5kHz
Q
c

0
1
R
1c
C
1c

1
R
2c
C
1c

+
1 G
R
2c
C
2c

+
: Q
c
0.707
C
Leff
C
1c
: C
Leff
1.004pF
A
r
g
mr
R
1r
: A
r
70.887
A
maxr
1
1
Q

1r
g
mr
R
1r
+

,
: 20 log A
maxr
( ) 37.253 dB Maximum Attenuation with a fast transistor
f
notchr

0
2
A
r
: f
notchr
5.165MHz Frequency of the Notch
A
notchr
1
A
r
: 20 log A
notchr
( ) 37.011 dB
area
Rr
W
min
R
1r
R
2r
+ ( ) W
min

R
sq
:
area
Rr
10m
cost
Rr
cost_mm2 area
Rr
: cost
Rr
1.2 10
3
cent
area
Cr
1
C_area
C
1r
C
2r
+ ( ) : area
Cr
88.666m
cost
Cr
cost_mm2 area
Cr
: cost
Cr
0.094cent
area
r
area
Cr
area
Rr
+ : area
r
89.228m
cost
powerr
cost
power
I
r
V
DD
: cost
powerr
0.14cent
cost
r
cost
Cr
cost
Rr
+ cost
powerr
+ : cost
r
0.236cent
5
cost
Rc
cost_mm2 area
Rc
: cost
Rc
2.194 10
3
cent
area
Cc
1
C_area
C
1c
C
2c
+ ( ) : area
Cc
53.547m
cost
Cc
cost_mm2 area
Cc
: cost
Cc
0.034cent
area
c
area
Cc
area
Rc
+ : area
c
55.227m
cost
powerc
cost
power
I
c
V
DD
: cost
powerc
0.076cent
cost
c
cost
Cc
cost
Rc
+ cost
powerc
+ : cost
c
0.113cent
Solving Assumption Number 3: R
1
C
1
=R
2
C
2
=.
G
thresh
2
1
Q
: G
thresh
0.586
valid
t
G G
thresh
> : valid
t
1
R
2t
V
neq
2
V
n
2

4 k Temp
1
Q
G + 1

: R
2t
258.507k
R
1t
1
Q
G + 2

,
R
2t
: R
1t
107.081k
C
1t
1
R
1t

0

: C
1t
2.423pF
C
2t
1
R
2t

0

: C
2t
1.004pF

0t
1
R
1t
R
2t
C
1t
C
2t

:

0t
2
613.5kHz
C
Leff
C
1c
: C
Leff
1.004pF
I
slewc
C
Leff
Voutswing_t : I
slewc
5.022A Required Current to Slew Output
I
noisec
4 k Temp
V
T
2

1
1
]
V
n
2
: I
noisec
0.106A
I
c
if I
slewc
I
noisec
> I
slewc
, I
noisec
, ( ) : I
c
5.022A
I
c
if I
c
I
min
< I
min
, I
c
, ( ) :

1c
1
R
1c
C
1c

:

1c
2
433.814 433.806i + kHz
g
mc
I
c
V
T
: g
mc
0.386
mA
V

A
c
g
mc
R
1c
: A
c
70.58 70.578i
A
maxc
1
1
Q

1c
g
mc
R
1c
+

,
: 20 log A
maxc
( ) 40.106 dB Maximum Attenuation
with a fast transistor
f
notchc

0
2
A
c
: f
notchc
5.663 2.346i MHz Frequency of the Notch
A
notchc
1
A
c
: 20 log A
notchc
( ) 39.984 6.822i + dB Depth of Notch
area
Rc
W
min
R
1c
R
2c
+ ( ) W
min

R
sq
:
area
Rc
13.52m
6
valid
m
Q
0
C
1m

V
neq
2
V
n
2

4 k Temp 4

,
< : valid
m
1
R
2m
V
neq
2
V
n
2

4 k Temp 2
1 1
4 k Temp ( ) 4
V
neq
2
V
n
2

_
,
Q

0
C
1m

1
1
1
]
: R
2m
222.683k
R
1m
V
neq
2
V
n
2

4 k Temp
R
2m
: R
1m
142.905k
C
2m
1

0
2
R
1m
R
2m
C
1m

:
C
2m
1.004pF

0m
1
R
1m
R
2m
C
1m
C
2m

:

0m
2
613.5kHz
Q
m

0
1
R
1m
C
1m

1
R
2m
C
1m

+
1 G
R
2m
C
2m

+
: Q
m
0.707
Q
maxm

0
C
1m

V
neq
2
V
n
2

4 k Temp 4

,
: Q
maxm
0.742
C
Leff
C
1m
: C
Leff
2.107pF Estimated Load Capacitance
I
slewm
C
Leff
Voutswing_t : I
slewm
10.546A Required Current
to Slew Output
4 k Temp
V
T
2

1
1
]
R
1t
R
2t
C
1t
C
2t

2
Q
t

0
1
R
1t
C
1t

1
R
2t
C
1t

+
1 G
R
2t
C
2t

+
: Q
t
0.707
Solving Assumption #4: C
1
=C
max
or C
min
.
First solve for maximum Capacitance by setting the cost of the internal capacitor to that of an external capacitor.
This upper limit is set when extra pins are available to put a capacitor off-chip.
C
max
C_area
cost_mm2
cost
Cext
: C
max
183.96pF
Area
Cmax
C
max
C_area
: Area
Cmax
512.64m
If the pins are not available to put the capacitor off-chip, the maximum capacitor size must be re-evaluated using
marketing estimates for the amount the chip can sell for, and yields given the larger chip size, and package limits on
the die size.
C
max
100pF : Maximum Desired On-Chip Capacitance
Area
Cmax
C
max
C_area
: Area
Cmax
512.64m
Given the center frequency, maximum capacitor size, and desired SNDR the needed capacitance is given by the
following equation to prevent a complex resistor sizing.
C
maxm
Q

0
4 k Temp 4
V
neq
2
V
n
2

:
C
maxm
2.007pF
Area
Cmaxm
C
maxm
C_area
: Area
Cmaxm
53.546m
Now Solve for Variables
C
1m
C
maxm
1.05 : C
1m
2.107pF
7
cost
Cm
cost_mm2 area
Cm
: cost
Cm
0.053cent
area
m
area
Cm
area
Rm
+ : area
m
68.022m
cost
powerm
cost
power
I
m
V
DD
: cost
powerm
0.081cent
cost
m
cost
Cm
cost
Rm
+ cost
powerm
+ : cost
m
0.136cent
Solving Assumption #4.5: Other Solution to Quadratic of 4.
C
1m2
C
maxm
1.05 : C
1m2
2.107pF
valid
m2
Q
0
C
1m2

V
neq
2
V
n
2

4 k Temp 4

,
< : valid
m2
1
R
2m2
V
neq
2
V
n
2

4 k Temp 2
1 1
4 k Temp ( ) 4
V
neq
2
V
n
2

_
,
Q

0
C
1m2

1
1
1
]
: R
2m2
142.905k
R
1m2
V
neq
2
V
n
2

4 k Temp
R
2m2
: R
1m2
222.683k
C
2m2
1

0
2
R
1m2
R
2m2
C
1m2

:
C
2m2
1.004pF

0m2
1
R
1m2
R
2m2
C
1m2
C
2m2

:

0m2
2
613.5kHz
Q
m2

0
1
R
1m2
C
1m2

1
R
2m2
C
1m2

+
1 G
R
2m2
C
2m2

+
:
Q
m2
0.707
Q
maxm2

0
C
1m2

V
neq
2
V
n
2

: Q
maxm2
0.742
I
noisem
2
, ]
V
n
2
: I
noisem
0.106A
I
m
if I
slewm
I
noisem
> I
slewm
, I
noisem
, ( ) :
I
m
if I
m
I
min
< I
min
, I
m
, ( ) : I
m
10.546A

1m
1
R
1m
C
1m

:

1m
2
528.48kHz
g
mm
I
m
V
T
: g
mm
0.407
mA
V

A
m
g
mm
R
1m
: A
m
58.189
A
maxm
1
1
Q

1m
g
mm
R
1m
+

,
: 20 log A
maxm
( ) 35.538 dB Maximum Attenuation
with a fast transistor
f
notchm

0
2
A
m
: f
notchm
4.68MHz Frequency of the Notch
A
notchm
1
A
m
: 20 log A
notchm
( ) 35.297 dB Depth of Notch
area
Rm
W
min
R
1m
R
2m
+ ( ) W
min

R
sq
:
area
Rm
13.52m
cost
Rm
cost_mm2 area
Rm
: cost
Rm
2.194 10
3
cent
area
Cm
1
C_area
C
1m
C
2m
+ ( ) : area
Cm
66.665m
8
Depth of Notch
area
Rm2
W
min
R
1m2
R
2m2
+ ( ) W
min

R
sq
:
area
Rm2
13.52m
cost
Rm2
cost_mm2 area
Rm2
: cost
Rm2
2.194 10
3
cent
area
Cm2
1
C_area
C
1m2
C
2m2
+ ( ) : area
Cm2
66.665m
cost
Cm2
cost_mm2 area
Cm2
: cost
Cm2
0.053cent
area
m2
area
Cm2
area
Rm2
+ : area
m2
68.022m
cost
powerm2
cost
power
I
m2
V
DD
: cost
powerm2
0.081cent
cost
m2
cost
Cm2
cost
Rm2
+ cost
powerm2
+ : cost
m2
0.136cent
Solving Assumption #5: R
1
=R
max
.
R
max
cost
Rext
cost_mm2
R
sq
W
min
2
: R
max
442.267M
R
max
if R
max
R
maxdes
< R
max
, R
maxdes
, ( ) : R
max
400k
Area
Rmax
W
min
R
max
W
min

R
sq
: Area
Rmax
14.142m
R
1n
R
max
:
R
1n
400k
R
2n
V
neq
2
V
n
2

4 k Temp
R
1n
:
R
2n
34.413 k
C
1n
1
R
1n
1
R
2n
+

,
Q

0
G 1 = if

0 1
R
1n _ 2
1
:
Q
maxm2

0
C
1m2

4 k Temp 4

,
: Q
maxm2
0.742
C
Leff
C
1m2
: C
Leff
2.107pF Estimated Load Capacitance
I
slewm2
C
Leff
Voutswing_t : I
slewm2
10.546A Required Current
to Slew Output
I
noisem2
4 k Temp
V
T
2

1
1
]
V
n
2
: I
noisem2
0.106A
I
m2
if I
slewm2
I
noisem2
> I
slewm2
, I
noisem2
, ( ) :
I
m2
if I
m2
I
min
< I
min
, I
m2
, ( ) : I
m2
10.546A

1m2
1
R
1m2
C
1m2

:

1m2
2
339.148kHz
g
mm2
I
m2
V
T
: g
mm2
0.407
mA
V

A
m2
g
mm2
R
1m2
: A
m2
90.673
A
maxm2
1
1
Q

1m2
g
mm2
R
1m2
+

,
: 20 log A
maxm2
( ) 39.391 dB Maximum Attenuation
with a fast transistor
f
notchm2

0
2
2 A
m
: f
notchm2
9.36MHz Frequency of the Notch
A
notchm2
1
A
m2
: 20 log A
notchm2
( ) 39.15 dB
9
g
mn
0.386
mA
V

A
n
g
mn
R
1n
: A
n
154.447
A
maxn
1
1
Q

1n
g
mn
R
1n
+

,
: 20 log A
maxn
( ) 43.157 dB Maximum Attenuation
with a fast transistor
f
notchn

0
2
A
n
: f
notchn
7.624MHz Frequency of the Notch
A
notchn
1
A
n
: 20 log A
notchn
( ) 43.776 dB Depth of Notch
area
Rn
W
min
R
1n
R
2n
+ ( ) W
min

R
sq
:
area
Rn
13.52m
cost
Rn
cost_mm2 area
Rn
: cost
Rn
2.194 10
3
cent
area
Cn
1
C_area
C
1n
C
2n
+ ( ) : area
Cn
74.339i m
cost
Cn
cost_mm2 area
Cn
: cost
Cn
0.066 cent
area
n
area
Cn
area
Rn
+ : area
n
73.099i m
cost
powern
cost
power
I
n
V
DD
: cost
powern
0.076cent

0
2 Q
1
1 G ( )
0
2
R
1n

1
]
1 1 1
R
1n
R
2n
+

,
4 1 G ( ) Q
2

1
1
]
G 1 if
C
1n
4.872 pF
G
thresh
1
1
4 Q
2
1
R
1n
R
2n
+

: G
thresh
1.047
G must be greater than
0.773 for C1 to be real
valid
n
G G
thresh
> ( ) R
2n
0 > ( ) : valid
n
0
C
2n
1

0
2
R
1n
R
2n
C
1n

: C
2n
1.004pF

0n
1
R
1n
R
2n
C
1n
C
2n

:

0n
2
613.5kHz
Q
n

0
1
R
1n
C
1n

1
R
2n
C
1n

+
1 G
R
2n
C
2n

+
: Q
n
0.707
C
Leff
C
1n
: C
Leff
4.872 pF Estimated Load Capacitance
I
slewn
C
Leff
Voutswing_t : I
slewn
24.38 A Required Current
to Slew Output
I
noisen
4 k Temp
V
T
2

1
1
]
V
n
2
: I
noisen
0.106A
I
n
if I
slewn
I
noisen
> I
slewn
, I
noisen
, ( ) :
I
n
if I
n
I
min
< I
min
, I
n
, ( ) : I
n
10A

1n
1
R
1n
C
1n

:

1n
2
81.67 kHz
g
mn
I
n
V
T
:
10
Required Current to Slew Output
20 log A
maxc
( ) 40.106 dB Maximum Attenuation with a fast transistor
f
notchc
5.663 2.346i MHz Frequency of the Notch
20 log A
notchc
( ) 39.984 6.822i + dB Depth of Notch
cost
c
0.113cent Cost of c method
Implementation, where R
1
=R
2
=R
valid
r
1 Are these Coefficients Valid? 0=no, 1=yes
R
1r
100k Resistor 1 Value
R
2r
100k Resistor 2 Value
C
1r
3.669pF Capacitor 1 Value
C
2r
1.834pF Capacitor 2 Value
I
r
18.359A Required Current to Slew Output
20 log A
maxr
( ) 37.253 dB Maximum Attenuation with a fast transistor
f
notchr
5.165MHz Frequency of the Notch
20 log A
notchr
( ) 37.011 dB Depth of Notch
cost
r
0.236cent Cost of r method
cost
n
cost
Cn
cost
Rn
+ cost
powern
+ : cost
n
0.012cent
Solving Assumption #6: Minimize Area
This doesn't work for G<1. It spits out unrealistically sized values for G's close to one. Lets set a threshold of a G of
about 1.3. In general the area is dominated by the capacitor
R
1g
0.6M : Guess at R1
valid
a
G 1.3 > : valid
a
0
R
1a
root
1
R
1g
1
R
1g
V
neq
2
V
n
2

4 k Temp

,
1
W
min
2
C_area
R
sq
R
1g

1 G ( ) R
1g
2

W
min
2
C_area
R
sq

0
2
+
Q

0
R
1g
,

1
1
1
1
1
]
:
R
1a
2.627 10
8
k
R
2a
R
1a
V
neq
2
V
n
2

4 k Temp
:
R
2a
2.627 10
8
k
C
1a
W
min
2
C_area
R
sq
R
1a
: C
1a
9.194 10
4
pF
C
2a
1
R
1a
2
W
min
2
C_area
R
sq

0
2

,
R
2a

: C
2a
0pF
Outputs
Implementation, where C
1
=C
2
=C
valid
c
0 Are these Coefficients Valid? 0=no, 1=yes
R
1c
182.794 182.79i k Resistor 1 Value
R
2c
182.794 182.79i + k Resistor 2 Value
C
1c
1.004pF Capacitor Value
C
2c
1.004pF Capacitor Value
I
c
10A
11
Required Current to Slew Output
20 log A
maxm2
( ) 39.391 dB Maximum Attenuation with a fast transistor
f
notchm2
9.36MHz Frequency of the Notch
20 log A
notchm2
( ) 39.15 dB Depth of Notch
cost
m2
0.136cent Cost of m2 method
Implementation, where R
1
=R
max
.
valid
n
0 Are these Coefficients Valid? 0=no, 1=yes
R
1n
400k Resistor 1 Value
R
2n
34.413 k Resistor 2 Value
R
1
R
1r
valid
r
if
R
1c
valid
c
if
:
architecture 3
architecture 1 valid
r
if
2 valid
c
if
3 valid
m
if
error "none are valid" ( ) 1 valid
m
( ) 1 valid
c
( ) 1 valid
r
( ) if
:
Cost of n method cost
n
0.012cent
Depth of Notch 20 log A
notchn
( ) 43.776 dB
Frequency of the Notch f
notchn
7.624MHz
Maximum Attenuation with a fast transistor 20 log A
maxn
( ) 43.157 dB
Required Current to Slew Output I
n
10A
Capacitor 2 Value C
2n
1.004pF
Capacitor 1 Value C
1n
4.872 pF
f
notchm
4.68MHz
Maximum Attenuation with a fast transistor 20 log A
maxm
( ) 35.538 dB
Required Current to Slew Output I
m
10.546A
Capacitor 2 Value C
2m
1.004pF
Capacitor 1 Value C
1m
2.107pF
Resistor 2 Value R
2m
222.683k
Resistor 1 Value R
1m
142.905k
Are these Coefficients Valid? 0=no, 1=yes valid
m
1
Implementation, where C
1
=C
max
.
r
I
m2
10.546A
Capacitor 2 Value C
2m2
1.004pF
Capacitor 1 Value C
1m2
2.107pF
Resistor 2 Value R
2m2
142.905k
Resistor 1 Value R
1m2
222.683k
Are these Coefficients Valid? 0=no, 1=yes valid
m2
1
2
nd
Implementation, where C
1
=C
max
.
Cost of m method cost
m
0.136cent
Depth of Notch 20 log A
notchm
( ) 35.297 dB
Frequency of the Notch
12
f
20 log A
1
A
1
, j 2 f
notchguess
, ( ) ( ) dB
1
A
jammer
dB A
jammer
A
jammer
20 log A
1
A
1
, j 2 f
jammer
, ( ) ( ) :
1
A
notch
dB A
notch
A
notch
20 log A
1
A
1
, j 2 f
notch
, ( ) ( ) : f
notch
f
notchguess
4.68MHz f
notchguess
A

0
2
:
Useful bandwidth
f
notch
MHz f
notch
f
notch

0
2
1
( )
1 1 4

,
2
A + +

1
1
1
]

0
2
:

1
A 58.189 A g
m
R
1
:
g
m
0.407
mA
V
g
m
I
V
T
:
20 log A
max
( ) 35.538 dB
A
max
A
maxr
valid
r
if
A
maxc
valid
c
if
A
maxm
valid
m
if
error "none are valid" ( ) 1 valid
m
( ) 1 valid
c
( ) 1 valid
r
( ) if
:
I 0.011mA
I I
r
valid
r
if
I
c
valid
c
if
I
m
valid
m
if
error "none are valid" ( ) A 1 valid
m
( ) 1 valid
c
( ) 1 valid
r
( ) if
:
C
2
1.004pF
C
2
C
2r
valid
r
if
C
2c
valid
c
if
C
2m
valid
m
if
error "none are valid" ( ) F 1 valid
m
( ) 1 valid
c
( ) 1 valid
r
( ) if
:
C
1
2.107pF
C
1
C
1r
valid
r
if
C
1c
valid
c
if
C
1m
valid
m
if
error "none are valid" ( ) F 1 valid
m
( ) 1 valid
c
( ) 1 valid
r
( ) if
:
R
2
222.683k
R
2
R
2r
valid
r
if
R
2c
valid
c
if
R
2m
valid
m
if
error "none are valid" ( ) 1 valid
m
( ) 1 valid
c
( ) 1 valid
r
( ) if
:
R
1
142.905k
R
1c
valid
c
if
R
1m
valid
m
if
error "none are valid" ( ) 1 valid
m
( ) 1 valid
c
( ) 1 valid
r
( ) if
13
f
start
f
0
10
:
Starting Frequency for Plotting
f
stop
f
0
100 : Stopping Frequency for Plotting
f
i
f
stop
f
start

,
i
num
f
start
:

i
2 f
i
: s
i
j
i
:
Filter Response vs. Frequency
Frequency (MHz)
A
t
t
e
n
u
a
t
i
o
n

(
d
B
)
5.744 10
4

80
log A
max
( )
A
jammer
f
stop
MHz
f
start
MHz
f
jammer
MHz
f
notch
MHz
Functions
sallenkey f
0
Q , SNR , G , ( ) errval if G
1
8 Q
2

1 + >

,
G 1
1
Q
+
1
2 Q
2

<

,
1 , 0 ,

1
1
]

choice if G
1
8 Q
2

1 + < 0 , 1 ,

R
1
if choice
1
2
Q
2
1 G ( )
1 G ( )
2
Q
2
1 +

1
1
1
1
]
V
neq
2
V
n
2

4 k Temp
1 1
1
1
2 Q
Q 1 G ( )

1
1
]
2

1
1
1
1
]
,
V
neq
2
V
n
2

2 4 k Temp
,

1
1
1
1
1
]

if R
1
R
max
> R
max
, R
1
, ( )
R
2
if choice
V
neq
2
V
n
2

4 k Temp
R
1
, R
1
,

C
2
if choice
1
R
1
R
2
+ 1 G ( ) R
1
+

1
]
Q
0

,
1 1 8 Q
2
G 1 ( )

1
]
+
4 Q
0
R
,

1
1
1
]

C
1
if choice
1
R
1
R
2
+ 1 G ( ) R
1
+

1
]
Q
0

,
1

0
2
R
2
C
2

1
1
1
]

errval
R
1

R
2

:
14
R
2
182.794k Resistor 2 Value
C
1
x
4
F : C
1
3.669pF Capacitor 1 Value
C
2
x
5
F : C
2
1.834pF Capacitor 2 Value
1
.
10
4
1
.
10
5
1
.
10
6
1
.
10
7
1
.
10
8
100
80
60
40
20
0
20 log H
LPF
s
i
G , 2 f
0
, Q , ( ) ( )
f
i
Analysis yields:

0
1
R
1
R
2
C
1
C
2

0
R
1
R
2
, C
1
, C
2
, ( )
1
R
1
R
2
C
1
C
2

:

0
R
1
R
2
, C
1
, C
2
, ( )
2
0.336MHz
Q G R
1
, R
2
, C
1
, C
2
, ( )
1
R
1
R
2
C
1
C
2

1
R
1
C
1

1
R
2
C
1

+
1 G
R
2
C
2

+
: Q G R
1
, R
2
, C
1
, C
2
, ( ) 0.707
Q
C
1
C
2
R
1
R
2

R
1
R
2
+
=
1
C
2

0
R
1
R
2
+ (
=
H
SK
s G , R
1
, R
2
, C
1
, C
2
, ( ) H
LPF
s G ,
0
R
1
R
2
, C
1
, C
2
, ( ) , Q G R
1
, R
2
, C
1
, C
2
, ( ) , ( ) :
50
0
20 log
H
SK
s
i
G , R
1
, R
2
, C
1
, C
2
, ( )

_

R
2

C
1
F
C
2
F

,
Example
f
0
613.5kHz Center Frequency
Q 0.707 Desired Q
SNR 80 Minimum Signal to Noise Ratio
G 1 Gain
x sallenkey f
0
Q , SNR , G , ( ) :
errval x
1
: errval 0 Error? (0=error, 1=no error)
R
1
x
2
: R
1
182.794k Resistor 1 Value
R
2
x
3
:
15
_______________________________________
Copyright Information
Conclusions
choose G=1 for minimum sensitivity!
Other benefits of G=1:
- simplicity, low sensitivity of G ...
- good linearity: voltage accross R is zero in passband
Other Problems:
- sensitive to top/bottom plate parasitics
- sensitive to RC time constant variations
Use only in non-critical applications:
- low pole Q (hence restrict order to 4 or so)
- where large variations of cutoff frequency can be accepted
(typical variation of untrimmed RC time constants: +/- 30%)
Note: true only for very small variations ... large (e.g. 10%) changes
of R
1
will still change Q.
S
QR1
Q ( ) 0 : Version 2:
QbyQ 0.45 QbyQ S
QR1
5 ( )
R
1
R
1
: R
1
0.1 R
1
:
S
QR1
5 ( ) 4.5 S
QR1
Q ( ) Q
1
2
: Version 1:
Sensitivity

0
1.1 R
1
R
2
, C
1
, C
2
, ( )

0
R
1
R
2
, C
1
, C
2
, ( )
1 0.047
Q G 1.1 R
1
, R
2
, C
1
, C
2
, ( )
Q G R
1
, R
2
, C
1
, C
2
, ( )
1 1.134 10
3

1
.
10
4
1
.
10
5
1
.
10
6
1
.
10
7
1
.
10
8
40
30
20
10
0
20 log
H
SK
s
i
G , R
1
, R
2
, C
1
, C
2
, ( )
G

20 log
H
SK
s
i
G , R
1
1.1 , R
2
, C
1
, C
2
, ( )
G

f
i
"small" variations
1
.
10
4
1
.
10
5
1
.
10
6
1
.
10
7
1
.
10
8
100
50 20 log
G

f
i
16
Copyright Information
All software and other materials included in this document are protected by copyright, and are owned or controlled
by Circuit Sage.
The routines are protected by copyright as a collective work and/or compilation, pursuant to federal copyright laws,
international conventions, and other copyright laws. Any reproduction, modification, publication, transmission, transfer, sale,
distribution, performance, display or exploitation of any of the routines, whether in whole or in part, without the express
written permission of Circuit Sage is prohibited.
17