CS2100: Assignment 2

Bare-bones Implementation of a Single-cycle MIPS Processor

Gan Soon Bing 10 November 2011

Lab Session 7 Tutor: Zhao Jin

Submitted in partial fulfillment towards credit for CS2100: Computer Organisation

CS2100: Assignment 2 Gan Soon Bing A0073817Y

Augmenting the ALU:

The original adder/subtractor/negator created in Assignment 1 is augmented with the addition of logic circuits. First, the 32-bit versions of the AND and OR operators need to be constructed, and this is done simply through splitting the two 32-bit input into 1-bit inputs. For simplicitys sake, the two inputs are labelled Q and R. For the AND operation, each split 1-bit of Q is passed through the AND gate together with the corresponding 1-bit of R that is of the same bit order. In this way, Q0 is passed through the AND gate with R0, Q1 AND R1, etc. The resultant output is then passed through another splitter to re-combine the result into a 32-bit output. The same is done separately for the 32-bit version of the OR operator. The 32-bit NOT gate is created by passing a given 32-bit input Q through a splitter, and then passing each of the 1-bit through a NOT gate. The results are passed through another splitter to re-combine the result into a 32-bit output. The updated ALU circuit is constructed by feeding both 32-bit inputs, Q and R to each of the 32-bit AND, OR, and the adder created in assignment 1 simultaneously. A 1-bit multiplexer controls which of the two outputs from the 32-bit AND and OR would be passed through. The selector of this multiplexer goes to an input, AND-OR, that can be controlled by an ALU Control unit. The output selected in the last paragraph is then connected in parallel to another 1-bit multiplexer. The first path contains a 32-bit NOT gate, which would negate the 32-bit value, while the other path contains the output mentioned in the last paragraph, without modifications. The 1-bit multiplexer selects whether the negated version or the original version is passed through. This output (known as the Logical outcome) then appears at the input of yet another 1-bit multiplexer. The other input to the multiplexer would contain the output from the adder that was built in assignment 1 (known as the Arithmetic outcome). Depending on whether the selector bit is activated, either the Arithmetic outcome or the Logical outcome would be passed to the output of the ALU. In total, 3 bits control the 3 multiplexers which determine which output would be pushed through, and can be summarised in the table below: AND-OR X 0 1 1 0 NOT-PASSTHROUGH X 1 1 0 0 ARITHMETIC-LOGIC 0 1 1 1 1 Outcome Arithmetic Logical AND Logical OR Logical NOR Logical NAND

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Building the 32-register Register File

The basic component of each register in the register file is the D-flipflop. Each flipflop is able to represent and store 1-bit of memory. Hence, 32 D-flipflops are utilised to memorise 32-bits. However, to make implementation easier, a 4-bit D-flipflop is built, with 4 flipflops. The output is passed through a splitter to become a 4-bit output. Four of these 4-bit flipflops are then combined into a 16-bit flipflop. The 32-bit flipflop thus consists of two 16-bit flipflops. A write-enabled bit is passed through to all the flipflops to indicate when to memorise the data that is being passed in. The 32-bit flipflop forms a register. 31 of these registers are then built. A special constant 32-bit zero value is also created. The output of each of the 31 registers are connected to a 32-bit multiplexer, which then allows a selector 5-bit value to decide which register output would be passed as the output of the register file. The 32-bit multiplexer is duplicated to create a total of 2 multiplexers, capable of passing out the output of 2 different registers based on the corresponding selector bits passed to the respective multiplexers. On the other side, a de-multiplexer with 31 outputs to each of the registers controls which register a 1-bit write bit would be activated. Depending on the value of the 5-bit selector, the corresponding register number will receive the write-enabled bit. The 32-bit value to be written is piped to all the 31 registers, but only the register that receives the write-enabled bit will commit the 32-bit value into its memory. As a special note, de-multiplexer line 0 is not connected to any register file, as it represents the special 32-bit value of 0, which cannot be over-written. Similarly, this value is connected just like a normal register would to the 0th input for the 2 multiplexers controlling the register files output.

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Building the Control Unit

According to the specifications, the following functions needed to be achieved: add/addi, sub, and/andi, or/ori, lw/sw, slt/slti, beq/bne, and j. As the ALU that has been designed supports an additional operation, nor will be added to the project scope. The following table shows the possible input bits, and the outputs of the control unit:
Instruction MinTerm RegDst ALUSrc MemToReg RegWrite MemRead MemWrite Branch ALUOP2 ALUOP1 ALUOP0 BranchNE Jump SLTI

R-type j beq bne slti addi andi ori lw sw

m00 m02 m04 m05 m10 m08 m12 m13 m35 m43

1 x x x 0 0 0 0 0 x

0 x 0 0 1 1 1 1 1 1

0 x x x 0 0 0 0 1 x

1 0 0 0 1 1 1 1 1 0

0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 1

0 1 1 1 0 0 0 0 0 0

0 x 0 0 0 0 1 1 0 0

1 x 0 0 0 0 1 0 0 0

0 x 1 1 1 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 0

Each of the bits is read vertically to derive the actual composition expression: RegDst ALUSrc MemToReg RegWrite MemRead MemWrite Branch ALUOP2 ALUOP1 ALUOP0 (Op5 + Op4 + Op3 + Op2 + Op1 + Op0) Op3 + Op1 Op5.Op4.Op3.Op2.Op1.Op0 (Op5+Op4+Op3+Op2+Op1+Op0).(Op5+Op4+Op3+Op2+Op1).(Op5+Op4+Op3+Op2+Op1+Op0) Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1 (Op5.Op4.Op3.Op2.Op1.Op0) + (Op5.Op4.Op3.Op2.Op1.Op0) (Op5.Op4.Op3.Op2.Op1.Op0) + (Op5.Op4.Op3.Op2.Op1.Op0)

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CS2100: Assignment 2 Gan Soon Bing A0073817Y BranchNE Jump SLTI Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0

The diagram below describes the logical layout of the Control Unit:

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Building the ALU Control Unit

The ALU Control units input consist of the 3-bits: ALUOP2, ALUOP1, ALUOP0 from the Control Unit constructed in the section above, as well as inputs from the lower 6-bits from the 32-bit original instruction (also known as the Funct code). The Funct code portion matters as an input only if the instruction to be executed is a register type instruction. For all other instructions, the portion that matters relates only to ALUOP2, ALUOP1, ALUOP0. The outputs for the ALU Control Unit are the Subtract (S) bit, AND/OR bit, NOT/PASSTHROUGH bit, ARITHMETIC/LOGIC bit, as well as a SLT bit. The logic table for the outputs are listed: Operation ALU Operation lw add sw add beq sub bne sub add add sub sub and and or or slt sub nor nor addi add andi and ori or slti sub j x ALUOP 2 to 0 000 000 001 001 010 010 010 010 010 010 000 110 100 001 xxx Funct (F5-F0) xxxxxx xxxxxx xxxxxx xxxxxx 100000 100010 100100 100101 101010 100111 xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx E 0 0 0 0 0 0 x x 0 x 0 x x 0 x S 0 0 1 1 0 1 x x 1 x 0 x x 1 x AND/OR x x x x x x 0 1 x 1 x 0 1 x x NOT/PASSTHROUGH ARITHMETIC/LOGIC x x x x x x 0 0 x 1 x 0 0 x x 0 0 0 0 0 0 1 1 0 1 0 1 1 0 x

Each of the outputs: E, S, AND/OR, NOT/PASSTHROUGH, ARITHMETIC/LOGIC are expressed in terms of the inputs ALUOP and Funct. E S AND/OR NOT/PASS ARITHMETIC/LOGIC 0 (Op2+Op1+Op0+F5+F4+F3+F2+F1+F0).(Op2+Op1+Op0) (Op2+Op1+Op0+F5+F4+F3+F2+F1+F0).(Op2+Op1+Op0) Op2+Op1+Op0+F5+F4+F3+F2+F1+F0 (Op2.Op1.Op0.F5.F4.F3.F2) + (Op5.Op3)

The ALU Control Unit is then created as per the following diagram:

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Creating the Instruction Memory portion:

To make implementation simple, a RAM unit is used to store 32-bit instructions. However, the unit is capable of only 8-bit addressing. An 8-bit register provides an 8-bit address for the RAM to access at the current cycle. In the meantime, the same 8-bit is also passed through an adder to derive the next instruction address to process at the next clock cycle. This utilises the original adder built in assignment 1 to increment the value of the address bits by 1, and passes it as a form of input to the 8-bit register for the next clock cycle. When the next clock cycle hits, the 8-bit register then updates with the new address, and thus pushes the RAM to access the new address.

To mimic the original MIPS processing of word addressing, the addresses of the RAM already address 32-bits of data. Thus each increment of 1 in the address will automatically address 4 bytes of data; Hence in this implementation, the PC counter is incremented by 1, instead of by the usual 4.

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Additional modification to accept branching and jumps

To enable the address of the next instruction to be executed to be controllable through branching and jumps, the original circuit described in the previous section has been modified such that the output of the adder goes through a series of multiplexers before returning to the 8-bit register. The first multiplexer concerns the branching operation, where an offset supplied by the instruction code bits 0-15 would be added to the original PC + 1 value. If the selector of the multiplexer is not flagged (set to 0), then the original PC + 1 value will be passed through the multiplexer. However, if the multiplexer is flagged, then the alternate value of PC + 1 + offset is passed through instead. The input to the selector of the multiplexer depends on whether the Branch flag from the Control Unit is flagged, as well as whether the result of the ALU operation is Zero. Since the instruction beq must be supported too, the combination of the output BranchNE from the Control Unit AND the negated result of the Zero flag from the ALU is also used.

Thus, if it so happens that the Branch flag is on, and the result of the operation in the ALU raises the Zero flag (i.e. the 2 input values to the ALU are equal), then the selector will assert, and the output of the multiplexer will be from the PC + 1 + sign-extended Instr[15-0]. Similarly, if the BranchNE flag is on, and the result of the operation fails to raise the Zero flag, the multiplexer will assert, and the output of the multiplexer will be from the PC + 1 + sign-extended Instr[15-0]. The output from the multiplexer then goes to another multiplexer, which chooses between the output mentioned in the paragraph above, and the zero-extended value of the jump immediate. The selector is linked to the Jump flag output from the Control Unit. If this is asserted, the value of the jump immediate is passed through instead of the output from the previous paragraph, such that at

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CS2100: Assignment 2 Gan Soon Bing A0073817Y the next clock cycle, the RAM will access the instruction at the address listed in the jump immediate.

Working with the instructions from the Instruction Memory

The instructions that are output from the Instruction Memory are 32-bits, of which the first 6 bits (31-26) constitute the OpCode. This is passed as an input to the Control Unit so that the flags for the rest of the circuit are set accordingly. Page | 10

CS2100: Assignment 2 Gan Soon Bing A0073817Y The next 5 bits (25-21) consist of the rs portion of the instruction. This indicates which register to read the data from, and is connected directly to the first multiplexer in the register file. Similarly, the 5 bits after that (20-16) is rt portion of the instruction, and also indicates which register to read the data from. This is connected directly to the second multiplexer in the register file. Coincidentally, the 5-bits (20-16) is also connected to a multiplexer that controls which register would be written to. The other input to the multiplexer comes from 5-bits of the instruction (15-11). A selector for the multiplexer is connected to RegDST output of the Control Unit, which would raise the flag to select from the rd field of the instruction as the destination for register-type operations. If RegDST is not asserted, then the destination comes from the rt field of the instruction. Externally, the register file is connected to the 3 inputs listed in the previous 2 paragraphs. In addition to that, a special RegWrite flag form the Control Unit decides whether the register file is written to or not. The bottom right side of the register file contains the 2 32-bit outputs from the registers that have been requested to be read from. The bottom left contains the input data (32-bits) to be written to the register. The Funct field applies only for register type instructions, and is extracted from the last 5-bits of the instruction (5-0). This is connected to the ALU Control unit as part of its input to determine the final operation for the ALU unit. In addition, the last 16-bits of the instruction contain the immediate values for immediate operations, and are extended to 32-bits. Sign-extension is used for immediates used for arithmetic processing, while zero-extension is used for immediates that would be used for logic processing in the ALU. The multiplexer that controls this is selected by the ARITHMETIC-LOGIC output from the ALU Control Unit. The jump immediate is the last 26 bits of the instruction (25-0), and is extracted to be used in determining which instruction should be executed in the next clock cycle.

Connecting the ALU and Data Memory

The ALU takes input from the ALU control unit, which determines the final operation of the ALU, whether it is a And or Or operation, Arithmetic or Logic operation, and whether to do subtraction for arithmetic operation. The output from the ALU is passed through a multiplexer that controls whether the operation output of the ALU is passed on, or the 1-bit Negate bit. This is used for slt and slti operations. Thus, the multiplexer input comes from both the SLT and SLTI input. This output is then displayed at both the Data Memory as the address input for the Data Memory, as well as by-passing it. The portion that goes to the Data Memory will cause the RAM to return the 32bit value that is stored at that memory location. The output from the RAM will meet the original output from the multiplexer mentioned in the previous paragraph at yet another multiplexer. This multiplexer controls whether the information from the Data Memory would be used (hence utilizing the ALU output as the input address to access data memory), or whether the ALU output is pushed on to appear at the data-in location of the registry file. The selector is controlled by the MemToReg flag controlled by the Control Unit described in an earlier section.

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CS2100: Assignment 2 Gan Soon Bing A0073817Y On the Data Memory unit, the data port is connected to the first output from the register file, effectively retrieving the 32-bit value stored in the register number specified by the rs field of the instruction. The MemWrite flag controlled by the Control Unit decides whether the Data Memory is to be written to. The MemRead flag is similarly controlled by the Control Unit to decide whether the Data Memory should operate.

Conclusion and Limitations

The implemented circuit is a single-cycle implementation of a processor. This is unrealistic as compared to the real world, where access to Data Memory elements usually take multiple cycles to complete. However, for the purpose of this assignment, the single-cycle implementation of the processor is assumed to be sufficient for the requirement specifications. The following instructions have been implemented and tested: add/addi, sub, and/andi, or/ori, lw/sw, slt/slti, beq/bne, and j. In order to score bonus marks, an additional implementation for nor has been added. Test cases that provide rudimentary unit testing may be found at the end of this document. The accompanying RAM images accompany this document, and may be loaded into the circuit to run test cases easily. When running the test cases, special care needs to be taken to ensure that no part of the circuit turns red, especially when opening the file. This is an issue with Logisim that seems to appear at random openings of the source file. In no way should the circuit malfunction during testing, as demonstrated during the demo. The next section describes the steps to be taken if errors occur during testing of the test cases listed at the end of this document.

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Contents of the archive:

A0073817Y-Assignment2.circ
This is the main circuit file.

A0073817Y.circ
This file contains the adder/subtractor/negator as built in Assignment 1, and is used as a library in the main circuit file.

ALU.circ
This file contains the combination of the original adder/subtractor/negator, added with logic operations to create a semi-complete ALU. Shifting is not within the scope of this assignment, and hence will not be included.

Extended Test Case.txt

This contains the memory image for the instruction memory for the processor circuit. Load this image into the instruction memory, and step through with the aid of Test Case 2 to conduct blackbox testing for the entire circuit.

Extended Test Case 2.txt

This contains the memory image for the instruction memory for the processor circuit. Load this image into the instruction memory, and step through with the aid of Test Case 1 to conduct unit testing for each of the instructions.

Caveat when opening project file:

Please make sure that there is sufficient memory space for the Java Runtime Environment when opening the file to prevent quirky issues with components not working. In addition, there is a possibly of LogiSim bugging out in the middle of testing, so if any red lines appear, please restart the program. In the event of any red lines in the circuit, please close LogiSim, relaunch it, and re-open the project file: 1. Launch LogiSim with extended memory parameters: "C:\Program Files (x86)\Java\jre6\bin\java" -Xms32M -Xmx512M -jar logisim-generic2.7.1.jar 2. Open the project file A0073817Y-Assignment2.circ. 3. Open the main processor circuit named Processor Circuit. 4. If any part of the circuit displays in red, then please close LogiSim, and re-open LogiSim.

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Test Case 1:
The following test case attempts to test the proper functionality for the following implemented instructions: addi/add/sub/and/andi/or/ori/slt/bne. The state of the first 10 registers after each instruction has been executed is also listed in the table. Instruction addi $1, $0, 1 addi $2, $0, 3673 add $3, $1, $2 addi $4, $1, 7 sub $5, $3, $4 addi $4, $4, -1 and $6, $5, $4 andi $7, $5, 255 or $8, $5, $1 ori $9, $8, $9 slt $10, $8, $9 nor $10, $1, $10 bne $8, $9, -12 Encoded 20010001 20020E59 00221820 20240007 00642822 2084FFFF 00A43024 30A700FF 00A14025 3509000C 0109502A 002A5027 1509FFF3 $1 1 1 1 1 1 1 1 1 1 1 1 1 1 $2 0 3673 3673 3673 3673 3673 3673 3673 3673 3673 3673 3673 3673 $3 0 0 3674 3674 3674 3674 3674 3674 3674 3674 3674 3674 3674 $4 0 0 0 8 8 7 7 7 7 7 7 7 7 $5 0 0 0 0 3666 3666 3666 3666 3666 3666 3666 3666 3666 $6 0 0 0 0 0 0 2 2 2 2 2 2 2 $7 0 0 0 0 0 0 0 82 82 82 82 82 82 $8 0 0 0 0 0 0 0 0 3667 3667 3667 3667 3667 $9 $10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3679 3679 1 3679 -2 3679 -2

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CS2100: Assignment 2 Gan Soon Bing A0073817Y

Test Case 2:
The following test case attempts to test the proper functionality for the following implemented instructions: sw/slt/lw/beq/j. j7 addi $1, $0, 100 addi $4, $0, 16 sw $1, -4($4) lw $2, -4($4) add $3, $1, $2 slt $5, $2, $3 slti $6, $2, 101 beq $4, $1, -7 08000008 20010064 20040010 AC81FFFC 8C82FFFC 00221820 0043282A 28460064 1022FFF8 Jump to instruction at address 8 $1 = 100 $4 = 16 M[12] = 100 $2 = 100 $3 = 200 $5 = 1 $6 = 1 Jump to instruction at address 9 8 = 1 0 1 2 3 4 5 6 7 8

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