CPLD xc95

0
XC2C512 CoolRunner-II CPLD

0 0
DS096 (v3.2) March 8, 2007
Product Specification
Features
Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 A quiescent current Industrys best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation 1.5V to 3.3V Available in multiple package options - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 212 user I/O - 324-ball FG (1.0mm) BGA with 270 user I/O - Pb-free available for all packages Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management DataGATE enable signal control - Four separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide by 2,4,6,8,10,12,14,16) CoolCLOCK - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Advanced design security - PLA architecture Superior pinout retention 100% product term routability across function block - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pullup on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility - Hot Pluggable
Description
The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.
Refer to the CoolRunner-II family data sheet for architecture description.
2002-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS096 (v3.2) March 8, 2007 Product Specification
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XC2C512 CoolRunner-II CPLD By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is I/O banking. Four I/O banks are available on the CoolRunner-II 512 macrocell device that permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The CoolRunner-II 512 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL I/O standards make use of a VREF pin for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C512(1) IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15(2) HSTL_1 SSTL2_1 SSTL3_1 Output VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Input VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Board Input Termination VREF Voltage VTT N/A N/A N/A N/A N/A 0.75 1.25 1.5 N/A N/A N/A N/A N/A 0.75 1.25 1.5
RealDigital Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance and low power operation.
Supported I/O Standards

The CoolRunner-II 512 macrocell features LVCMOS, LVTTL, SSTL, and HSTL I/O implementations. See Table 1
250
(1) For information on Vref pins, see XAPP399. (2) LVCMOS15 requires Schmitt-trigger inputs.
200
150
ICC (mA)
100
50
0 0 20 40 60 80 100 120 140 160 180

DS096_01_030705
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical ICC (mA) 0.025 20 17.22 40 34.37 60 52.04 80 69.44 100 86.85 120 105.13 140 122.68 160 140.23 180 157.78
Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block).
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Absolute Maximum Ratings

Symbol VCC VCCIO VJTAG(2) VCCAUX VIN(1) VTS(1) TSTG(3) TJ Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground(1) Voltage applied to 3-state output(1) Storage Temperature (ambient) Junction Temperature Value 0.5 to 2.0 0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 0.5 to 4.0 0.5 to 4.0 65 to +150 +150 Units V V V V V V C C
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to 2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427.
Recommended Operating Conditions

Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0C to +70C Industrial TA = 40C to +85C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VCCAUX
JTAG programming
DC Electrical Characteristics (Over Recommended Operating Conditions)

Symbol ICCSB ICCSB ICC
(1)
Parameter Standby current Commercial Standby current Industrial Dynamic current JTAG input capacitance Global clock input capacitance I/O capacitance Input leakage current I/O High-Z leakage
Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V
Typical 50 150 -
Max. 240 400 1 55 10 12 10 +/1 +/1
Units A A mA mA pF pF pF A A
CJTAG CCLK CIO IIL

(2)
IIH(2)
Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at VCC= VCCIO = 1.9V. 2. See Quality and Reliability section of the CoolRunner-II family data sheet.
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LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage Test Conditions IOH = 8 mA, VCCIO = 3V IOH = 0.1 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Min. 3.0 2 0.3 VCCIO 0.4V VCCIO 0.2V Max. 3.6 3.9 0.8 0.4 0.2 Units V V V V V V V
LVCMOS 2.5V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage Test Conditions IOH = 8 mA, VCCIO = 2.3V IOH = 0.1 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V IOL = 0.1mA, VCCIO = 2.3V Min. 2.3 1.7 0.3 VCCIO 0.4V VCCIO 0.2V Max. 2.7
VCCIO +
Units V V V V V V V
0.3(1))
0.7 0.4 0.2
(1) The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.
LVCMOS 1.8V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage Test Conditions IOH = 8 mA, VCCIO = 1.7V IOH = 0.1 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V Min. 1.7 0.65 x VCCIO 0.3 VCCIO 0.45 VCCIO 0.2 Max. 1.9
VCCIO
Units V V V V V V V
+ 0.3(1) -
0.35 x VCCIO
0.45 0.2
(1) The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.
LVCMOS 1.5V DC Voltage Specifications(1)

Symbol VCCIO VIH VIL Parameter Input source voltage High level input voltage Low level input voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 1.6 0.8 x VCCIO 0.5 x VCCIO Units V V V
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Symbol VOH VOL
Parameter High level output voltage Low level output voltage
Test Conditions IOH = 8 mA, VCCIO = 1.4V IOH = 0.1 mA, VCCIO = 1.4V IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V
Min. VCCIO 0.45 VCCIO 0.2 -
Max. 0.4 0.2
Units V V V V
Notes: 1. Hysteresis used on 1.5V inputs.
Schmitt Trigger Input DC Voltage Specifications

Symbol VCCIO VT+ VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 3.9 0.8 x VCCIO 0.5 x VCCIO Units V V V
SSTL2-1 DC Voltage Specifications

Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = 8 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V Test Conditions Min. 2.3 1.15 VREF 0.04 VREF + 0.18 0.3 VCCIO 0.62 Typ 2.5 1.25 1.25 Max. 2.7 1.35 VREF + 0.04 3.9 VREF 0.18 0.54 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
SSTL3-1 DC Voltage Specifications

Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = 8 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V Test Conditions Min. 3.0 1.3 VREF 0.05 VREF + 0.2 0.3 VCCIO 1.1 Typ 3.3 1.5 1.5 Max. 3.6 1.7 VREF + 0.05 VCCIO + 0.3 VREF 0.2 0.7 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
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HSTL1 DC Voltage Specifications

Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = 8 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V Test Conditions Min. 1.4 0.68 VREF + 0.1 0.3 VCCIO 0.4 Typ 1.5 0.75 VCCIO x 0.5 Max. 1.6 0.90 1.9 VREF 0.1 0.4 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak-to-peak AC noise on VREF may not exceed 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
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AC Electrical Characteristics Over Recommended Operating Conditions

-7 Symbol TPD1 TPD2 TSUD TSU1 TSU2 TH TH TCO FTOGGLE
(1) (2) (2)
-10 Max. 7.1 7.5 5.8 250 179 167 119 114 7.3 6.5 7.5 8.6 7.6 7.5 9.3 400 Min. 4.0 3.1 3.9 0 0 2.8 1.7 2.5 0.4 1.7 3.2 0 3.0 10.0 10.0 0.0 6.0 5.0 2.5 0 Max. 9.2 10.0 7.9 166 128 116 91 85 9.3 9.2 10.2 12.5 11.6 11.5 11.0 400 Units ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Parameter Propagation delay (single p-term) Propagation delay (OR array) Direct input register set-up time Setup time fast (single p-term) Setup time (OR array) Direct input register hold time P-term hold time Clock to output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Direct input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Asynchronous preset/reset pulse width (High or Low) Set-up before DataGATE latch assertion Hold to DataGATE latch assertion DataGATE recovery to new data DataGATE low pulse width CDRST setup time before falling edge GCLK2 Hold time CDRST after falling edge GCLK2
Min. 3.4 2.6 3.0 0 0 2.1 1.1 1.5 0.1 1.3 2.8 0 2.0 7.5 7.5 0.0 4.0 3.0 1.7 0 -
FSYSTEM1 FSYSTEM2 FEXT1

(3)
FEXT2(3) TPSUD TPSU1 TPSU2 TPHD TPH TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TPCW TAPRPW TDGSU TDGH TDGR TDGW TCDRSU TCDRH TCONFIG
(4)
Configuration time
Notes: 1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more information). 2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit Resetable binary counter through one p-term per macrocell while FSYSTEM2 is through the OR array. 3. FEXT1(1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array 4. Typical configuration current during TCONFIG is approximately 15mA DS096 (v3.2) March 8, 2007 Product Specification www.xilinx.com 7
Internal Timing Parameters(1)

-7 Symbol
Buffer Delays
-10 Max. 3.1 4.4 2.4 3.8 2.9 3.0 3.6 0.8 0.5 0.4 0.5 0.4 0.7 0 3.3 2.2 3.0 0.8 3.0 2.0 0 2.5 Min. 1.8 0 1.8 0 Max. 3.8 5.5 3.3 4.6 3.7 3.9 5.5 0.9 0.8 0.8 0.7 0.7 3.0 0 4.5 3.0 4.0 1.0 4.0 3.0 0 4.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter(1) Input buffer delay Direct data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single P-term delay adder Multiple P-term delay adder Input to output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Clock doubler delay Feedback delay Macrocell to global OE delay Hysteresis input adder Output adder Output slew rate adder Hysteresis input adder Output adder Output slew rate adder
Min. 1.4 0 1.3 0 -
TIN TDIN TGCK TGSR TGTS TOUT TEN

P-term Delays
TCT TLOGI1 TLOGI2

Macrocell Delay
TPDI TSUI THI TECSU TECHO TCOI TAOI TCDBL

Feedback Delays
TF TOEM THYS15 TOUT15 TSLEW15 THYS18 TOUT18 TSLEW18
I/O Standard Time Adder Delays 1.5V CMOS
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Internal Timing Parameters(1) (Continued)

-7 Symbol TIN25 THYS25 TOUT25 TSLEW25 TIN33 THYS33 TOUT33 TSLEW33 SSTL2-1 SSTL3-1 HSTL-1 Parameter(1) Standard input adder Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder Input adder to TIN, TDIN, TGCK, TGSR,TGTS Output adder to TOUT Input adder to TIN, TDIN, TGCK, TGSR,TGTS Output adder to TOUT Input adder to TIN, TDIN, TGCK, TGSR,TGTS Output adder to TOUT
Notes: 1. 1.5 ns input pin signal rise/fall.
-10 Max. 0.6 1.5 0.8 3.0 0.5 1.2 1.2 3.0 0.4 -0.5 0.6 0.0 0.8 0.0 Min. Max. 1.0 3.0 2.0 4.0 2.0 3.0 3.0 4.0 1.0 0.0 1.0 0.0 1.0 0.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min. -
I/O Standard Time Adder Delays 3.3V CMOS/TTL
I/O Standard Time Adder Delays HSTL, SSTL
Switching Characteristics
VCC = VCCIO = 1.8V @ 25oC
7.0
AC Test Circuit
VCC R1
6.8
Device Under Test R2 CL
Test Point
6.6
TPD2 (ns)
Output Type
R1 268 275 188 112.5 150
R2 235 275 188 112.5 150
CL 35 pF 35 pF 35pF 35pF 35pF
6.4
LVTTL33 LVCMOS33 LVCMOS25
6.2
LVCMOS18 LVCMOS15
6.0 1 2 4 8 16
CL includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs.
DS_ACT_08_14_02
Number of Outputs Switching

DS096_02_022003
Figure 3: Load Circuit
Figure 2: Derating Curve for TPD
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Typical I/O Output Curves

The I/V curve illustrates the nominal amount of current that an I/O can source/sink at different voltage levels.
80
IO (Output Current mA)
60
3.3V 2.5V 1.8V
40
IOL 1.5V
20
0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5
VO (Output Volts)
XC512VoIo_all022003
Figure 4: Typical I/V Curves for XC2C512
10
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Pin Descriptions
11
Pin Descriptions (Continued)

FT256 D4 B2 E3 C3 D3 B3 B4 C4 A1 D2 C2 E5 B1 E4 FG324 C1 C2 B1 B2 D3 C3 A1 A2 D2 D1 F4 F3 E2 E1 F2 G4 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 205 203 202 201 200 199 14 15 16 17 18 FT256 A2 C5 A3 E7 A4 C6 B5 C1 E2 F2 E6 F3 D1 G4 E1 FG324 B3 C4 B4 C5 B5 A3 A4 D6 A5 G3 G2 G1 H4 H3 H2 H1 J4 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 7 6 5 4 3 2 208 206 8 9 10 12
Function Block 1(GTS0) 1 1(GTS3) 1 1 1 1 1 1 1 1 1 1(GTS2) 1 1 1(GSR) 2 2 2 2 2 2 2 2 2 2 2 2 2 2(GTS1) 2 2
Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PQ208
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Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 198 197 196 195 194 193 192 19 20 21 FT256 D6 A5 E8 B6 C7 A6 D7 B7 G3 G2 F5 F1 G5 FG324 C6 B6 A6 D7 C7 B7 A7 D8 C8 J3 J2 J1 K4 K3 K2 K1 L1 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 191 189 188 187 186 185 184 183 22 23 25 FT256 E9 A7 D8 B8 C8 A8 E11 E10 H2 H4 G1 H3 H1 H5 FG324 B8 A8 D9 C9 B9 A9 D10 C10 B10 L4 L3 L2 M1 M2 M3 M4 N1 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
12
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Function Block 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9(GCK1) 10(CDRST) 10 10(GCK2) 10 10 10 10 10 10 10 10 10 10 10(DGE) 10 10 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 50 49 48 47 46 51 54 55 56 57 58 FT256 N3 R1 N4 N2 M3 P2 P4 P5 R2 T1 T2 N5 FG324 AA2 AB1 AA1 W4 Y3 Y2 W3 Y1 AB2 Y4 AB3 AA4 Y5 AA5 AB4 W6 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Function Block 11 11 11(GCK0) 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 45 44 43 41 40 39 38 60 61 62 63 64 65 66 67 FT256 P1 M4 M2 L3 N1 L4 M1 L5 R4 M5 R5 R6 N6 R3 FG324 W2 W1 V3 U4 V2 V1 U3 U2 AB5 Y6 AA6 AB6 W7 Y7 AA7 AB7 W8 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Function Block 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 37 36 35 34 32 69 70 71 72 73 FT256 K4 L2 K3 L1 K5 K2 M6 T3 P6 T4 P7 T5 FG324 U1 T4 T3 T2 T1 R4 R3 R2 Y8 AA8 AB8 W9 Y9 AA9 AB9 W10 Y10 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Function Block 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 31 30 29 28 27 74 75 76 77 78 FT256 J4 K1 J3 J2 J5 J1 N7 R7 M7 T6 FG324 R1 P4 P3 P2 P1 N4 N3 N2 AA10 AB10 AB11 W11 AA11 Y11 AB12 AA12 Y12 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14
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Function Block 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 161 162 163 164 165 166 167 168 169 160 159 158 FT256 A16 B13 B14 C13 A15 C12 B12 B15 C14 G11 B16 D14 C15 FG324 A21 B20 C19 B19 C18 B18 A19 D17 A18 A22 B21 B22 C20 C21 D19 D20 C22 I/O Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

Function Block 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 170 171 173 155 154 153 152 151 150 FT256 D13 A14 E13 A13 C11 A12 B11 D11 A11 G12 D15 E14 C16 F14 D16 F13 E15 FG324 C17 B17 A17 D16 C16 B16 A16 D15 C15 D21 D22 E20 F19 E21 E22 F20 F21 I/O Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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Function Block 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 174 175 178 149 148 147 146 145 144 143 142 FT256 D10 B10 E12 F12 G13 F15 G14 E16 H12 F16 H16 FG324 B15 A15 D14 B14 A14 D13 C13 B13 A13 F22 G19 G20 G21 G22 H19 H20 H21 I/O Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

Function Block 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 179 180 182 140 139 138 137 136 135 134 FT256 B9 C9 C10 A9 D9 G15 H13 G16 H14 H15 J12 K12 J16 FG324 A12 D12 B12 C12 A11 B11 C11 D11 A10 H22 J19 J20 J21 J22 K19 K20 K21 I/O Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
16
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Function Block 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 110 111 112 113 114 115 116 117 109 108 107 106 103 102 101 100 FT256 R16 N15 M15 M13 P16 N16 L14 M14 N14 T16 R15 P15 P14 P13 R13 N13 R14 FG324 W22 V20 V21 U19 V22 U20 U21 U22 Y22 W21 W20 Y21 Y20 AA22 AB22 AA21 AB21 I/O Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

Function Block 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 118 119 120 121 99 97 95 FT256 L15 L13 M12 M16 K14 T15 R12 T14 N11 P11 M11 T13 N10 FG324 T19 T20 T21 T22 R19 R20 R21 R22 W19 AA20 Y18 AA19 W17 Y17 AA18 AB18 AA17 I/O Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
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17

Function Block 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 122 123 125 91 90 89 88 87 86 FT256 L16 K15 L12 T12 P10 T11 R10 M10 T10 M9 R9 FG324 P19 P20 P21 P22 N19 N21 N22 M22 AB17 W16 Y16 AA16 AB16 W15 Y15 AA15 AB15 I/O Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

Function Block 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 126 127 128 131 85 84 83 82 80 FT256 K16 J14 J15 J13 P9 N9 T9 M8 T8 P8 R8 T7 N8 FG324 M19 M20 M21 L22 L21 L20 L19 K22 W14 Y14 AA14 AB14 W13 Y13 AA13 AB13 W12 I/O Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable. 2. GCK, GSR, and GTS pins can also be used for general purpose I/O.
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XC2C512 JTAG, Power/Ground, No Connect Pins and Total User I/O

Pin Type TCK TDI TDO TMS VCCAUX (JTAG supply voltage) Power internal (VCC) Power Bank 1 I/O (VCCIO1) Power Bank 2 I/O (VCCIO2) Power Bank 3 I/O (VCCIO3) Power Bank 4 I/O (VCCIO4) Ground PQ208 98 94 176 96 11 1, 53, 124 33,59,79 26, 204 92, 105, 132 133, 157, 172, 181 13, 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 FT256 P12 R11 A10 N12 F4 P3, K13, D12, D5 J6, K6, L7, L8 F7, F8, G6, H6 J11, K11, L9, L10 F9, F10, H11 F6, F11, G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10, L6, L11 FG324 Y19 AB19 C14 AB20 F1 E3, AA3, N20, A20, D4 M9, N9, P10, P11 J10,J11, K9, L9 M14, N14, P12, P13 J12, J13, K14, L14 D5, D18, E4, E19, J9, J14, K10, K11, K12, K13, L10, L11, L12, L13, M10, M11, M12, M13, N10, N11, N12, N13, P9, P14, V4, V19, W5, W18 270
No connects Total user I/O (includes dual function pins)
173
212
Device Part Marking
Device Type Package Speed Operating Range
XC2Cxxx TQ144 7C
This line not related to device part number
Figure 5: Sample Package with Part Marking
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Ordering Information
Commercial (C) Part Number XC2C512-7PQ208C XC2C512-10PQ208C XC2C512-7FT256C XC2C512-7FT256I XC2C512-10FT256C XC2C512-7FG324C XC2C512-10FG324C XC2C512-7PQG208C XC2C512-10PQG208C XC2C512-7FTG256C XC2C512-7FTG256I XC2C512-10FTG256C XC2C512-7FGG324C XC2C512-10FGG324C XC2C512-10PQ208I XC2C512-10FT256I XC2C512-10FG324I XC2C512-10PQG208I XC2C512-10FTG256I XC2C512-10FGG324I Pin/Ball Spacing 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 0.5mm 1.0mm 1.0mm 0.5mm 1.0mm 1.0mm JC JA (C/Watt) (C/Watt) 35.1 35.1 32.2 32.2 32.2 39.1 39.1 35.1 35.1 32.2 32.2 32.2 39.1 39.1 35.1 32.2 39.1 35.1 32.2 39.1 7.2 7.2 4.9 4.9 4.9 5.0 5.0 7.2 7.2 4.9 4.9 4.9 5.0 5.0 7.2 4.9 5.0 7.2 4.9 5.0 Package Type Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin BGA Fine Pitch Thin BGA Fine Pitch Thin BGA Fine Pitch BGA Fine Pitch BGA Plastic Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch BGA; Pb-free Fine Pitch BGA; Pb-free Plastic Quad Flat Pack Fine Pitch Thin BGA Fine Pitch BGA Plastic Quad Flat Pack; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch BGA; Pb-free Package Body Dimensions 28mm x 28mm 28mm x 28mm 17mm x 17mm 17mm x 17mm 17mm x 17mm 23mm x 23mm 23mm x 23mm 28mm x 28mm 28mm x 28mm 17mm x 17mm 17mm x 17mm 17mm x 17mm 23mm x 23mm 23mm x 23mm 28mm x 28mm 17mm x 17mm 23mm x 23mm 28mm x 28mm 17mm x 17mm 23mm x 23mm I/O 173 173 212 212 212 270 270 173 173 212 212 212 270 270 173 212 270 173 212 270 Industrial (I)(1) C C C I C C C C C C I C C C I I I I I I
Notes: 1. C = Commercial (TA = 0C to +70 C); I = Industrial (TA = 40C to +85C)..
Standard Example: XC2C128 Device Speed Grade Package Type Number of Pins Temperature Range
-7 TQ
144
Pb-Free Example: XC2C128 Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range
-7 TQ
144
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VCC I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O VAUX I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCCIO2 I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O(2) I/O I/O(2) I/O I/O I/O I/O I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
I/O GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4 I/O I/O I/O GND TDO I/O I/O I/O VCCIO4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4
PQ208 Top View
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VCC I/O I/O(2) I/O I/O I/O(5) VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO3 GND TDI I/O TMS I/O TCK I/O I/O I/O I/O I/O GND
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO4 VCCIO3 I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO3
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
Figure 6: PQ208 Plastic Quad Flat Pack
www.xilinx.com
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15
14
13
12
11
10
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A B C D E F G H J K L M N P R T
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(3)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O(1)
I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(1)
I/O
I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCIO4 VCCIO4 VCCIO2 VCCIO2
GND
I/O
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO4
GND
GND
GND
GND
VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO3
GND
GND
GND
GND
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O(2)
I/O
I/O
I/O
I/O
I/O
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O
VCC
I/O(4)
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(5)
I/O
FT256 Bottom View
Figure 7: FT256 Fine Pitch Thin BGA
22
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16
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14
13
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2
I/O(3) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(4)
A B C D E F G H J K L M N P R T U V W Y AA AB
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O(1) I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O(1)
I/O
I/O
I/O
I/O
GND
GND
VCC
I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O I/O
I/O I/O
I/O I/O
I/O
I/O
I/O
I/O
VCCIO4 VCCIO4
GND
GND
GND
GND
VCCIO2 VCCIO2
I/O
I/O
I/O
I/O
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO3
GND
GND
GND
GND
VCCIO1
I/O I/O
I/O I/O
I/O I/O
I/O
I/O
VCC
I/O
VCCIO3
GND
GND
GND
GND
VCCIO1
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND I/O I/O I/O
GND
I/O(2)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O I/O
I/O I/O
I/O TMS
I/O TDI
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O(5) I/O
I/O I/O
VCC I/O(2)
I/O I/O
FG324 Bottom View
Figure 8: FG324 Fine Pitch BGA
www.xilinx.com
1
23
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
Additional Information
Additional information is available for the following CoolRunner-II topics: XAPP784: Bulletproof CPLD Design Practices XAPP375: Timing Model XAPP376: Logic Engine XAPP378: Advanced Features XAPP382: I/O Characteristics XAPP389: Powering CoolRunner-II XAPP399: Assigning VREF Pins To access these and all application notes with their associated reference designs, click the following link and scroll down the page until you find the document you want: CoolRunner-II Data Sheets and Application Notes Device Packages
Revision History
The following table shows the revision history for this document. Date 7/19/02 3/15/03 11/25/03 1/26/04 8/03/04 10/01/04 01/30/05 03/07/05 03/20/06 02/15/07 Version 1.0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 3.0 3.1 Initial Xilinx release. Added characterization data. Fixed two typos. Updated Tsol; added links to Data Sheets and Application Notes. Pb-free documentation Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. Change to ICCSB MAX for Commercial and Industrial. Removed -6 speed grade. Modified Table 1, IOSTANDARDs. Change to Product Specification. Add warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can also be used for general purpose I/O. Corrections to timing parameters tDIN, tSUD, tPSUD, tPHD, tPH, tSLEW18, tIN (HSTL), tOUT(SSTL3), and tTin (SSTL3) for -6 speed grade. Corrections to tDIN, tSUD, tCO, tPSUD, tPHD, and tPH for the -7 speed grade. Values now match the software. There were no changes to silicon or characterization. Added XC2C512-7FT256I and XC2C512-7FTG236I packages. Change to VIH specification for 2.5V and 1.8V LVCMOS. Fixed typo in note for VIL for LVCMOS18; removed note for VIL for LVCMOS33. Revision
03/08/07
3.2
24
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XC2C512 CoolRunner-II CPLD

DS096 (v3.2) March 8, 2007

Refer to the CoolRunner-II family data sheet for architecture description.

DS096 (v3.2) March 8, 2007 Product Specification

RealDigital Design Technology

Supported I/O Standards

0 0 20 40 60 80 100 120 140 160 180

DS096 (v3.2) March 8, 2007 Product Specification

XC2C512 CoolRunner-II CPLD

Absolute Maximum Ratings

Recommended Operating Conditions

DC Electrical Characteristics (Over Recommended Operating Conditions)

Max. 240 400 1 55 10 12 10 +/1 +/1

CJTAG CCLK CIO IIL

DS096 (v3.2) March 8, 2007 Product Specification

XC2C512 CoolRunner-II CPLD

LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications

LVCMOS 2.5V DC Voltage Specifications

0.7 0.4 0.2

LVCMOS 1.8V DC Voltage Specifications

LVCMOS 1.5V DC Voltage Specifications(1)

DS096 (v3.2) March 8, 2007 Product Specification

XC2C512 CoolRunner-II CPLD

Symbol VOH VOL

Parameter High level output voltage Low level output voltage

Min. VCCIO 0.45 VCCIO 0.2 -

Max. 0.4 0.2

Notes: 1. Hysteresis used on 1.5V inputs.

Schmitt Trigger Input DC Voltage Specifications

SSTL2-1 DC Voltage Specifications

SSTL3-1 DC Voltage Specifications

DS096 (v3.2) March 8, 2007 Product Specification

XC2C512 CoolRunner-II CPLD

HSTL1 DC Voltage Specifications

DS096 (v3.2) March 8, 2007 Product Specification

XC2C512 CoolRunner-II CPLD

AC Electrical Characteristics Over Recommended Operating Conditions

FSYSTEM1 FSYSTEM2 FEXT1

XC2C512 CoolRunner-II CPLD

Internal Timing Parameters(1)

Min. 1.4 0 1.3 0 -

TIN TDIN TGCK TGSR TGTS TOUT TEN

TCT TLOGI1 TLOGI2

TPDI TSUI THI TECSU TECHO TCOI TAOI TCDBL

TF TOEM THYS15 TOUT15 TSLEW15 THYS18 TOUT18 TSLEW18

I/O Standard Time Adder Delays 1.5V CMOS

I/O Standard Time Adder Delays 1.8V CMOS

DS096 (v3.2) March 8, 2007 Product Specification

XC2C512 CoolRunner-II CPLD

Internal Timing Parameters(1) (Continued)

I/O Standard Time Adder Delays 2.5V CMOS

I/O Standard Time Adder Delays 3.3V CMOS/TTL

I/O Standard Time Adder Delays HSTL, SSTL

Device Under Test R2 CL

R1 268 275 188 112.5 150

R2 235 275 188 112.5 150

CL 35 pF 35 pF 35pF 35pF 35pF

LVTTL33 LVCMOS33 LVCMOS25

Number of Outputs Switching

Figure 3: Load Circuit

Figure 2: Derating Curve for TPD