COSC3215

Serial Peripheral Interface SPI

Summary
Why SPI? SPI Features SPI Registers Example programs using SPI

SPI Concepts
Faster than SCI (high transfer rate) Synchronous transmission Common clock between sender and receiver (synchronous) Master/Slave mode: Master controls, slave responds Communication with simple peripherals and other microcontrollers

Master
MISO SPIF 8-Bit shift register
SPODR

Slave

MOSI

SPIF 8-Bit shift register

SPODR

SCK SS SS

VDD

Master provides the clock Full duplex (half duplex is also possible

SPI
The clock source is the P-clock divided by a userdefined constant. SPR[2:1:0] The SPIDR at the master, and the slave are configured as a 16-bit shift register. Each SCK clock cycle one bit is transmitted (one edge is used to send, the other is used to receive). Port S must be configured correctly (DDR) Baud rate must be set. Control registers SPICR1 and SPICR2 must be set

SPI
SS bit is properly set. (in a system containing one master and one slave, 1 for master, o for salve). The master component must be enabled, followed by the salve component. Transmission is initiated by writing the byte to SPIDR (if the master shift register is empty, the data is transmitted to the shift register and transmission starts). SPIF is set after the transmission is completed. Is the SS bit is under software control, it must be deasserted to stop transmission.

SPI
For the salve, the SPIF is set to indicate the data are received. An interrupt may be triggered if the transmission is complete

SPPR SPI Baud Rate Pre-selection Bits SPR SPI Baud Rate Selection Bits

BaudRateDivisor = ( SPPR + 1) 2

( SPR +1)

SPIE SPE SPTIE MSTR CPOL

Enables the SPI interrupts every time the SPIF flag is set SPI system Enable Bit (overall enable) SPI Transmit interrupt enable. It enables SPI interrupt generated each time the SPTEF flag is set SPI Master/Slave Moe selection bit SPI Clock Polarity bit SCK is active low/high idle low/high

CPHA SSOE LSBFE

SPI clock phase bit. The first SCK edge is issued at the beginning/one-half-cycle into the 8 cycle transmission Slave select output bit LSB-first enable 1=data is transmitted LSB first

MODFIN Module fault enable bit. Allows the MODF flag to be set. If master, and MODFEN bit is low, then SS is available as a general purpose I/O. If slave, SS is available only as an input regardless of the value of MODFEN BIDIROW SPISWAI SPC0 Output enable in the bi-directional mode. SPI stop in wait mode Serial pin control bit 0.

SPRF Receive interrupt flag. Is set after the 8th cycle and is cleared by reading the SPISR followed by a read to SPIDR SPTEF SPI transmit empty interrupt flag. Is set each time the transmit data register transfers a byte into the shift register. Generates an interrupt request if the SPTIE bit in SPICR1 is also set. Cleared by a write to SPIDR. MODF Mode fault flag. Is set if SS is low while the SPI is configured as a master

Do not write to the SPIDR unless the SPTEF bit is high

Configure port S Set baude rate

POLL SPI status

SPIF = 1 Configure SPICR1&2

Y
READ SPIDR

Clear SPIF

Enable

Assert SS

Write to SPIDR Poll SPI

SPIF = 1

Y
De-assert SS