EMAC

PCI66
HPI
TC0
TC1
CC Events
C64x+ DSP
SRIO
SCR
C64x+ memory
DDR2 EMIF
EMIF64
PCI66
McBSP
UTOPIA
CFG
XBAR
Masters Slaves
TCP
VCP
TC2
TC3















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DMA/QDMA
channel
logic
PaRAM
Transfer
request
submission
Completion
and error
interrupt
logic
EDMA3CC_INT[7:0]
EDMA3CC_MPINT
Completion
detection
To/from
EDMA3
programmer
Channel controller
TC0
Transfer
controllers
Read/write
commands
and data
EDMA3TC0_
ERRINT0
MMR
TC3 commands
Read/write
and data
MMR
EDMA3TC3_
ERRINT
EDMA3CC_ERRINT
access
access
EDMA3CC_INTG
Event
queues





























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Event
register
(ER/ERH)
Event
enable
register
(EER/EERH)
Event
set
register
(ESR/ESRH)
Chained
event
register
(CER/CERH)
QDMA
event
register
(QER)
64
64
64
6
4
:
1

p
r
i
o
r
i
t
y

e
n
c
o
d
e
r
4
:
1

p
r
i
o
r
i
t
y

e
n
c
o
d
e
r
4
Event queues
C
h
a
n
n
e
l

m
a
p
p
i
n
g
Queue bypass
Parameter
set 0
Parameter
set 1
set 255
Parameter
Parameter
set 254
T
r
a
n
s
f
e
r

r
e
q
u
e
s
t

p
r
o
c
e
s
s

s
u
b
m
i
t
PaRAM
E63 E0 E1
To
TC(S)
From
EDMA3TC0
From
EDMA3TC3
Completion
interface
Completion
detection
Event
trigger
Manual
trigger
Chain
trigger
Completion
interrupt detection
Error
EDMA3CC_INT[7:0]
EDMA3CC_INTG
From peripherals/external events
EDMA3CC_
ERRINT
QDMA trigger
Memory
protection
Read/
write to/
from CPU
EDMA3CC_
MPINT
To chained event register (CER/CERH)
0 15
EDMA3
channel
controller
E
a
r
l
y

c
o
m
p
l
e
t
i
o
n
Queue 0
0 15
Queue 1
0 15
Queue 2
0 15
Queue 3







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Read data
Write
command
Write data
Destination FIFO
register set
SRC
Transfer request
submission
EDMA3TCn
EDMA3TCn_ERRINT
To completion
detection logic
in EDMA3TC
Read
command
SRC active
register set
R
e
a
d
c
o
n
t
r
o
l
l
e
r
W
r
i
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e
c
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e
r
P
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g
r
a
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r
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g
i
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t
e
r

s
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t
























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31 14 13 5 4 0
00 0000 0000 0000 0000 00000 PAENTRY
00 0000 0000 0000 0000
31 13 14
PAENTRY
4 5 0 2 1
TR
WORD
00
DCHMAPn
QCHMAPn
Parameter set 0
Parameter set 1
Parameter set 3
Parameter set 2
Parameter set 255
Parameter set 254
Entry
#
Byte
address
4000h
4020h
4040h
4060h
5FC0h
5FE0h
0
1
2
3
254
255
DSTBIDX
BCNTRLD
Rsvd
DSTCIDX
CCNT
SRCCIDX
LINK
SRCBIDX
DST
BCNT ACNT
SRC
OPT
PaRAM PaRAM entry
+0h
+4h
+8h
+Ch
Byte
address
+1Ch
+18h
+14h
+10h
Array BCNT Array 2 Array 1 Frame 0
ACNT bytes in
Array/1st dimension
Array 1 Frame 1 Array BCNT Array 2
Array 1 Frame CCNT Array BCNT Array 2
CCNT frames in
Block/3rd dimmension
BCNT arrays in Frame/2nd dimmension




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1 3
5 7
13
9
15
11
ELEIDX
SRC
FRMIDX
15 13
FRMIDX
9
5
DST
1
11
7
3
ELEIDX
1 3
5 7
13
9
15
11
SRCBIDX
SRC
SRCCIDX
DSTCIDX
9
5
DST
1
11
7
3
DSTBIDX
























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Array 0 Array 1 Array 2 Array 3
Each array submit
as one TR
Array 0 Array 3 Array 1 Array 2
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Array 0 Array 3
(SRC|DST)
Array 1
BIDX BIDX
(SRC|DST)
Array 2
(SRC|DST)
CIDX
Frame 0
Frame 1
Frame 2
Array 0 Array 1 Array 2 Array 3
Each array submit
as one TR
Array 0 Array 3 Array 1 Array 2
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
(SRC|DST)
BIDX
Array 0 Array 3
(SRC|DST)
Array 1
BIDX BIDX
(SRC|DST)
Array 2
Frame 0
Frame 1
Frame 2
(SRC|DST)
CIDX
(SRC|DST)
CIDX
AB_Sync transfer












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All
Source
address
0_1
address
Destination
0_2 0_3 0_4 1_1 1_2 1_3
1_4 2_2 2_1 2_3 2_4






















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0_1
address
Source
0_2 0_3 0_4
1_1 1_2 1_3 1_4
2_2 2_1 2_3 2_4
EIX EIX EIX
FIX
FIX
2_1 2_4 2_3 2_2
FIX
FIX
1_1
Destination
address
0_1
EIX
1_4
0_4
1_3 1_2
0_3 0_2
EIX EIX






















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address
Destination
Source
address
0_1 0_2 0_3 0_4
1_1 1_2 1_3 1_4
2_2 2_1 2_3 2_4
AIX
AIX
0_1 0_2 0_3 0_4
1_1 1_2 1_3 1_4
2_2 2_1 2_3 2_4
AIX
AIX






















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1
0
First
event
Link
event event
Link Final link
event
Event in
queue queue
Event in Event in
queue
Event in
queue in TC
Event
in TC
Event Event
in TC in TC
Event
1
0
Static.OPT=0 Static.OPT=0 Static.OPT=0 Static.OPT=1
QER
QSER






























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