IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO.

5, OCTOBER 2002

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Natural Balancing of Three-Level Neutral-Point-Clamped PWM Inverters

H. du Toit Mouton, Member, IEEE

AbstractThis paper explores the natural balancing mechanisms of the three-level neutral-point-clamped (NPC) multilevel inverter. An equivalent circuit of the three-level NPC inverter is derived that facilitates an understanding of the balancing mechanisms. This is followed by a detailed analysis of the balancing mechanisms. The theory is applied to a three-level NPC inverter under vector control. It is shown that this inverter possesses natural balancing mechanisms in which the load impedance and spectra of the switching functions play an important role. Finally, it is illustrated how the natural balancing can be enhanced by using a passive balancing circuit which provides a low impedance at the sampling frequency. Index TermsNatural balancing, neutral-point voltage, threelevel inverter, vector modulation.

I. INTRODUCTION ULTILEVEL inverters are mainly applied in high-voltage and high-power applications. They offer the advantage of effectively stacking the switching devices in series, thereby providing a higher dc-bus voltage than can be obtained by conventional techniques. At the same time, the harmonic content of the output voltage waveform is significantly reduced compared to conventional two-level inverters. This comes at the expense of a number of added components like clamping diodes [1] or a number of flying capacitors [2]. Furthermore, to generate the large number of gating signals requires a more complicated controller. Another inherent problem with these inverters is possible unbalance of the capacitor voltages which may result in overvoltage of one or more of the switches. The neutral-point balancing problem of the three-level neutral-point-clamped (NPC) inverter has received a large amount of attention in recent years ([3][8]). A variety of different strategies has been introduced to solve this problem. These methods are based on adding a zero-sequence voltage component to the output voltage [6] or by manipulating the redundant switching vectors when applying vector control [8]. Some of these techniques also address the so-called short-pulse problem or minimizes the switching losses. Most of these methods have disadvantages in terms of the maximum usable modulation index or an increase in the inverter switching losses.

Two somewhat distinct problems associated with the neutralpoint voltage of the three-level NPC inverter can be identified as follows. 1) At high modulation indexes, a low-frequency ripple (at three times the fundamental frequency) occurs on the neutral-point voltage. Although balancing techniques can be used to reduce this voltage there are still limitations on the maximum amount of reduction. This problem appears to be inherent to the topology. 2) Steady-state unbalance in the neutral-point voltage may arise due to a variety of factors including component imperfections, transients and other nonidealities and imbalances. Although the dc-bus voltages are stable if the average center-point current is zero, this does not guarantee that the two dc-bus voltages are equal. This paper focuses on the second problem. In Section II, a general balancing theory is developed. It is proven that the three-level NPC inverter possesses natural balancing mechanisms. The effectiveness of these mechanisms is related to the modulation technique, harmonics of the switching functions, as well as the load impedance. The harmonics of the switching functions are studied in Section III. This theory is applied to a three-level NPC inverter under vector control, where the technique of alternative small vector selection is used. In Section IV. it is also shown how the balancing mechanisms can be enhanced by adding passive balancing circuits to the output of the inverter. In Section V, the theoretical results are verified through a number of simulations. II. BALANCING THEORY Fig. 1 shows the three-level NPC inverter. The load consists of a low-pass LC filter and a load resistor. The dc supply voltage is denoted by . In order to gain an understanding of the balancing mechanisms of the three-level NPC inverter, the following variable, which presents the unbalance in the dc-bus capacitor voltages, is introduced:

Let and
Manuscript received June 29, 2001; revised December 5, 2001. Abstract published on the Internet July 15, 2002. The author is with the Department of Electrical and Electronic Engineering, University of Stellenbosch, Stellenbosch, 7602 South Africa (e-mail: dtmouton@eng.sun.ac.za). Publisher Item Identifier 10.1109/TIE.2002.803205.

, , and represent the switching states of phases , , respectively. For instance, if if if and and and are closed are closed are closed.

0278-0046/02$17.00 2002 IEEE

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Fig. 1.

Three-level NPC inverter.

Fig. 2.

Equivalent circuit of the three-level NPC inverter.

Expressing , states results in

and

in terms of the , and switching

(1) Since , which is constant, it follows that

By considering the current flowing into the center point of the dc-bus capacitor bank it is easy to see that

(2) The next step in the analysis is to transform the three-phase plane. Let quantities to the

Fig. 3.

Switching vectors of the three-level NPC inverter.

where

By making use of the above definitions, it can be shown that (3) Furthermore, applying the transformation to (1) results in

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TABLE I SMALL, MEDIUM, AND LARGE SWITCHING VECTORS

Fig. 4. Regions of vector modulation of the NPC inverter in the first sector.

the voltage across it varies slowly and contains a relatively small ripple voltage, provides a large amount of insight into the balancing mechanisms on the three-level NPC inverter. In order to analyze the balancing mechanisms it is assumed that the dc component is large compared to its ripple component. is slow compared It is further assumed that the variation in to the dynamics of the rest of the system. Based on these considerations it is assumed throughout the following analysis that is a dc voltage and that the system is in the steady state. Let denote the impedance of the filter inductor in series with load resistor and filter capacitor, as shown in Fig. 2. Then, the following equations hold in the frequency domain: (4) (5) Since capacitor current is given by

in the time domain, it follows that

in the frequency domain. (Note that denotes convolution in the frequency domain.) By making use of (4) and (5), it follows that

Fig. 2 shows an equivalent circuit based on these two equations. This equivalent circuit provides an intuitive way of understanding the balancing mechanisms of the three-level NPC inverter. Each of the switching blocks of Fig. 2 can be thought of as a two-port switching circuit. An explanation of how these blocks are defined is given in the right top corner of Fig. 2. In general, this circuit can only be analyzed through simulation. A detailed analysis of a similar circuit applied to series-stacked multilevel inverters can be found in [9]. However, by studying is large in the sense that the case where the bus capacitance

By making use of the fact that the average value of is equal to 0 A in the steady state and applying the definition of convolution, it follows that

(6)

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Region A

Region B Fig. 5. Switching functions over two sampling periods.

Since

and

, it follows that (7)

where

A detailed study of these spectra under vector modulation is the subject of the next section. A variety of different modulation techniques, for instance closed-loop current regulation, are used in practical applications of the NPC converter. The theory developed above is general and applies to all these modulation strategies. III. SPECTRA
OF THE

SWITCHING FUNCTIONS UNDER VECTOR MODULATION

(Note that denotes the complex conjugate of .) This fundamental equation shows that the steady-state balancing of the capacitor voltages is influenced by the following two factors. 1) One factor is the impedance of the output filter and load. and . These 2) The other factor is the values of and are dependent on the way the spectra of as well as and overlap in the frequency domain. Orthogonality of these two sets of spectra would imply that the dc-bus voltages balance in the steady state.

Fig. 3 shows the 19 different switching vectors that can be produced by selecting the 27 different switching states of the inverter. The values of these vectors are given in Table I. The zero vector is associated with three different switching states. ), The other switching vectors are grouped into small ( ), and large ( ) vectors. By observing medium ( and are zero for the large switching vectors, it that both follows from (3) that the zero and large vectors do not influence the neutral point voltage. It is important to note that each small vector is associated with two different switching states. These two different vectors are

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Region C

Region D Fig. 5. (Continued.) Switching functions over two sampling periods.

referred to as positive and negative small vectors in [8]. Furand are of opposite sign for the thermore, the values of two different switching states associated with a particular small vector. This observation plays an important role in the natural balancing of three-level NPC inverter. Each medium vector is associated with only one switching state. The medium vectors are the major source of capacitor voltage ripple. It is the task of the modulator to synthesize the three line-to-line output voltages presented by the reference voltage vector

Only the case is considered in this paper and the shortpulse problem is not taken into account. Due to the circular symmetry only the sector for which is considered in detail. This sector can be subdivided into four smaller regions as shown in Fig. 4. The output voltage vector is synthesized by selecting those three vectors which are at each sampling instant. For closest to the reference vector

instance, in region vectors , and are used to synthesize the output voltage. The sum of these three vectors weighted by their duty cycles reproduces the reference vector. The sampling rate is fixed with denoting the sampling frequency. For the remainder of this paper, the technique of alternative small vector selection is applied. This means that, in regions and , switching pairs 100 and 110 are selected for the one sampling period, while 0-1-1 and 00-1 are selected for the next sampling instant. Similarly, switching pairs 100 and 0-1-1 are selected alternatively in region and 110 and 00-1 in region . The main advantage of this technique is that the waveforms of switching functions and repeat at the sampling frequency, and repeat at half the sampling frequency. while those of This results in orthogonality of the switching functions in the frequency domain, which is a requirement for natural balancing. Fig. 5 shows typical waveforms of switching functions , , , and over two sampling periods in regions , , and . A number of important observations can be made. 1) In all four regions, the fundamental component of occurs at half the sampling frequency. This is a result

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(a)

(b)

(c) Fig. 6. Switching functions over one fundamental cycle.

(d)

of the alternative small vector selection which increases the periods of these functions to two times the sampling period. 2) With the exception of region , the fundamental compoalso occur at half the sampling frequency. nents of is zero for both choices of the small vector Since this is not the case in region . and as well as 3) In region , the spectra and do not overlap. This implies excellent with relatively small balancing properties for region ripple on the dc-bus capacitor voltages. Although the and as well as and spectra of do overlap in regions , , and , the effect of this overlap disappears when the switching functions are calculated over a full fundamental cycle of the voltage reference. 4) From Fig. 2, it is now easy to see that as long as the dc-bus ) voltages capacitor voltages are unbalanced ( and will contain components at half the sampling frequency associated with . The only exception is region where the -component is absent.

Fig. 6(a) and (b) shows switching functions , , , and in the time domain over one fundamental cycle as well as in the frequency domain. The reference waveform is sinusoidal and the sampling frewith a frequency of 50 Hz and and , quency is 6 kHz. Fig. 6(c) and (d) shows is small compared to , (7) respectively. Since shows that the dc-bus voltages of the NPC inverter are balanced in the steady state. However, it will later be shown that this balance can easily be disturbed by introducing harmonics into the reference waveform. is only It should be noted that, although shown for a special case, this fact has been verified through a number of simulations. A formal mathematical proof of this fact is currently being developed. IV. ENHANCING THE BALANCING MECHANISMS As was noted in Section II, the balancing properties of the NPC inverter are determined by the overlap of the frequencydomain representations of the switching functions as well as the load impedance. As was shown in the previous section, the

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(a) Fig. 7.

(b)

Equivalent circuit of the three-level NPC inverter with balancing circuit. (a) Load with balancing circuit. (b) Equivalent circuit. TABLE II SIMULATION PARAMETERS

largest component of occurs in the neighborhood of half is small in the neighthe sampling frequency , while . Based on these observations, it follows from borhood of (7) that the balancing mechanisms of the NPC inverter can be . This can enhanced by decreasing the load impedance at be achieved by adding a passive balance booster consisting of in series with a capacitor to each phase of the an inductor load as shown in Fig. 7. Current will only flow in the balance booster when the two dc-bus voltages are unbalanced. Similar balancing circuits have been applied to flying-capacitor multilevel inverters. This circuit acts as a bandpass filter providing a low impedance at half the sampling frequency. In an experimental evaluation of the balancing mechanisms it was found that the typical VA rating of the balance booster is small, approximately 5% of the total VA rating of the converter. Intuitively, the balance booster provides a low-impedance and associated with . In this path for harmonics of is suppressed, forcing the dc-bus capacitor voltages to way, balance. When optimizing the balance booster, the following two requirements must be achieved. 1) The circuit must provide a low impedance at half the sampling frequency. It should also provide a low impedance . at the sidebands associated with the harmonic at 2) In order to reduce the rating of the balancing circuit, it should provide a high impedance at the fundamental frequency as well as at the sampling frequency and above. and capacitor would In practical systems, inductor have nonzero equivalent series resistance. If an unbalance condition does occur in the dc-bus capacitor voltages, this resistance would provide damping for the energy resonating between the dc-bus capacitors and the balance booster. The energy dissipated in the balance booster is small compared with the losses associated with passive resistive balancing of the dc-bus capacitor voltages. This is a result of the fact that only part of the energy associated with unbalanced capacitor voltages will be dissipated in the balance booster. The balance booster essentially swings energy from one capacitor to the other. With passive resistive balancing, significant losses occur, even when no voltage un-

balance is present. Active resistive balancing is also possible, but this requires additional switches and resistors. In order to further enhance the balancing properties, it is possible to use more than one balancing circuit, tuned at the other . This possibility will, however, not be furharmonics of ther investigated in this paper. V. SIMULATION RESULTS In this section, a number of simulation results are presented to confirm and illustrate the theory. Table II gives the simulaand are set to 500 tion parameters. The initial values of and 300 V, respectively. All four simulations are done with and without the balancing circuit. To illustrate the fact that the balancing of the three-level NPC inverter is highly dependent on the load impedance, the load is replaced by three 50-Hz sinusoidal current sources forming a positive-sequence system with an amplitude of 30 A, in the first simulation. As can be seen in Fig. 8(a), the capacitor voltages do not oscillates near 200 V indefinitely. This is rebalance and due to the fact that the current-source load presents an infinite

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(a)

(b)

(c) Fig. 8.

(d)

Simulation results. (a) Current-source load. (b) Practical load. (c) Unequal switching behavior. (d) Reference contains a harmonic at 150 Hz.

impedance. In the second part of the simulation, the balancing circuit is added, resulting in the rapid convergence of to 0 V. In the second simulation, shown in Fig. 8(b), the current sources of the previous simulation are removed and the load is as specified in Table II. In this case, natural balancing of the two dc-bus capacitor voltages occurs. It can also be seen that the balancing circuit significantly increases the rate of rebalancing. The time constant associated with the rebalancing of the dc-bus voltages is 0.4 s without the balance booster and 0.015 s with the balance booster. This is equivalent to connecting two balancing resistors of 160 (without the balance booster) and 6 (with the balance booster) in parallel with the two dc-bus capacitors. In the third simulation, the effect of unequal switching behavior of the inverters switches is studied. This is achieved by of the inintroducing a 5- s delay in the turn-on of switch verter. This essentially introduces a high-frequency component into the switching functions that results in an overlap in the spectra of the switching functions, giving rise to steady-state unbalance. The results of the simulation are shown in Fig. 8(c). settles Without the balancing circuit, the average value of

around 40 V, while the balancing circuit reduces this to approximately 5 V. In the final simulation, a third-order harmonic is added to the is a square wave that varies reference voltage. In this case, between 0.50.7 with a frequency of 150 Hz. The resulting dican be seen in Fig. 8(d). Again, the balancing vergence of circuit significantly improves the balancing properties. VI. CONCLUSIONS This paper has presented a systematic study of the neutral-point voltage balancing problem of the three-level NPC inverter. As a first step, the circuit was transformed to and parameters and an equivalent circuit was derived that results in an intuitive way of approaching the balancing problem. It was shown that the inverter possesses natural balancing mechanisms that are dependent on the modulation strategy and the load impedance. As an application of the basic theoretical model, the balancing of the three-level NPC inverter under vector modulation was studied. It was shown that the technique of alternative small

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vector selection results in natural balancing of the dc-bus capacitor voltages. The balancing mechanisms can be enhanced by adding a small passive balancing circuit to the load. This circuit provides a low-impedance path for harmonics at half the sampling frequency. In the final part of the paper the theory was verified and illuminated through a number of simulation results. It was shown that a number of conditions, including the effect of unequal switching behavior and harmonics of the voltage reference, can result in steady-state unbalance. In all the cases that were studied, the balancing circuit significantly improved the balancing mechanisms. The techniques discussed in this paper can also be adapted to study the transient behavior of the NPC converter. This is the subject of future research. REFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped PWM inverter, IEEE Trans. Ind. Applicat., vol. IA-17, pp. 518523, Sept./Oct. 1981. [2] T. A. Meynard and H. Foch, Multi-level conversion: High voltage choppers and voltage-source inverters, in Proc. IEEE PESC92, Toledo, Spain, June 1992, pp. 397403. [3] H. L. Liu, N. S. Choi, and G. H. Cho, DSP based space vector PWM for three-level inverter with DC-link voltage balancing, in Proc. IEEE IECON91, vol. 1, 1991, pp. 197203. [4] H. L. Lui and G. H. Cho, Three-level space vector PWM in low index modulation region avoiding narrow pulse problems, IEEE Trans. Power Electron., vol. 9, pp. 481486, Sept. 1994.

[5] J. Zhang, High performance control of a three-level IGBT inverter fed AC drive, in Conf. Rec. IEEE-IAS Annu. Meeting, vol. 1, 1995, pp. 2228. [6] S. Ogasawara and H. Akagi, Analysis of variation of neutral point potential in neutral-point-clamped voltage source PWM inverters, in Conf. Rec. IEEE-IAS Annu. Meeting, 1993, pp. 965970. [7] Y. H. Lee, B. S. Suh, and D. S. Hyun, A novel PWM scheme for a three-level voltage source inverter with GTO thyristor, IEEE Trans. Ind. Applicat., vol. 32, pp. 260268, Mar./Apr. 1996. [8] N. C. Celanovic and D. Boroyevich, A comprehensive study of the neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters, IEEE Trans. Power Electron., vol. 15, pp. 242249, Mar. 2000. [9] H. du T. Mouton, J. H. R. Enslin, and H. Akagi, Balancing theory of series-stacked power quality conditioners, in Proc. IEEE PESC, 2001, pp. 15771582.

H. du Toit Mouton (S98M00) was born in Bloemfontein, South Africa, in 1965. He received the B.Sc., B.Sc. (Hons), M.Sc., and Ph.D. degrees in mathematics from the University of the Free-State, Bloemfontein, South Africa, in 1986, 1987, 1988, and 1991, respectively, and the B.Eng. degree and the Ph.D. degree in electrical engineering from the University of Stellenbosch, Stellenbosch, South Africa, in 1996 and 2000, respectively. He is currently an Associate Professor of Electrical Engineering at the University of Stellenbosch and the Leader of the Power Electronics Research Group.