An Overview to Cmos based Digital to Analog Converter

Enrique Rivas, Carlos Zorrilla Universidad Politcnica de Cartagena Cartagena, Spain

Abstract- A digital to analog converter is a semiconductor device that is used to convert a digital code into an analog signal. These devices have plenty uses due the importance to translate digital data from computer based device to signal for be uses in audio, video, mechanical move, etc. there are several types of architecture, each one with advantages and disadvantages. I. INTRODUCCION A digital-to-analog converter, or simply DAC, is a semiconductor device that is used to convert a digital code into an analog signal. Digital-toanalog conversion is the primary means by which digital equipment such as computerbased systems are able to translate digital data into real-world signals that are more understandable to or useable by humans, such as music, speech, pictures, video, and the like. It also allows digital control of machines, equipment, household appliances, and the like. [1]

Figure 1 A simple DAC may be implemented using an op-amp circuit known as a summer, so named because its output voltage is the sum of its input voltages. Each of its inputs uses a resistor of different binary weight, such that if R0=R, then R1=R/2, R2=R/4, R3=R/8,.., RN-1=R/(2N-1). The output of a summer circuit with N bits is: Vo = -VR (Rf / R) (SN-12N-1 + SN-22N-2+...+S020) where VR is the voltage to which the bit is connected when the digital input is '1'. A digital input is '0' if the bit is connected to 0V (ground). A 4-bit summer circuit is shown in Figure 1.

A typical digital-to-analog converter outputs an analog signal, which is usually voltage or current, that is proportional to the value of the digital code provided to its inputs. Most DAC's have several digital input pins to receive all the bits of its input digital code in parallel (Figure 1). Some DAC's, however, are designed to receive the input digital data in serial form (one bit at a time), so these only have a single digital input pin.

Figure 2

One problem with this circuit is the wide range of resistor values needed to build a DAC with a high number of digital inputs. Putting thin-film resistors that come in a wide range of values (e.g., from a few ks to several Ms) on a

single semiconductor chip can be very difficult, especially if high accuracy and stability are required. [2] A better-designed and more commonly-used circuit for digital-to-analog conversion is known as the R-2R ladder DAC, a 4-bit version of which is shown in Fig. 2. It consists of a network of resistors with only two values, R and 2R. The input SN to bit N is '1' if it is connected to a voltage VR and '0' if it is grounded. Thevenin's Theorem may be applied to prove that the output Vo of an R-2R ladder DAC with N bits is: Vo = VR/2N (SN-12N-1 + SN-22N-2+...+S020). Thus, the output of the R-2R ladder in Figure 2 is Vo = VR/24 (S323+S222+S121+S020) or Vo = VR (S3 / 2 + S2 / 4 + S1 / 8 + S0 / 16) . In effect, contribution of each bit to the analog output is proportional to its binary weight.

digital output of a compatible CD player or dedicated transport (which is basically a CD player with no internal DAC) and convert the signal into an analog line-level output that can then be fed into an amplifier to drive speakers. Similar digital-to-analog converters can be found in digital speakers such as USB speakers, and in sound cards. In VoIP (Voice over IP) applications, the source must first be digitized for transmission, so it undergoes conversion via an Analog-to-Digital Converter, and is then reconstructed into analog using a DAC on the receiving party's end. B. Video

Figure 3

II. A. Audio

APPLICATIONS

Most modern audio signals are stored in digital form (for example MP3s and CDs) and in order to be heard through speakers they must be converted into an analog signal. DACs are therefore found in CD players, digital music players, and PC sound cards. Specialist standalone DACs can also be found in high-end hi-fi systems. These normally take the

Video sampling tends to work on a completely different scale altogether thanks to the highly nonlinear response both of cathode ray tubes (for which the vast majority of digital video foundation work was targeted) and the human eye, using a "gamma curve" to provide an appearance of evenly distributed brightness steps across the display's full dynamic range hence the need to use RAMDACs in computer video applications with deep enough colour resolution to make engineering a hardcoded value into the DAC for each output level of each channel impractical (e.g. an Atari ST or Sega Genesis would require 24 such values; a 24-bit video card would need 768...). Given this inherent distortion, it is not unusual for a television or video projector to truthfully claim a linear contrast ratio (difference between darkest and brightest output levels) of 1000:1 or greater, equivalent to 10 bits of audio precision even though it may only accept signals with 8-bit precision and use an LCD panel that only represents 6 or 7 bits per channel. Video signals from a digital source, such as a computer, must be converted to analog form if they are to be displayed on an analog monitor. As of 2007, analog inputs were more commonly used than digital, but this changed as flat panel displays with DVI and/or HDMI connections

became more widespread. A video DAC is, however, incorporated in any digital video player with analog outputs. The DAC is usually integrated with some memory (RAM), which contains conversion tables for gamma correction, contrast and brightness, to make a device called a RAMDAC. A device that is distantly related to the DAC is the digitally controlled potentiometer, used to control an analog signal digitally. C. Mechanical B. Oversampling

Figure 4

An unusual application of digital-to-analog conversion was the whiffletree electromechanical digital-to-analog converter linkage in the IBM Selectric typewrite

III.

DAC TYPES

The most common types of electronic DACs are [1]: A. pulse-width modulator

Oversampling DACs or interpolating DACs such as the delta-sigma DAC, use a pulse density conversion technique. The oversampling technique allows for the use of a lower resolution DAC internally. A simple 1-bit DAC is often chosen because the oversampled result is inherently linear. The DAC is driven with a pulse-density modulated signal, created with the use of a low-pass filter, step nonlinearity (the actual 1-bit DAC), and negative feedback loop, in a technique called delta-sigma modulation. This results in an effective high-pass filter acting on the quantization (signal processing) noise, thus steering this noise out of the low frequencies of interest into the megahertz frequencies of little interest, which is called noise shaping. The quantization noise at these high frequencies is removed or greatly attenuated by use of an analog low-pass filter at the output (sometimes a simple RC low-pass circuit is sufficient). Most very high resolution DACs (greater than 16 bits) are of this type due to its high linearity and low cost. Higher oversampling rates can relax the specifications of the output low-pass filter and enable further suppression of quantization noise. Speeds of greater than 100 thousand samples per second (for example, 192 kHz) and resolutions of 24 bits are attainable with delta-sigma DACs. A

The pulse-width modulator, the simplest DAC type. A stable current or voltage is switched into a low-pass analog filter with a duration determined by the digital input code. This technique is often used for electric motor speed control, but has many other applications as well. The overall scheme in which the core conversion process is pulse width modulation (PWM) is shown in Fig. 4. This Figure also shows the additional components needed to turn the PWM DAC into a power amplifier. The digital input is first processed by a n 'oversampling filter', which effectively increases the sampling rate (for example from 44.1 kHz to 325.8 kHz). The primary purpose of this stage is to help reduce distortion. The 'cross-point detector' is a lineariser which improves the distortion performance of the system. [1]

short comparison with pulse-width modulation shows that a 1-bit DAC with a simple first-order integrator would have to run at 3 THz (which is physically unrealizable) to achieve 24 meaningful bits of resolution, requiring a higher-order lowpass filter in the noise-shaping loop. A single integrator is a low-pass filter with a frequency response inversely proportional to frequency and using one such integrator in the noise-shaping loop is a first order delta-sigma modulator. Multiple higher order topologies (such as MASH) are used to achieve higher degrees of noise-shaping with a stable topology. C. binary-weighted

perform slowly due to increasingly large RCconstants for each added R-2R link. E. The thermometer-coded

The thermometer-coded DAC, which contains an equal resistor or current-source segment for each possible value of DAC output. An 8-bit thermometer DAC would have 255 segments, and a 16-bit thermometer DAC would have 65,535 segments. This is perhaps the fastest and highest precision DAC architecture but at the expense of high cost. Conversion speeds of >1 billion samples per second have been reached with this type of DAC. F. Hybrid

The binary-weighted DAC, which contains individual electrical components for each bit of the DAC connected to a summing point. These precise voltages or currents sum to the correct output value. This is one of the fastest conversion methods but suffers from poor accuracy because of the high precision required for each individual voltage or current. Such high-precision components are expensive, so this type of converter is usually limited to 8-bit resolution or less. The binary weighted DAC is the simplest in the family of current steering architectures. In this architecture each current source has a value of twice of the previous current source. Current switches are directly controlled by the binary input bit patterns. The stringent matching requirement of the different current sources generally restricts the resolution

Hybrid DACs, which use a combination of the above techniques in a single converter. Most DAC integrated circuits are of this type due to the difficulty of getting low cost, high speed and high precision in one device. The segmented DAC, which combines the thermometer-coded principle for the most significant bits and the binary-weighted principle for the least significant bits. In this way, a compromise is obtained between precision (by the use of the thermometer-coded principle) and number of resistors or current sources (by the use of the binary-weighted principle). The full binary-weighted design means 0% segmentation, the full thermometercoded design means 100% segmentation. G. multiplying DAC

D.

R-2R ladder

The R-2R ladder DAC which is a binaryweighted DAC that uses a repeating cascaded structure of resistor values R and 2R. This improves the precision due to the relative ease of producing equal valued-matched resistors (or current sources). However, wide converters

Most DACs, shown earlier in this list, rely on a constant reference voltage to create their output value. Alternatively, a multiplying DAC takes a variable input voltage for their conversion. This puts additional design constraints on the bandwidth of the conversion circuit.

IV. EXAMPLES OF IMPLEMENTATION Next lets see some examples of DAC desing using different of the architecture shown before: A. Low-Voltage 10-Bit CMOS DAC in 0.01mm2 Die Area [3] A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18- m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 m 94 m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area.

The user desires the DAC to effectively act as an ideal, adjustable current source or sink. In order for the current source/sink to be effective, it should take up as little percentage of the power supply as possible. In order to achieve an output current that takes up minimum headroom, this DAC uses the linear current mirror stage shown in Fig. 6. The opamps shown in Fig. 6 (A1A4) are the critical blocks in the mirroring operation. Using opamps with high dc gain, nodes A-D are effectively held at V regardless of the current passing through devices M1M4. Since the gates of M1 and M2 are tied together, and the drains are each servoed to the same voltage, the current produced in M1 will be replicated in M2.

A segmented R-2R ladder architecture implementation achieves the highest area efciency in the design of the 10 b CMOS current-steering DAC for dc operation. Fig. 5 shows an overview of the segmented DAC architecture. The single-ended CMOS logic input digital word is received and latched before being passed on to the switches.

Figure 6

B. A 113dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling [4] a technique called segmented scrambling is used, in which the 6b word is split into two smaller sub-words that are each individually noise-shaped. These two smaller words are then individually scrambled and applied to two separate DACs. Figure 5

Figure 7 shows the segmented scrambling technique. A 2nd-order digital modulator with a 6b output is applied to a simple lSt-order digital modulator of conventional design that reduces the 6b wordlength to 4b. This 4b signal 'B'is subtracted from the original 6b signal 'A' (with MSBs aligned) to produce a 3b signal 'C'. The signal 'B' is then thermometer encoded and applied through an oise-shaped scrambler to a 16-level DAG with weight K, and signal 'C' is likewise applied to an 8-level DAG with weight W4. The sum of B and C must equal the original signal A, as the signal C was derived by subtracting B from A. Since each of the signals B and C pass through a noise-shaped scrambler circuit, any errors within each DAC result in shaped noise. Now consider what happens if the gain of DAC B does not match the gain of DAC C. Since signal C contains only shaped noise, the result of a gain mismatch must also be a noise-shaped signal that contributes little energy to the in band spectrum.

Figure 8

C. A 30 GS/s 4-Bit Binary Weighted DAC in SiGe BiCMOS Technology [5] Next is shown a 4-bit 30GS/s binary weighted DAC in 0.25 m BiCMOS technology. The binary weighting function was implemented in the load resistor instead of the current sources. This DAC showed 0.49 LSB and 0.57 LSB of INL and DNL respectively. 0.92pJ FOM was achieved with 3.5V of power supply at a conversion rate of 30GHz. This DAC can also be used as a sub-DAC for implementing the LSB part of a segmented 8-bit current steering DAC with 20GS/s or more sampling rate.

Figure 7 a dual return to zero scheme is shown in the figure 8, this scheme is designed to overcome problems with jitter sensitivity and linearity in the output stage.

In the present application a binary weighted architecture is chosen as the resolution is only 4 bits. Secondly it allows to combine this DAC with a 4-bit unary weighted DAC to enhance the resolution up to 8-bits. The block diagram of the presented DAC is shown in Fig. 9. Unlike the common binary weighted DAC, all of the current sources in this work have same current.

nMOS transistor is used as the main current source and the cascade device is an HBT transistor.

Figure 9

The DAC is implemented in a 0.25m SiGe BiCMOS technology [8]. The minimum emitter size of the HBT is 0.21x0.84 m2 and the fT, fMAX are both 190GHz. This technology also provides poly resistors and MIM capacitors in a five-layer metallization system. In the time critical signal paths, minimum size HBTs have been used for high speed and minimum parasitic capacitance load. The main improvement in the proposed DAC lies in the high-speed design based on the resistive load network. All of the four current switches have the same low resistive load at the output node.

Fig. 11 shows the schematic of one branch of the output load for the DAC. The load is directly matched with the 50 output. Additional resistors are used to equalize the resistive load at the input of each current switch. Unlike the conventional binary weighted DAC, this new approach allows to operate all of the current sources with the same current and load impedance.

Figure 11

V. CONCLUTION As we have seen in this article, Digital to Analog Converter have plenty uses in several technology, as so we have several types of DACs architecture based on Cmos, each one with their advantage and disadvantage. On the other hand, there are many ways and research in progress efficient ways for the implementation of DACs in microchips. Figure 10 REFERENCES Schematic diagrams of the novel current switch concept used in this work are presented in Fig. 10. A simple differential pair is used as the current switch. The current source is implemented by a cascade stage. An isolated [1] i. Analog Devices, Data Conversion Handbook, Analog Devices, inc, 2005. [2] i. Analog Devices, "Multiplying DACs". [3] M. Sandler, "Digital to analogue conversion using pulse width modulation,"

ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL, 1993. [4] B. Greenley, R. Veith and D.-Y. Chang, "A Low-Voltage 10-Bit CMOS DAC in 0.01-mm2 Die Area," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 2005. [5] K. Nguyen and R. Adams, "A 113dB SNR Oversampling DAC with Segmented NoiseShaped Scrambling," in IEEE International Solid-State Circuits Conference, 1998. [6] S. Halder and H. Gustat, "A 30 GS/s 4-Bit Binary Weighted DAC in SiGe BiCMOS Thecnology," in Bipolar/BiCMOS Circuits and Technology Meeting, 2007.