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CSEE 3827: Fundamentals of Computer Systems, Spring 2011 9.

Single Cycle MIPS Processor

Web: http://www.cs.columbia.edu/~martha/courses/3827/sp11/

Prof. Martha Kim (martha@cs.columbia.edu)

Outline (H&H 7.2-7.3)


Single Cycle MIPS Processor Datapath (functional blocks) Control (control signals) Single Cycle Performance

Microarchitecture
Microarchitecture: an implementation of a particular architecture Multiple implementations for a single architecture Single-cycle: Each instruction executes in a single cycle Multi-cycle: Each instruction is broken up into a series of shorter steps Pipelined: Each instruction is broken up into a series of steps; Multiple instructions execute at once

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Our MIPS Processor


We consider a subset of MIPS instructions: R-type instructions: and, or, add, sub, slt Memory instructions: lw, sw Branch instructions: beq Later consider adding addi and j

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Instruction Execution
PC instruction memory, fetch instruction Register numbers register le, read registers Depending on instruction class: Use ALU to calculate: Arithmetic or logical result Memory address for load/store Branch target address Access data for load/store PC target address or PC + 4

MIPS State Elements


Architectural state determines everything about a processor: PC, 32 registers, memory

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Single-Cycle Datapath: lw fetch


First consider executing lw STEP 1: Fetch instruction

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Single-Cycle Datapath: lw register read


STEP 2: Read source operands from register le

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Single-Cycle Datapath: lw immediate


STEP 3: Sign-extend the immediate

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Single-Cycle Datapath: lw address


STEP 4: Compute the memory address

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Single-Cycle Datapath: lw memory read


STEP 5: Read data from memory and write it back to register le

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Single-Cycle Datapath: lw PC increment


STEP 6: Determine the address of the next instruction

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Single-Cycle Datapath: sw
Write data in rt to memory

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Single-Cycle Datapath: R-type instructions


Read from rs and rt Write ALUResult to register le Write to rd (instead of rt)

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Single-Cycle Datapath: beq


Determine whether values in rs and rt are equal Calculate branch target address: BTA = (sign-extended immediate)x4 + (PC+4)

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Complete Single-Cycle Processor

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Control Unit

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ALU Interface and Implementation


F2:0
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Function
A&B A|B A+B
not used

A & ~B A | ~B A-B SLT

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Control Unit: ALU Decoder


ALUOp1:0 0 0 1 1 0 1 0 1

Meaning Add Subtract Look at Funct


not used

ALUOp1:0 0 0 x 1 1 x 1 x 1 x 1 x 1 x
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Funct x x 100000 (add) 100010 (sub) 100100 (and) 100101 (or) 101010 (slt)

ALUControl2:0 010 (Add) 110 (Subtract) 010 (Add) 110 (Subtract) 000 (And) 001 (Or) 111 (SLT)
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Control Unit: Main Decoder


Instruction R-type Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemToReg ALUOp1:0

000000 100011 101011 000100

lw sw beq

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Single-Cycle Datapath Example: or

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Extended Functionality: addi


No change to datapath

Instruction R-type

Op5:0

RegWrite RegDst AluSrc Branch MemWrite MemToReg ALUOp1:0

lw sw beq addi

000000 100011 101011 000100 001000

1 1 0 0 1

1 0 x x 0

0 1 1 0 1

0 0 0 1 0

0 0 1 0 0

0 1 x x 0

1 0 0 0 0

0 0 0 1 0
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Extended Functionality: j

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Control Unit: Main Decoder with j


Instruction Op
5:0

RegWrite

RegDst

AluSrc

Branch

MemWrite

MemToReg

ALUOp

1:0

Jump

R-type

000000 100011 101011 000100 001000 000010

1 1 0 0 1 0

1 0 x x 0 x

0 1 1 0 1 x

0 0 0 1 0 x

0 0 1 0 0 0

0 1 x x 0 x

1 0 0 0 0 0 0 1 0 0 x x

0 0 0 0 0 1

lw sw beq addi j

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Review: Processor Performance

Seconds Instructions Clock cycles Seconds = x x Program Program Instruction Clock cycle

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Single-Cycle Performance
Seconds/cycle (or TC) is limited by the critical path (lw)

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Single-Cycle Performance
Single-cycle critical path:

Tc = tpcq_PC + tmem + max(tRFread, tsext + tmux) + tALU + tmem + tmux + tRFsetup


In most implementations, limiting paths are: memory, ALU, register le

Tc = tpcq_PC + 2tmem + tRFread + tmux + tALU + tRFsetup

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Single-Cycle Performance Example


Element
Register clock-to-Q Register setup

Parameter

Delay (ps) 30 20 25 200 250 150 20

Multiplexer ALU Memory read Register le read Register le setup

tpcq_PC tsetup tmux tALU tmem tRFread tRFsetup

Tc = tpcq_PC + 2tmem + tRFread + tmux + tALU + tRFsetup = [30 + 2(250) + 150 + 25 + 200 + 20] ps = 925 ps
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Single-Cycle Performance Example


For a program with 100 billion instructions executing on a single-cycle MIPS processor, Execution Time = # instructions x CPI x TC = (100 109)(1)(925 10-12 s) = 92.5 seconds

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