FPGA IMPLEMENTATION OF FIR FILTER STRUCTURES

By G. Aruna Sukeerthi (M.Tech - C&C) Regd. No: 08021D3627

Under the Guidance of Sri K.BABULU, Associate Professor in ECE, JNTU CE, Kakinada

AIM
This Project work mainly concentrates on Design and FPGA implementation of FIR filter structures. Design Entry Simulation Synthesis FPGA Target Device -VHDL Language -ModelSim XE III 6.2g -Xilinx Synthesis Tool -Spartan3E:XC3S500E

INTRODUCTION
Choices of implementing a DSP application (FIR Filter) Using a dedicated DSP processor

Using a hardware approach FPGA ASIC

FIR FILTER
An FIR filter is usually implemented by using a series of delays, multipliers, and adders to create the filter's output.

The logical structure of an FIR filter

PROBLEMS IN DESIGNING FIR FILTER

Excessive area
Power consumption

FIR FILTER DESIGN WITH FDA TOOL

6-tap FIR Filter Structures are designed with constant and fixed coefficients. Filter specifications Sampling Frequency Fs = 50 KHz Pass Band Edge Frequency = 15 KHz Stop Band Edge frequency = 18 KHz

FIR FILTER STRUCTURES

Direct form FIR filter Transposed form FIR filter

Symmetric form FIR filter

Distributed arithmetic FIR filter

MODULES IN FIR FILTER STRUCTURES

Adder/ Subtractor Multiplier Parallel In Parallel Out shift register LUT Accumulator

DIRECT FORM FIR FILTER - BLOCK DIAGRAM

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y(n)

TRANSPOSED FORM FIR FILTER - BLOCK DIAGRAM

X[n]
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h(6)

h(5)

h(4)

h(3)

h(2)

h(1)

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Z-1

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Z-1
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Y[n]

SYMMETRIC FORM FIR FILTER - BLOCK DIAGRAM

DISTRIBUTED ARITHMETIC FIR FILTER - BLOCK DIAGRAM

SIMULATION RESULTS
Impulse Response

SIGNAL DESCRIPTION
Input Signals : rst, clk,x (15 downto 0) Output Signal : count, y (15 downto 0) Logic: Whenever the rst is set to 1 the register will reset i.e.; all the bits are set to 0. When rst=0 normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. Here, Count is an intermediate signal that counts the number of clock cycles. When the count reaches the value 6 that indicates input sequence is entirely processed till the last stage. The output response of a filter for an impulse is nothing but the sequence of filter coefficients.

Contd
Step Response

Contd..
Input Signals : rst, clk,x (15 downto 0) Output Signal : y (15 downto 0) Logic: Whenever the rst is set to 1 the register will reset i.e.; all the bits are set to 0. When rst=0 normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. The input x is a step signal hence it is shown as a sequence of bits for which a few bits are 0s at the start and next all 1s. The output response of a filter for a step is nothing but the cumulative sum of fir filter coefficients processed.

Contd
Low frequency Sine wave

Contd..
Input Signals : rst, clk,x (15 downto 0) Output Signal : y (15 downto 0) Logic: Whenever the rst is set to 1 the register will reset i.e.; all the bits are set to 0. When rst=0 normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. For the sine wave signal at the input, the filter gives the output same as input signal without any attenuation as this is a low pass filter.

Contd
Low frequency sine wave with added noise

Contd..
Input Signals : rst, clk,x (15 downto 0) Output Signal : y (15 downto 0) Logic: Whenever the rst is set to 1 the register will reset i.e.; all the bits are set to 0. When rst=0 normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. The noise added sine wave gives the response as the sine wave with reduction in noise to some extent at the output. As this is a low pass filter high frequency components are attenuated to some extent.

SYNTHESIS REPORT ANALYSIS -COMPARISON OF FIR FILTER STRUCTURES

FIR Structures Number of arithmetic operation Addition s Direct Structure 5 Multiplicatio ns 6 Critical path delay (ns) 6.669 FPGA area (number of slices) 257

Transpose d Structure
Symmetric structure Distribute d Arithmetic Structure

6.047

95

5 5 shift & Add operatio ns

3 0

1.967 6.290

95 39

DIRECT FORM FIR FILTER - RTL VIEW

TRANSPOSED FORM FIR FILTER - RTL VIEW

SYMMETRIC FORM FIR FILTER - RTL VIEW

DISTRIBUTED ARITHMETIC FIR FILTER RTL VIEW

FLOOR PLANNING

ROUTING ANALYSIS

CHIP VIEW

PROTOTYPING ON FPGA
FIR filter architectures are implemented on Spartan3E FPGA device by incorporating ChipScope modules into design. The implemented filter structure is tested for validation by the following test cases. Impulse response Step response Low frequency sine wave Low frequency sine wave with riding high frequency noise on it

ChipScope Pro Analyser Results

Impulse Response

Contd
Step response

Contd
Input : Low Frequency Sine Wave

Output

Contd
Input : Low freq sine plus high frequency noise

Output

APPLICATIONS
FPGA based digital signal processing algorithms Digital front end receiver for filtering the high frequency components in digital Several other places where FIR filter is required.

CONCLUSION
Different FIR filter architectures have been introduced and the sub modules involved for all the architectures have been discussed clearly. Simulation for all the FIR filter architectures has been carried out and the outputs have been clearly discussed by considering four different input formats. Synthesis has been performed for all the FIR filter structures. All the FIR filter architectures have been successfully implemented on Spartan 3E FPGA device.

FUTURE SCOPE
The implemented FIR structures at code level can be modified to make full benefit from the FPGA, such as using fast carry chains, Embedded Array Blocks etc. To achieve the peak performance fully parallel pipelined version can be implemented In the present work the DA based FIR filter is implemented with one LUT and without pipelining. This can be extended to full parallel implementation with more than one LUTs for high speed applications. The following figure shows a possible architecture.

BIBLIOGRAPHY

Simon Haykin, Communication Systems, Fourth Edition, John Wiley & Sons, Inc. J. Bhaskar, A VHDL Premier, Third Edition, Pearson Education Asia. 5. Volnei A. Pedroni, Circuit design with VHDL. Digital Signal Processing with Field Programmable Gate Arrays, by U. Meyer-Baese, Springer Publications. Practical FIR Filter Design in MATLAB, Revision 1.1, Ricardo A. Losada The MathWorks, Inc. Essentials of electronic testing for digital, memory and mixed signal VLSI- by Micael Lee Bushnell, Vishwani D Agarwal. www.hunteng.co.uk www.fpgajournal.com