SCALAR PROCESSOR

Computer Architecture and Operating System

Master of Science in Information Technology 8/1/2012

Definition Scalar processors are those executing one instruction per cycle, only one instruction is issued per cycle and only one completion of instruction is expected from the pipeline per cycle
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ARCHITECTURAL OVERVIEW
A scalar processor logically consists of an integer unit (IU) and a floatingpoint unit (FPU), each with its own registers. This organization allows for implementations with concurrency between integer and floating-point instruction execution.
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INTEGER UNIT
contains the general-purpose registers and controls the overall operation of the processor. The IU executes the integer arithmetic instructions and computes memory addresses for loads and stores. It also maintains the program counters and controls instruction execution for the FPU.
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DEFINITION OF TERM A request by a processor to replace the value of a specified memory location. The address and new value are bound to the store transaction when the processor initiates the store transaction.
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DEFINITION OF TERM

A request by a processor to retrieve the value of the specified memory location. The address is bound to the load transaction when the processor initiates the load transaction.
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FLOATING- POINT UNIT

A processing unit that contains the floating-point registers and performs floating-point operations.

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REGISTERS
includes two types of registers: generalpurpose, or working data registers, and control/status registers Working registers include: Integer working registers (r registers) Floating-point working registers (f registers)
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Control/ Status Registers

Program Counter register (PC) Next Program Counter register (nPC) Trap Base Address register (TBA) Y register (Y) Processor Interrupt Level register (PIL) Current Window Pointer register (CWP) Trap Type register (TT) Condition Codes Register (CCR) Address Space Identifier register (ASI)
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Trap Level register (TL) Trap Program Counter register (TPC) Trap Next Program Counter register (TNPC) Trap State register (TSTATE) Hardware clock-tick counter register (TICK) Savable windows register (CANSAVE)

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CONTROL STATUS REGISTERS

Other windows register (OTHERWIN) Clean windows register (CLEANWIN) Window State register (WSTATE) Version register (VER) Implementation-dependent Ancillary State Registers (ASRs) Implementation-dependent IU
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Deferred-Trap Queue (impl. dep. #16) Floating-Point State Register (FSR) floating-Point Registers State register (FPRS) Implementation-dependent Floating-Point Deferred-Trap Queue (FQ)

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THE USE OF A LARGE REGISTER FILE

The register file is physically small, on the same chip as the ALU and control unit, and employs much shorter addresses than addresses for cache and memory. Thus, a strategy is needed that will allow the most frequently accessed operands to be kept in registers and to minimize register- memory operations.
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