ARM AT91SAM 9XE512

WHAT IS ARM?

Advanced RISC Machine

Market-leader for low-power and cost-sensitive embedded applications

Architectural simplicity which allows

Very small implementations which result in

Very low power consumption

APPLICATIONS
Product Type

Application

Smartphones, PDA, Set top box, Electronic toys, Digitalcameras etc Networking Wireless LAN, 802.11, bluetooth, Firewire etc Automotive Power train, ABS, Body systems, Navigation, etc Embedded USB controllers, bluetooth controllers, medical scanners etc Storage HDD controllers, solid state drives etc

Consumer

THE HISTORY OF ARM

Developed at Acorn Computers Limited, of Cambridge, England, between 1983 and 1985 Later they spun off the Acorn Computers and launched a new company called ARM Ltd. In 1990. (Acorn, Apple & VLSI Technologies) ARM architecture is licensable. Licensees include ATMEL, INTEL, SAMSUNG,PHILIPS(NXP), TEXAS etc.

ARM ARCHITECTURE

Typical RISC architecture:

Large uniform register file

Load/store architecture
Simple addressing modes Uniform and fixed-length instruction fields

Increases speed most instructions executed in single cycle Pipeline Versions:

3-stage (ARM7TDMI and earlier) 5-stage (ARMS, ARM9TDMI) 6-stage (ARM10TDMI)

ARM CORES
Architecture ARMv1 ARMv2 ARMv3 ARMv4

Family

ARMv5

ARMv6 ARMv7 ARMv8

ARM1 ARM2, ARM3 ARM6, ARM7 Strong ARM, ARM7TDMI, ARM9TDMI ARM7EJ, ARM9E, ARM10E, XScale ARM11 Cortex Will support 64-bit data and addressing

NOMENCLATURE

ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S}

x - family y - memory management/protection unit z - cache T Thumb Instruction D - JTAG debug M - fast multiplier I - Embedded ICE macro cell E - enhanced instructions J - Jazelle F - vector floating-point unit S - synthesizable version

ARM AT91SAM 9XE512

ATMELs Smart ARM-based Microcontrollers. Incorporates the ARM926EJ-S ARM Processor. DSP Instruction Extensions Harvard Architecture Two Instruction Sets

ARM 32-bit Instruction Set Thumb 16-bit Instruction Set

5-Stage Pipeline

Fetch (F) Decode (D) Execute (E) Data Memory (M) Write back (W)

REGISTERS

Sixteen 32 bit registers(R0-R15) & CPSR (current program status register ). R0 R12 are user registers.

R13 used as stack pointer (SP).

R14 is the link register (LR). On a function call, the return address is automatically stored in LR R15 is the program counter (PC)

CPSR

Divided into four 8 bits wide fields: flags, status, extension, and control.

OPERATING MODES
Seven different operating modes Processor enters

Abort Mode : when failed to access memory FIQ Mode : when a high priority (fast) interrupt is raised IRQ Mode : when a low priority (normal) interrupt is raised Supervisor Mode : on reset and on a Software Interrupt instruction is executed Undefined Mode - when encounters an instruction that is undefined or not supported

User Mode : unprivileged mode. Normal program execution mode. Mode changed by exception only. System mode - special version of user mode, full readwrite access to the CPSR

BANKED REGISTERS
20 registers are hidden from a program. Only available in particular mode Mode can be changed by a program writes to CPSR (except in user ) or by hardware

EXCEPTION HANDLING

When an exception occurs:

Copies CPSR into SPSR _<mode> CPU changes mode. Stores the return address in LR_<mode> PC be forced to exception vector.

To return from exception :

Restore CPSR from SPSR_<mode> Restore PC from LR_<mode>

ARM AT91SAM 9XE512 BLOCK DIAGRAM

External Bus Interface (EBI)

Supports

SDRAM, Static Memory, ECC-enabled NAND Flash and Compact Flash

Image Sensor Interface Ethernet MAC

128-byte

FIFOs and Dedicated DMA Channels for Receive and Transmit

USB 2.0 Full Speed Port

Integrated

FIFOs and Dedicated DMA Channels

32 Kbyte Internal ROM 32 Kbyte Internal SRAM 512 Kbytes of Internal High-speed Flash

Reset Controller(RSTC) Shutdown Controller(SHDWC) Four 32-bit backup registers(GPBREG) 32KHZ oscillator and a RC oscillator Real-time Timer (32 bit RTT) Main oscillator supports 3 to 20 MHz Embeds 2 PLLs. PLL A outputs 80 to 240 MHz clock. PLL B outputs

70 MHz to 130 MHz clock

Power Management Controller(PMC) Advanced Interrupt Controller (AIC) Debug Unit(DBGU) Periodic Interval Timer(20-bit PIT) Watchdog Timer (16 bit WDT) Brown Out Detect (BOR) Power On Reset(POR)

Two-slot Multimedia Card Interface (MCI) 4-channel 10-bit Analog to Digital Converter Peripheral DMA Controller Channels (PDC) Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) 2 Three-channel 16-bit Timer/Counters (TC) One 2-wire UART 4 USART 2 Master/Slave SPI USB 2.0 Full Speed Device Port (12 Mbps) 2 Two-wire Interfaces (TWI-I2C) One Synchronous Serial Controllers (SSC- I2S)

BUS MANAGEMENT

Consist of 2 Buses
6-layer AHB Matrix bus handling requests from 6 masters (Advanced High Performance Bus) APB bus (Advanced Peripheral Bus) Peripheral Bridge 24 channel Peripheral DMA Controller Allows data transfers from peripheral to any memory space without any intervention of the processor.

MEMORY MAP

MEMORY MAP

4 GBytes of address space

Divided into 16 banks of 256 Mbytes. Bank0 15

Bank 0 is reserved for the addressing of the internal memories The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7 The bank 15 is reserved for the peripherals