Amp 8086

CHAPTER 4 A PROGRAMMER'S VIEW OF COMPUTER ORGANIZATION
Copyright 2000, Daniel W. Lewis. All Rights Reserved.
Two Alternative Input/Output Configurations

I/O
CPU
Memory
CPU coordinates transfer between I/O and memory. Direct Memory Access (DMA).
CPU
Memory
I/O
Central Processing Unit and Main Memory of a Computer.

Operations performed here.
CPU
Address Bus
Control Bus Data Bus Memory
Operands and results are stored here.
The Central Processing Unit

Control Unit Program Counter Instruction Register Memory Address Register Memory Data Register Address Bus Data Bus Control Bus
Instruction Decoder
General Purpose Registers
Arithmetic and Logic Unit (ALU)
ALU Data Paths for Dyadic Operations Using a Single Accumulator Register.
Operand #1: Current contents of accumulator
A Result: Replaces old contents of accumulator ALU Operand #2: Read from memory Accumulator B Memory Data Bus
result op1 + op2

Single Accumulator Machine:
ACC MEM[adrs_of_op1] ACC ACC + MEM[adrs_of_op2] MEM[adrs_of_result] ACC

Register Machine:
REG[r] MEM[adrs_of_op1] REG[r] REG[r] + MEM[adrs_of_op2] MEM[adrs_of_result] REG[r]

The Fetch-Execute Cycle

Program counter provides the address. Additional instruction bytes retrieved here as necessary.
Fetch The Next Instruction
Execute the Fetched Instruction
The Fetch Phase

1. 2. 3. 4. 5. 6. Memory_Address_Bus Program_Counter Start Memory Read Operation Increment Program_Counter Wait for Memory Read to Complete Instruction_Register Memory_Data_Bus Go to execute phase.
The Fetch Phase

Program Counter
+1 1001 1000 Main Memory Address 1000 1001 1002 Data LDA ADD STA [x] [y] [z]
Instruction Register LDA [x]
Control Flow Portion of a CPU

Memory Data Bus
Memory Address Bus Control Unit (Opcode decoding and sequencing) Control Signals
Branch Address
Opcode bits. Instruction Register
+1
Program Counter
The Intel Processor Family

Processor Year MIPS CPU Frequency 8.0 MHz Register Size Data Bus Address Space CPU Cache 8086 1978 0.8 16 16 1 MB None
286
1982
2.7
12.5 MHz
16
16
16 MB
None
386
1985
6.0
20 MHz
32
32
4 GB
None
486
1989
20
25 MHz
32
32
4 GB
8 KB L1
Pentium
1993
100
60 MHz
32
64
4 GB
16 KB L1 16 KB L1; 512 KB L2 32 KB L1; 512 KB L2 32 KB L1; 512 KB L2
Pentium Pro
1995
440
200 MHz
32
64
64 GB
Pentium II
1997
466
266
32
64
64 GB
Pentium III
1999
1000
500
32
64
64 GB
Operating Modes of Intel IA

Real-address Mode: This mode corresponds to the original 8086 processor and is supported by all processors in the IA family. It is the initial operating mode when a hardware reset signal is applied to the processor at start-up. Only a limited number of processor features are available in real mode and the physical address space is limited to one megabyte. Protected Mode System Management Mode

Real-address Mode Protected Mode: This mode was originally introduced with the Intel 286, and later enhanced in the Intel 386. Protected mode offers greater performance than real mode. All of the features of the processor are available and a much larger physical address space. System Management Mode

Real-address Mode Protected Mode System Management Mode: This mode was originally introduced with the Intel 386SL. This mode is primarily used to implement power management and system security. It is not described in this text.
Four Types of Instruction Operands

1. A constant embedded within the instruction representation, or 2. The contents of a register, or
3. The contents of a memory location, or
4. The contents of an I/O port.

Instruction Formats
Operand Fields
0 1 2
Example
Description
CLC Clear the carry flag to 0. INC AX Increment contents of register AX MOV AX,BX Copy contents of BX into AX.
Destination operand
Source operand
General Purpose Registers

31 (E)AX: Accumulator 16 15 AH BH CH DH SP BP SI DI 0 AL BL CL DL MSW of EAX MSW of EBX MSW of ECX MSW of EDX MSW of ESP MSW of EBP MSW of ESI MSW of EDI
(E)BX: Base Register

(E)CX: Count Register (E)DX: Data Register (E)SP: Stack Pointer (E)BP: Base Pointer (E)SI: Source Index (E)DI: Destination Index
Segment Registers
Hidden Part 79 16 15 Visible Part 0
CS DS
SS
ES FS
Copies of GDT entries corresponding to value of segment selectors (not used in Real Mode)
Segment Selector
GS
EFlags and EIP Registers

31 (E)Flags Register: MSW of EFLAGS FLAGS 0
(E)IP: Instruction Pointer MSW of EIP IP
Flags Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF
DF
IF
TF
SF
ZF
AF
PF
CF
Flag Overflow Direction Interrupt Enable Trap Sign Zero Auxiliary Carry Parity Carry
Bit 11 10 9 8 7 6 4 2 0
Description Previous result caused arithmetic overflow. 1 = auto-decrement, 0 = auto-increment. Interrupts are enabled Single step mode enabled Previous result was negative Previous result was zero Previous result produced a BCD carry Previous result had even parity Previous result produced a carry put of MSB
Byte Ordering of 32-bit Value With Little Endian Format.

32-bit value = 1234567816
0001 0010 Byte N+3 0011 0100 Byte N+2 0101 0110 Byte N+1 0111 1000 Byte N
In little endian format, the address of a 32-bit quantity is the same as the address of its least significant byte.
The Stack
Instruction sequence:
PUSH EBX PUSH AX PUSH CS
Address
SS:[ESP+10] SS:[ESP+8] SS:[ESP+4]
Memory contents
value from EBX(32 bits) value from AX (16 bits) value from CS (32 bits)
Stack "grows" downward.
PUSH EDX
SS:[ESP]
value from EDX (32 bits)
Top of stack
Real-Mode Addressing
16-bit segment 0000 12 MSBs of offset padded with four 0's on the left 16-bit offset 4 LSBs of offset
16-bit Adder
16 MSBs of result 20-bit physical address
4 LSBs of result
The segment value establishes a reference point to the beginning of a 64kb block of memory; the offset is a positive displacement from this reference. Offset = 012316 Segment = 8B2E16
Memory Operand 8B40316
8B2E016
Instruction Operands
Constant Immediate Mode
Embedded within representation of instruction.
Memory Location Real Mode:

Address = RB + RI + constant
Protected Mode:
Address = R1 + C1 R2 + C2
Register Register Mode I/O Port
Immediate Mode
(Example: MOV AX,12345)
opcode
16-bit operand
Operand is embedded within instruction representation.

Protected Mode:
Register Mode
(Example: MOV AX,CX)
opcode
code AH CH AX SI DS
Instruction has code to select register contents as operand
registers AL BH CL DH BX CX DI SP CS SS
BL DL DX BP ES

Protected Mode:
ADDRESSING MEMORY IN REAL MODE
Base Index Constant
BX BP None +
SI DI None +
16-bit 8-bit None
Direct Addressing Mode

(Example: MOV AX,[TOTAL])
opcode
16-bit offset
Instruction provides offset
memory operand
Register Indirect Mode

(Example: MOV AX,[BX])
opcode
code BX, BP, SI, or DI Register provides offset
memory operand
or
Address = RB + RI + constant Address = RB + RI + constant

Indexed and Based Address Mode

(Example: MOV AX,[BX+3])
opcode Code selects register to use code displacement Offset is sum of selected register and displacement. memory
operand
BX, BP, SI, DI
Based: BX or BP Indexed: SI or DI
or
Based-indexed Address Mode

(Example: MOV AX,[BX+SI+3])
opcode
code
code
displacement
memory
BX or BP SI or DI
operand
ADDRESSING MEMORY IN PROTECTED MODE
How Segment Registers are Used

GDTR Register Physical Address (& Length) of Global Descriptor Table 32 bits + 16 bits Segment Start Address ... Segment Register + Physical Address 32 bits Global Descriptor Table
Resides in Main Memory
16-bit Segment Selector 32-bit offset from effective address calculation
32 bits
The Flat Memory Model

GDT configured so that all segments start at physical address zero and have a size of 4GB. There's a one-to-one correspondence between physical addresses and the 32-bit offsets produced by effective address calculations. Memory looks like a single continuous space, called a linear address space.

Protected Mode:
Protected-Mode Addressing
Base EAX EBX ECX EDX ESI EDI EBP ESP None Index EAX EBX ECX EDX ESI EDI EBP None Scale Factor Displacement
1
2
None +
8-bit
3
4
16-bit
32-bit
Restrictions: MOV dst,src

No more than 1 operand in memory. No more than 1 operand in a segment register. Only 8, 16, or 32 bit operands.
Operand sizes must match (or else extend the length using MOVSX or MOVZX).
If destination is a segment register, source cannot be an immediate constant.

Operand Sizes
May be implicit: May be inferred: INC EAX MOV AL,[EBX]
Size of register EAX is 32 bits.
AL is 8 bits, so register EBX contains the address of an 8-bit memory operand.
May be explicit:
INC DWORD [EBX]
Ambiguous without DWORD!
Real Mode Defaults

Address Field of Instructions is 16 bits
Precede instruction by 0x67 to use 32 bits:
DB 67H MOV AX,[BX]
Equivalent to MOV AX,[EBX]
Operands are either 8 or 16 bits

DB 66H MOV AX,[BX]
Equivalent to MOV EAX,[BX]
Protected Mode Defaults

Address Field of Instructions is 32 bits
DB 67H MOV EAX,[EBX]
Equivalent to MOV EAX,[BX]
Operands are either 8 or 32 bits

DB 66H MOV EAX,[EBX]
Equivalent to MOV AX,[EBX]
16 vs. 32-bit Operands

Real Mode Protected Mode
PUSH AX
0101 0000
Prefix Byte (66h)
PUSH EAX
PUSH EAX
0110 0110 0101 0000
PUSH AX
16 vs. 32-bit Operands

MOV AX,imm16
1011 1000
Prefix Byte (66h)
MOV EAX,imm32
(2 bytes follow)
MOV EAX,imm32 (4 bytes follow)
(4 bytes follow)
MOV AX,imm16 (2 bytes follow)
0110 0110 1011 1000
16 vs. 32-bit Address Field

MOV AX,[mem16] (2-byte adrs field) MOV AX,[mem32] (4-byte adrs field)
1010 0001
Prefix Byte (67h)
MOV EAX,[mem32] (4-byte adrs field) MOV EAX,[mem16] (2-byte adrs field)
0110 0111 1010 0001
Data Movement Instructions

MOV dst,src LEA reg32,mem MOVZX reg32,src MOVSX reg32,src XCHG dst,src ; dst src ; reg32 offset32 (mem) ; reg32 zero extended src ; reg32 sign extended src ; temp dst dst src src temp
Stack Instructions
PUSH src16 PUSH src32 PUSHF PUSHA ; ESP ESP-2, MEM[SS:ESP] src16 ; ESP ESP-4, MEM[SS:ESP] src32 ; ESP ESP-4, MEM[SS:ESP] EFlags ; Pushes EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI
POP dst16 POP dst32 POPF POPA
; dst16 MEM[SS:ESP], ESP ESP+2 ; dst32 MEM[SS:ESP], ESP ESP+4 ; EFlags MEM[SS:ESP], ESP ESP+4 ; Pops EDI, ESI, EBP, skip, EBX, EDX, ECX, EAX
Arithmetic Instructions
ADD dst,src ADC dst,src SUB dst,src SBB dst,src INC dst DEC dst NEG dst MUL src ; unsigned IMUL src ; signed DIV src ; unsigned IDIV src ; signed CBW CWD/CDQ CMP dst,src
Extended Precision ADD/SUB

MOV MOV instructions have no effect on EFlags! ADD MOV EAX,[x] EAX,[y] [z],EAX
63 63 32 31 0 [x+4] [x]
32 31
MOV
ADC MOV
EAX,[x+4]
EAX,[y+4] [z+4],EAX
63 [y+4] [y]
32 31
[z+4]
[z]
MUL & IMUL

Example MUL src8
MUL src16 MUL src32
Operation AL src8
AX src16 EAX src32
Product AX
DX.AX EDX.EAX
DIV & IDIV

Example
DIV src8 DIV src16
Operation
AX src8 DX.AX src16
Quotient Remainder
AL AX EAX AH DX EDX
DIV src32 EDX.EAX src32
CBW, CWD, & CDQ

Opcode
CBW CWD CDQ
Source
AL AX EAX
Destination
AX DX.AX EDX.EAX
Signed vs. Unsigned Division

unsigned int a, b, c ;
signed int a, b, c ;
a=b/c; MOV EAX,[b] SUB EDX,EDX DIV DWORD [c] MOV [a],EAX
a=b/c; MOV EAX,[b] CDQ IDIV DWORD [c] MOV [a],EAX
Bitwise Logical Instructions

AND OR XOR NOT TEST dst,src dst,src dst,src dst dst,src ; dst dst & src ; dst dst | src ; dst dst ^ src ; dst ~dst ; dst & src
Shift Instructions: opc dst,count

RCL:
ROL: SAL:
0
RCR:
ROR: SAR:
SHL:
SHR:
64-bit Logical Right Shift

63 32
Step #1:
[x+4]
CF
SHR [X+4],1
31
Step #2:
CF
[x]
RCR [X],1
Conditional Jump Instructions

Signed Tests: JG/JNLE label JGE/JNL label JL/JNGE label JLE/JNG label Equality Tests: JE/JZ label JNE/JNZ label Unsigned Tests: JA/JNBE label JAE/JNB label JB/JNAE label JBE/JNA label Other Tests: JC, JNC, JO, JNO, JS, JNS, JPO, JNP, JECXZ
Other Jump Instructions

Unconditional: JMP label JMP regptr JMP memptr Loops (count in register ECX): LOOP short-label LOOPE/LOOPZ short-label LOOPNE/LOOPNZ short-label

Amp 8086

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CHAPTER 4 A PROGRAMMER'S VIEW OF COMPUTER ORGANIZATION

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Two Alternative Input/Output Configurations

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Central Processing Unit and Main Memory of a Computer.

Operands and results are stored here.

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

The Central Processing Unit

General Purpose Registers

Arithmetic and Logic Unit (ALU)

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

result op1 + op2

ACC MEM[adrs_of_op1] ACC ACC + MEM[adrs_of_op2] MEM[adrs_of_result] ACC

REG[r] MEM[adrs_of_op1] REG[r] REG[r] + MEM[adrs_of_op2] MEM[adrs_of_result] REG[r]

The Fetch-Execute Cycle

Fetch The Next Instruction

Execute the Fetched Instruction

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

The Fetch Phase

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

The Fetch Phase

Instruction Register LDA [x]

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Control Flow Portion of a CPU

Opcode bits. Instruction Register

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

The Intel Processor Family

16 KB L1 16 KB L1; 512 KB L2 32 KB L1; 512 KB L2 32 KB L1; 512 KB L2

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Operating Modes of Intel IA

Operating Modes of Intel IA

Operating Modes of Intel IA

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Four Types of Instruction Operands

4. The contents of an I/O port.

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

General Purpose Registers

(E)BX: Base Register

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

EFlags and EIP Registers

(E)IP: Instruction Pointer MSW of EIP IP

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Byte Ordering of 32-bit Value With Little Endian Format.

Stack "grows" downward.

value from EDX (32 bits)

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

16 MSBs of result 20-bit physical address

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Memory Operand 8B40316

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Memory Location Real Mode:

Register Register Mode I/O Port

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Operand is embedded within instruction representation.

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Memory Location Real Mode:

Register Register Mode I/O Port

Copyright 2000, Daniel W. Lewis. All Rights Reserved.

Instruction has code to select register contents as operand

Copyright 2000, Daniel W. Lewis. All Rights Reserved.