ECE 425 - VLSI Circuit Design

Lecture 1 - Course Overview

Spring 2007

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu

Announcements
Course Website:
http://foghorn.cadlab.lafayette.edu/ece425/

Brief Lab Tomorrow in AEC 400 Reading

Wolf 1, 2.1-2.3

ECE 425 Spring 2007

Lecture 1 - Course Overview

Todays Topics
Course overview
Objectives Roadmap for the Semester Administrative Details

VLSI Overview
Transistor Structure Static CMOS Logic Design Methods & Design Styles VLSI Trends

ECE 425 Spring 2007

Lecture 1 - Course Overview

Course Objectives
Students should be able to
VLSI Circuit Analysis:

Understand MOS transistor operation, design eqns. Understand parasitics & perform simple calculations Understand static & dynamic CMOS logic Estimate delay of CMOS gates, networks, & long wires Estimate power consumption Understand design and operation of latches & flip/flops
Understand the VLSI manufacturing process. Have an appreciation of current trends in VLSI manufacturing. Understand layout design rules. Design and analyze layouts for simple digital CMOS circuits Design and analyze hierarchical circuit layouts. Understand ASIC Layout styles.
Lecture 1 - Course Overview 4

CMOS Processing and Layout

ECE 425 Spring 2007

Course Objectives
Students should be able to (contd)
VLSI System Design
Understand register-transfer level design. Design simple combinational and sequential logic circuits using using a Hardware Description Language (HDL). Design small to medium circuits consisting of multiple components such as a controller and datapath using a HDL. Understand the design flows used in industrial IC design. Design a small standard-cell chip in its entirety using a variety of CAD tools and check it for correct operation.

ECE 425 Spring 2007

Lecture 1 - Course Overview

Roadmap for the term: major topics

VLSI Overview \ CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools & Verilog Mixed Signal Concerns: D/A, A/D Conversion Register-Transfer Design with Verilog Design Project: Complete Chip
ECE 425 Spring 2007 Lecture 1 - Course Overview 6

Administrative Details
Grading
Take-Home Entry Exam 0% 2 In-Class Exams 50% Laboratory 40% Homeworks 10% MWF 9:00-9:50, T 1:10-4:00 PM MW 10:00-11:50 MWF 2-3, T 10-12 or by appointment

My Schedule
ECE 425 VAST 200 Office Hours

ECE 425 Spring 2007

Lecture 1 - Course Overview

Adminstrative Details (contd)

Prerequisites
ECE 322 - Intro. Solid State Devices & Circuits Unofficial: ECE 211, 212 - Digital Design

Textbook
W. Wolf, Modern VLSI Design: Systems on Silicon, 3rd. ed. Prentice-Hall, 2002.

References
J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd. ed., Prentice-Hall, 2002. N. Weste and D. Harris, CMOS VLSI Design: Addison-Wesley, 2005. M. Ciletti, Modeling, Synthesis, and Prototyping with the Verilog HDL, Prentice-Hall, 1999.

ECE 425 Spring 2007

Lecture 1 - Course Overview

VLSI Overview
Common technologies CMOS Transistors & Logic Gates
Structure Switch-Level Transistor Model Basic gates

The VLSI Design Process

Levels of Abstraction Design steps Design styles

VLSI Trends

ECE 425 Spring 2007

Lecture 1 - Course Overview

VLSI Technology Overview

Common technologies:
CMOS* (dominant technology) Bipolar (e.g., TTL) Bi-CMOS - hybrid Bipolar, CMOS (for high speed) GaAs - Gallium Arsenide (for high speed) Si-Ge - Silicon Germanium (for RF)

Key manufacturing technology: photolithography

*Complementary Metal Oxide Semiconductor

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VLSI Technology - CMOS Transistors

Key feature: transistor length L

2002: L=130nm 2003: L=90nm 2005: L=65nm 2007: L=45nm?

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VLSI Technology - CMOS Transitors

What they really look like a 130nm transistor from the IBM G5 processor:

Image Source: Apple Computer www.apple.com

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Transistor Switch Model

nfet or n transistor
on when gate H "good" switch for logic L "poor" switch for logic H "pull-down" device on when gate L "good" switch for logic H "poor" switch for logic L "pull-up" device

pfet or p transistor

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CMOS Logic Design

Complementary transistor networks
Pullup: p transistors Pulldown - n transistors
VDD VDD Pullup Network (p-transistors) Inputs Out Pulldown Network (n-transistors) Gnd
ECE 425 Spring 2007

In

Out

Gnd Lecture 1 - Course Overview Inverter

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CMOS Inverter Operation

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CMOS Logic Example - Whats This?

+VDD

B
OUT

P Transistors on when gate L

A
B GND

N Transistors on when gate H

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VLSI Levels of Abstraction

Specification
(what the chip does, inputs/outputs)

Architecture
major resources, connections

Register-Transfer
logic blocks, FSMs, connections

Logic
gates, flip-flops, latches, connections

Circuit
transistors, parasitics, connections

Layout
mask layers, polygons
ECE 425 Spring 2007 Lecture 1 - Course Overview 17

The VLSI Design Process

Move from higher to lower levels of abstraction Use CAD tools to automate parts of the process Use hierarchy to manage complexity Different design styles trade off:
Design time Non-recurring engineering (NRE) cost Unit cost Performance Power Consumption

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VLSI Design Tradeoffs

Non-Recurring Engineering (NRE) Costs
Design Costs Mask Tooling costs

Unit Cost - related to chip size

Amount of logic Current technology

Performance
Clock speed Implementation

Power consumption
Power supply voltage Clock speed
ECE 425 Spring 2007 Lecture 1 - Course Overview 19

VLSI Design Styles

Full Custom ASIC - Application-Specific Integrated Circuit PLD, FPGA - Programmable Logic SoC - System-on-a-Chip

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Full Custom Design Style

Each circuit element carefully handcrafted Tradeoffs
High Design Costs (huge effort!) High NRE Cost High Performance Low Unit Cost (good for high volume products!)

Examples
Analog and Mixed-Signal Microprocessor

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ASIC Design Style

Pre-designed (or pre-manufactured) components that are assembled and wired by CAD tools.
Standard cell (pre-designed cells) Gate array (pre-manufactured cells - just add wiring) Structured ASIC (complex function customized by wiring)

Tradeoffs
Low Design Cost High NRE Cost (lower in Gate Array / Structured ASIC) Medium Unit Cost Medium Performance

Examples:
Control chip for cell phone Graphics chips for desktop computers (e.g. nVidia, ATI)
ECE 425 Spring 2007 Lecture 1 - Course Overview 22

Programmable Logic Design Style

Pre-manufactured components with programmable interconnect wired by CAD tools Tradeoffs
Low Design Cost Low NRE Cost (basically 0) Low performance High unit cost

Examples
Network routers (e.g., Cisco) Gibson digital electric guitar

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System-on-a-chip Design Style

Idea: combine several blocks
Intellectual property (IP) cores (e.g. ARM processor) ASIC logic for special-purpose hardware Programmable Logic (PLD, FPGA) Analog

Tradeoffs
Medium design cost High NRE cost Medium performance Medium unit cost
Sigmatel STMP3520 MP3 Decoder
Image source: Semiconductor Insights, Inc. www.semiconductor.com

Examples
Consumer electronics (e.g., iPod) Cable set-top boxes
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Perspective on Design Styles

Few engineers will design custom chips Some engineers will design ASICs & SOCs Many engineers will design FPGA systems

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VLSI Trends: Moores Law

In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing:
Doubled transistor density every 18-24 months Doubled performance every 18-24 months
Your job is No exponential to postpone is forever, forever! BUT

History has proven Moore right But, is the end is in sight?

Physical limitations Economic limitations

Gordon Moore Intel Co-Founder and Chairmain Emeritus

Image source: Intel Corporation www.intel.com

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Microprocessor Trends (Intel)

Year 1971 1974 1976 1982 1985 1989 1993 1995 1999 2000 2002 2003 2004 2006 Chip 4004 8080 8088 80286 80386 80486 Pentium Pentium Pro Mobile PII Pentium 4 Pentium 4 (N) Itanium 2 (M) Pentium 4 (P) Core 2 Duo L 10m 6m 3m 1.5m 1.5m 0.8m 0.8m 0.6m 0.25m 180nm 130nm 130nm 90nm 65nm transistors 2.3K 6.0K 29K 134K 275K 1.2M 3.1M 15.5M 27.4 42M 55M 410M 125M 291M
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Deep Submicron

Source: http://www.intel.com/pressroom/kits/quickreffam.htm, media reports ECE 425 Spring 2007 Lecture 1 - Course Overview

Microprocessor Trends
Alpha (R.I.P)

P4

G4
Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com ECE 425 Spring 2007 Lecture 1 - Course Overview 28

Microprocessor Trends (Log Scale)

Itanium 2 Alpha (R.I.P) G5
P4N G4

Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com ECE 425 Spring 2007 Lecture 1 - Course Overview 29

DRAM Memory Trends (Log Scale)

Source: Textbook, Industry Reports

1000 512 100 10 4 1 0.25 0.1 0.01 1975 0.0625 1 16 Size (Mb) 256 128 64

1980

1985

1990

1995

2000

2005
30

ECE 425 Spring 2007

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Processor Performance Trends

Vax 11/780

Source: Hennesy & Patterson Computer Architecture: A Quantitative Approach, 3rd Ed., Morgan-Kaufmann, 2002.

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Summary - Technology Trends

Processor
Logic capacity Clock frequency Cost per function increases ~ 30% per year increases ~ 20% per year Not any more! decreases ~20% per year increases ~ 60% per year increases ~ 10% per year decreases ~25% per year

Memory
DRAM capacity: (4x every 3 years) Speed: Cost per bit:

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Gallery - Early Processors

Mos Technology 6502

Intel 4004
First P - 2300 xtors L=10m ECE 425 Spring 2007 Lecture 1 - Course Overview 33

Gallery - Current Processors

Process Shrinks

Pentium 4
42M transistors / 1.3-1.8GHz 49-55W L=180nm ECE 425 Spring 2007

Pentium 4 Northwood Pentium 4 Prescott

55M transistors / 2-2.5GHz 55W L=0.130nm Area=131mm2 Lecture 1 - Course Overview 125M transistors / 2.8-3.4GHz 115W L=90nm Area=112mm2 34

Gallery - Current Processors

Intel Core 2 Duo Conroe

291M transistors / 2.67GHz / 65W L=65nm Area=143mm2 ECE 425 Spring 2007 Lecture 1 - Course Overview
Image courtesy Intel Corporations All Rights Reserved

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Gallery - Current Processors

IBM Cell Processor

234M transistors / 2GHz / ??W L=90nm Area=221mm2 ECE 425 Spring 2007 Lecture 1 - Course Overview

Image courtesy International Business Machines All Rights Reserved

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Gallery - Current FPGA

Xilinx Virtex FPGA

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Gallery - Graphics Processor

nVidia GeForce4
ECE 425 Spring 2007 57M transistors / 300MHz / ??W L=0.15m Lecture 1 - Course Overview 38

What were going to do

Chip design: MOSIS tiny chip

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What were going to do

Fabricated MOSIS Tiny Chip

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Die Photo - 2001 Design Project

Chip Design by Ed Thomas Photo courtesy Ron Feiller, Agere

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Coming Up:
Fabrication Basics: Photolithography Transistor Structure Transistor Operation CMOS Processing Steps Layout Design

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