Design Methodologies by Rabaey

Digital Integrated Circuits
A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Design Methodologies
December 10, 2002
Digital Integrated Circuits2nd
The Design Productivity Challenge

.10m 1,000,000 100,000 .35m 10,000 1,000 100
X x X
X X X
Transistor/Staff Month 58%/Yr. compound Complexity growth rate
10,000,000 1,000,000 100,000 10,000 1,000 100 10

1999 2003 2005 2007
2001 2009
2.5m
10
1 Logic Transistors per Chip (K)

1981 1985 1987 1989 1991 1993 1995
1983
21%/Yr. compound Productivity growth rate

1997
Produc
A growing gap between design complexity and design productivity Source: sematech97 Digital Integrated Circuits2nd
19811985198919931997200120052009 1983198719911995199920032007
Productivity (Trans./Staff-Month)
10,000,000
Logic Transistors/Chip
100,000,000
Logic Transistors per Chip (K)
A Simple Processor
MEMORY INPUT/OUTPUT
CONTROL
INPUT-OUTPUT DATAPATH
A System-on-a-Chip: Example
Courtesy: Philips
Impact of Implementation Choices

100-1000
Energy Efficiency (in MOPS/mW) Domain-specific processor (e.g. DSP) Embedded microprocessor 0.1-1
10-100
Configurable/Parameterizable
Hardwired custom
1-10
None
Somewhat flexible
Fully flexible
Flexibility (or application scope)
Design Methodology
Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps Digital Integrated Circuits2nd
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Standard Cells Compiled Cells
Macro Cells
Pre-diffused (Gate Arrays)
Pre-wired (FPGA's)
The Custom Approach

Intel 4004
Courtesy Intel
Transition to Automation and Regular Structures
Intel 4004 (71) Intel 8080 Intel 8085
Intel 8286
Digital Integrated Circuits2nd Courtesy Intel
Intel 8486
Cell-based Design (or standard cells)
Routing channel requirements are reduced by presence of more interconnect layers
Standard Cell Example
[Brodersen92]
Standard Cell The New Generation
Cell-structure hidden under interconnect layers
Standard Cell - Example
3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time
Automatic Cell Generation
Initial transistor geometries
Placed transistors
Routed cell
Compacted cell
Finished cell
Courtesy Acadabra
A Historical Perspective: the PLA

Product terms x0 x1 AND plane
x2
OR plane
f0 x0 x1 x2
f1
Two-Level Logic
Every logic function can be expressed in sum-of-products format (AND-OR)
minterm
Inverting format (NORNOR) more effective

PLA Layout Exploiting Regularity

V DD
And-Plane
Or-Plane f
GND
x0 x0 x1 x1 x2 x2 Pull-up devices
f0 f1 Pull-up devices
Breathing Some New Life in PLAs

River PLAs

PRE-CHARGE
A cascade of multiple-output PLAs. Adjacent PLAs are connected via river routing.
BUFFER
BUFFER
PRE-CHARGE
PRECHARGE
BUFFER
BUFFER
PRE-CHARGE
PRE-CHARGE
BUFFER
BUFFER
PRE-CHARGE
BUFFER
PRE-CHARGE
No placement and routing needed. Output buffers and the input buffers of the next stage are shared.
PRECHARGE
BUFFER
Courtesy B. Brayton
Experimental Results
Area: RPLAs (2 layers) 1.23 SCs (3 layers) 1.00, NPLAs (4 layers) 1.31 Delay RPLAs 1.04 SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R.
1.4
0.6
Also: RPLAs are regular and predictable

0.2 0 2
SC
delay
1
4
NPLA RPLA
area
Layout of C2670
Standard cell, 2 layers channel routing
Standard cell, 3 layers OTC
Network of PLAs, 4 layers OTC
River PLA, 2 layers no additional routing
MacroModules
25632 (or 8192 bit) SRAM Generated by hard-macro module generator
Soft MacroModules
Synopsys DesignCompiler
Intellectual Property
A Protocol Processor for Wireless

Semicustom Design Flow

Design Capture HDL Design Iteration Pre-Layout Simulation Structural Logic Synthesis Behavioral
Floorplanning Post-Layout Simulation Circuit Extraction Placement Routing Physical
Tape-out Digital Integrated Circuits2nd
The Design Closure Problem
Iterative Removal of Timing Violations (white lines)
Courtesy Synopsys
Integrating Synthesis with Physical Design

RTL (Timing) Constraints
Physical Synthesis
Macromodules Fixed netlists Netlist with Place-and-Route Info
Place-and-Route Optimization
Digital Integrated Circuits2nd Artwork
Late-Binding Implementation
Array-based
Pre-diffused (Gate Arrays)
Pre-wired (FPGA's)
Gate Array Sea-of-gates

polysilicon VD D
rows of uncommitted cells
metal GND possible contact
Uncommited Cell
In 1 In 2
In 3 In4
routing channel
Committed Cell (4-input NOR)

Out
Sea-of-gate Primitive Cells

Oxide-isolation PMOS PMOS
NMOS
NMOS NMOS
Using oxide-isolation
Using gate-isolation
Example: Base Cell of Gate-Isolated GA
From Smith97
Example: Flip-Flop in Gate-Isolated GA
From Smith97
Sea-of-gates
Random Logic
Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS)
Courtesy LSI Logic
The return of gate arrays?

Via programmable gate array (VPGA)
Via-programmable cross-point
metal-5 programmable via
metal-6
Exploits regularity of interconnect

[Pileggi02]
Prewired Arrays
Classification of prewired arrays (or fieldprogrammable devices):
Based on Programming Technique

Fuse-based (program-once) Non-volatile EPROM based RAM based
Programmable Logic Style

Array-Based Look-up Table
Programmable Interconnect Style

Channel-routing Mesh networks
Fuse-Based FPGA
antifuse polysilicon ONO dielectric
n+ antifuse diffusion 2l
Open by default, closed by applying current pulse

From Smith97
Array-Based Programmable Logic

I5 I4 I3 I2 I1 I0 Programmable OR array I3 I2 I1 I0 Programmable OR array I5 I4 I3 I2 I1 I0 Fixed OR array
Programmable AND array O 3O 2O 1O 0
Fixed AND array O 3 O2 O1 O0
Programmable AND array

O 3O 2O 1O 0
PLA
PROM
Indicates programmable connection Indicates fixed connection
PAL
Programming a PROM
1 X2 X1 X0
: programmed node NA NA f 1 f 0
More Complex PAL
i inputs, j minterms/macrocell, k macrocells

Digital Integrated Circuits2nd From Smith97
2-input mux as programmable logic block

Configuration
A
0 0 0 0 X Y Y 1 1 1
B
0 X Y Y 0 0 1 0 0 1
S
0 1 1 X Y X X X Y 1
F=
0 X Y XY XY XY X1 Y X Y 1
A B
0 F 1
Logic Cell of Actel Fuse-Based FPGA

A B 1 Y 1
SA C
D SB S0 S1 1
Look-up Table Based Logic Cell

In Out 00 01
10 11 ln1 ln2
Memory
Out 00 1
1 0
LUT-Based Logic Cell

C1....C4 4 xx D4 D3 D2 D1 Logic function of xxx Logic function x of xxx Logic function of xxx xx xx xx xx xxxx xxxx xxxx Bits control
Figure must be updated
xxxx x xx x xx
x x x Bits control
xx xx x xxxx x xx x xx
F4 F3 F2 F1
xx xx xx xx
x xxxxx
xx xx H P x Multiplexer Controlled by Configuration Program x
Xilinx 4000 Series

Courtesy Xilinx
Array-Based Programmable Wiring

M
Interconnect Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
Mesh-based Interconnect Network

Switch Box
Connect Box
Interconnect Point
Courtesy Dehon and Wawrzyniek
Transistor Implementation of Mesh
Hierarchical Mesh Network
Use overlayed mesh to support longer connections Reduced fanout and reduced resistance
EPLD Block Diagram

Primary inputs
Macrocell
Courtesy Altera
Altera MAX
From Smith97
Altera MAX Interconnect Architecture

column channel
t PIA
row channel
LAB1
LAB2
LAB PIA
t PIA
LAB6
Array-based (MAX 3000-7000)

Mesh-based (MAX 9000)

Courtesy Altera
Field-Programmable Gate Arrays Fuse-based

I/O Buffers Program/T est/Diagnostics V ertical routes
Standard-cell like floorplan

I/O Buffers I/O Buffers
I/O Buffers
Rows of logic modules Routing channels
Xilinx 4000 Interconnect Architecture

12
Quad Single Double Long Direct

Connect
4 3
CLB
2
3
Long
12
Quad
4
Long
4
Global
8
Long
4
Carry
2
Direct
Double Single Global
Clock
Clock Chain Connect
Courtesy Xilinx
RAM-based FPGA
Xilinx XC4000ex Digital Integrated Circuits2nd Courtesy Xilinx
A Low-Energy FPGA (UC Berkeley)

Array Size: 8x8 (2 x 4 LUT) Power Supply: 1.5V & 0.8V Configuration: Mapped as RAM Toggle Frequency: 125MHz Area: 3mm x 3mm
Larger Granularity FPGAs

PADDI-2 (UC Berkeley)
1-mm 2-metal CMOS tech
1.2 x 1.2 mm2

600k transistors 208-pin PGA fclock = 50 MHz 3.6 W @ 5V
Pav =
Basic Module: Datapath
Design at a crossroad
System-on-a-Chip
500 k Gates FPGA MultiSpectral RAM + 1 Gbit DRAM Imager Preprocessing
64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS
mC system +2 Gbit DRAM

Recognition
Analog
Embedded applications where cost, performance, and energy are the real issues! DSP and control intensive Mixed-mode Combines programmable and application-specific modules Software plays crucial role
Addressing the Design Complexity Issue Architecture Reuse Reuse comes in generations
Generation 1 st 2 nd 3 rd 4 th Reuse element Standard cells IP blocks Architecture IC Status Well established Being introduced Emerging Early research
Source: Theo Claasen (Philips) DAC 00

Architecture ReUse
Silicon System Platform

Flexible architecture for hardware and software Specific (programmable) components Network architecture Software modules Rules and guidelines for design of HW and SW
Has been successful in PCs

Dominance of a few players who specify and control architecture
Application-domain specific (difference in constraints)

Speed (compute power) Dissipation Costs Real / non-real time data
Platform-Based Design
Only the consumer gets freedom of choice; designers need freedom from choice (Orfali, et al, 1996, p.522)
A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer New platforms will be defined at the architecture-micro-architecture boundary They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations Key to such approaches is the representation of communication in the platform model
Source:R.Newton
Berkeley Pleiades Processor

0.25um 6-level metal CMOS
FPGA
5.2mm x 6.7mm 1.2 Million transistors
Reconfigurable Data-path
Interface
40 MHz at 1V
2 extra supplies: 0.4V, 1.5V 1.5~2 mW power dissipation
ARM8 Core
Heterogeneous Programmable Platforms

FPGA Fabric
Embedded memories
Embedded PowerPc
Hardwired multipliers
Xilinx Vertex-II Pro

High-speed I/O
Courtesy Xilinx
Summary
Digital CMOS Design is kicking and healthy Some major challenges down the road caused by Deep Sub-micron
Super GHz design Power consumption!!!! Reliability making it work Some new circuit solutions are bound to emerge
Who can afford design in the years to come? Some major design methodology change in the making!

Design Methodologies by Rabaey

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Digital Integrated Circuits

The Design Productivity Challenge

Transistor/Staff Month 58%/Yr. compound Complexity growth rate

10,000,000 1,000,000 100,000 10,000 1,000 100 10

1 Logic Transistors per Chip (K)

21%/Yr. compound Productivity growth rate

Logic Transistors per Chip (K)

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Impact of Implementation Choices

Flexibility (or application scope)

Digital Integrated Circuits2nd

Standard Cells Compiled Cells

Pre-diffused (Gate Arrays)

Digital Integrated Circuits2nd

The Custom Approach

Digital Integrated Circuits2nd

Transition to Automation and Regular Structures

Intel 4004 (71) Intel 8080 Intel 8085

Cell-based Design (or standard cells)

Routing channel requirements are reduced by presence of more interconnect layers

Digital Integrated Circuits2nd

Standard Cell Example

Digital Integrated Circuits2nd

Standard Cell The New Generation

Cell-structure hidden under interconnect layers

Digital Integrated Circuits2nd

Standard Cell - Example

Digital Integrated Circuits2nd

Automatic Cell Generation

Initial transistor geometries

Digital Integrated Circuits2nd

A Historical Perspective: the PLA

Digital Integrated Circuits2nd

Inverting format (NORNOR) more effective

PLA Layout Exploiting Regularity

Breathing Some New Life in PLAs

Digital Integrated Circuits2nd

Also: RPLAs are regular and predictable

Standard cell, 2 layers channel routing

Standard cell, 3 layers OTC

Network of PLAs, 4 layers OTC

River PLA, 2 layers no additional routing

Digital Integrated Circuits2nd

25632 (or 8192 bit) SRAM Generated by hard-macro module generator

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

A Protocol Processor for Wireless

Semicustom Design Flow

Floorplanning Post-Layout Simulation Circuit Extraction Placement Routing Physical

Tape-out Digital Integrated Circuits2nd

The Design Closure Problem

Iterative Removal of Timing Violations (white lines)

Digital Integrated Circuits2nd

Integrating Synthesis with Physical Design

Pre-diffused (Gate Arrays)

Digital Integrated Circuits2nd

Gate Array Sea-of-gates

rows of uncommitted cells

metal GND possible contact

Committed Cell (4-input NOR)

Digital Integrated Circuits2nd

Sea-of-gate Primitive Cells

Digital Integrated Circuits2nd