Timing Analysis

Elec 326

Sequential Circuit Timing

Why Timing Analysis?

Timing performance of a design Design is free of violations

Elec 326

Sequential Circuit Timing

Two Methods: Static Timing Analysis Method of validating the timing performance of a design by checking all possible paths for timing violations. Dynamic Timing Analysis Determines the full behavior of the circuit for a given set of input stimulus vectors

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Sequential Circuit Timing

Advantages and Disadvantages

Static Timing Analysis + faster because it is not necessary to simulate the logical operation of the circuit + checks all the possible paths

- only check the timing, not the functionality

Dynamic Timing Analysis + can check the timing and the functionality - consumes more run time - dependent on stimulus vectors
Elec 326 Sequential Circuit Timing

When the Timing Analysis is Done?

First - gate-level design placement and routing (accurate delay information or detailed parasitic information) Second - back-annotated the design results in a layout-accurate timing analysis

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Sequential Circuit Timing

Timing Checks performed:

Setup, hold constraints User-specified data-to-data timing constraints Minimum period and minimum pulse width for clocks Design rules (minimum/maximum transition time, capacitance and fan out)

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Sequential Circuit Timing

Static Timing Analysis (Violation Checks)

The tool breaks the design down into a set of

timing paths calculates the signal propagation delay along each path and checks for violations of timing constraints inside the design and at the input/output interface.

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Sequential Circuit Timing

Timing Paths
Each path has a start point and an endpoint.

The start point is a place in the design where data is launched by a clock edge. The data is propagated through combinational logic in the path and then captured at the endpoint by another clock edge.
The start point of a path is a clock pin of a sequential element, or possibly an input port of the design (because the input data can be launched from some external source). The endpoint of a path is a data input pin of a sequential element, or possibly an output port of the design (because the output data can be captured by some external sink).
Elec 326 Sequential Circuit Timing

Timing Paths in Design Compiler

MY_DESIGN A D Q FF1 QB D Q FF2 QB Z

CLK

Each path has a startpoint and an endpoint:

Startpoints
Input ports Clock pins of Flip-Flops or registers

Endpoints
Output ports All input pins except clock pins of sequential devices

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Sequential Circuit Timing

MY_DESIGN A CLK1 CLK2 path1 D Q FF2 QB path2 D Q path3 FF3 QB Z

path4

Timing Paths

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Sequential Circuit Timing

How many timing paths?

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Sequential Circuit Timing

How many timing paths?

Path 1

Path 2

Path 3

Path 4
Path 1 starts at an input port and ends at the data input of a sequential element. Path 2 starts at the clock pin of a sequential element and ends at the data input of a sequential element. Path 3 starts at the clock pin of a sequential element and ends at an output port. Path 4 starts at an input port and ends at an output port.
Elec 326 9/4/2012 Sequential Circuit Timing

Delay Calculation

The total delay of a path is the sum of all cell and net delays in the path Cell Delay Cell delay is the amount of delay from input to output of a logic gate in a path Net Delay Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path

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Sequential Circuit Timing

Constraint Checking
A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device. This constraint enforces a maximum delay on the data path relative to the clock path. A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device after the clock edge that captures the data in the device. This constraint enforces a minimum delay on the data path relative to the clock path.

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Sequential Circuit Timing

Constraint Checking
The amount of time by which a violation is avoided is called the slack. E.g.: for a setup constraint, if a signal must reach a cell input at no later than 8 ns and is determined to arrive at 5 ns, the slack is 3 ns.

A slack of 0 means that the constraint is just barely satisfied.

A negative slack indicates a timing violation.
Elec 326 Sequential Circuit Timing

Timing Exceptions
Paths that are not intended to operate or different.

False path A path that is never sensitized due to the logic configuration, expected data sequence, or operating mode. Multicycle path A path designed to take more than one clock cycle from launch to capture.
Minimum/maximum delay path A path that must meet a delay constraint that you specify explicitly as a time value.
Elec 326 Sequential Circuit Timing

Sequential Circuit Timing

Objectives
Define

the following global timing parameters and show how they can be derived from the basic timing parameters of flip-flops and gates.
Maximum Clock Frequency Maximum allowable clock skew Global Setup and Hold Times

Discuss

ways to control the loading of data into registers and show why gating the clock signal to do this is a poor design practice.

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Sequential Circuit Timing

13.1. Maximum Clock Frequency

The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flipflops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency. Relevant timing parameters

Gates:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL

Flip-Flops:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL Setup time: tsu Hold time: th

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Sequential Circuit Timing

Example
D Q

CK

TW max tPFF + tsu

For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns
TW max (max tPLH + tsu, max tPHL + tsu) TW max (25+20, 40+20) = 60

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Sequential Circuit Timing

Example
D Q

CK

TW max tPFF + max tPINV + tsu

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Sequential Circuit Timing

 Example
D Q Q Q0
0

MUX
1

D Q

Q1

CK

TW max tPFF + max tPMUX + tsu

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Sequential Circuit Timing

 Example

Paths from Q1 to Q1: None Paths from Q1 to Q2: TW max tPDFF +tJKsu = 20 +10 = 30 ns TW max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns Paths from Q2 to Q1: TW max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns Paths from Q2 to Q2: TW max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns

TW 47 ns
Elec 326 Sequential Circuit Timing

Clock Skew

If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be skewed between these flip-flops. The difference between the times of arrival at the flip-flops is said to be the amount of clock skew. Clock skew is due to different delays on different paths from the clock generator to the various flip-flops.
Different length wires (wires have delay) Gates (buffers) on the paths Flip-Flops that clock on different edges (need to invert clock for

some flip-flops)

Gating the clock to control loading of registers

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Sequential Circuit Timing

Example (Effect of clock skew on clock rate)

Clock C2 skewed after C1

Q1 D Q C1 CK
Q

D2 C2

D Q Q

Q2

TW max TPFF + max tOR + tsu (if clock not skewed, i.e., tINV = 0)
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TW max TPFF + max tOR + tsu - min tINV (if clock skewed, i.e., tINV > 0)
Sequential Circuit Timing

Clock C1 skewed after C2

D Q

Q1

D2 C2

D Q Q

Q2

C1 CK

TW max TPFF + max tOR + tsu (if clock not skewed, i.e., tINV = 0) TW max TPFF + max tOR + tsu + max tINV (if clock skewed, i.e., tINV > 0)

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Sequential Circuit Timing

Summary of maximum clock frequency calculations

D Q C1 Q1 Logic Network D2 C2 D Q

TW C1 tSK = tINV C2 Q1 D2 tPFF tOR tsu

TW C1 tSK = tINV C2 Q1 D2 tPFF tOR tsu

C2 skewed after C1: TW max TPFF + max tNET + tsu - min tINV C2 skewed before C1: TW max TPFF + max tNET + tsu + max tINV
Elec 326 Sequential Circuit Timing

Example

tXY = Network delay from X to Y tXD = Network delay from X to D tQY = Network delay from Q to Y tQD = Network delay from Q to D

For each of the following two connections find

The minimum clock period The maximum and minimum delay from CLK to YOUT

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Sequential Circuit Timing

Circuit 1:
n2

t = Netw ork delay from X to Y XY tXD = Netw ork delay from X to D t = Netw ork delay from Q to Y QY t = Netw ork delay from Q to D QD

Minimum Clock Period: Tw max tPFF + max tQY + (n-2) max tXY +max tXD + tsu Tw max tPFF + max tQD + tsu Maximum Delay: TCY max tPFF + max tQY + (n-1) max tXY Minimum Delay: TCY min tPFF + min tQY
Elec 326

TW

Sequential Circuit Timing

Circuit 2:
n2

t = Netw ork delay from X to Y XY tXD = Netw ork delay from X to D t = Netw ork delay from Q to Y QY t = Netw ork delay from Q to D QD

Minimum Clock Period: Tw max tPFF + max tXD + tsu Tw max tPFF + max tQD + tsu Maximum Delay: TCY max tPFF + max (max tXY, max tQY) Minimum Delay: TCY min tPFF + min (min tXY, min tQY)
Elec 326 Sequential Circuit Timing

13.2. Maximum Allowable Clock Skew How much skew between C1 and C2 can be tolerated in the following circuit?
D Q Q

Q1

D2

D Q Q

C1

C2

Case 1: C2 delayed after C1

tPFF > th + tSK

tSK < min tPFF - th

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Sequential Circuit Timing

Case 2: C1 delayed from C2

D Q Q

Q1

D2

D Q Q

C1

C2

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Sequential Circuit Timing

How does additional delay between the flip-flops affect the skew calculations?

tSK min tPFF - th tsk min tPFF + min tMUX - th

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Sequential Circuit Timing

Summary of allowable clock skew calculations

tSK + th tPFF + tNET tSK min tPFF + min tNET - th

Elec 326 Sequential Circuit Timing

Example: What is the minimum clock period for the following circuit under the assumption that the clock C2 is skewed after C1 (i.e., C2 is delayed from C1)?
N2 D1
D Q Q

Q1

N1

D2

D Q Q

Q2

C1

C2

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Sequential Circuit Timing

N2 D1
D Q Q

Q1

N1

D2

D Q Q

Q2

C1

C2

First calculate the maximum allowable clock skew. tSK < min tPFF + min tN1 - th Next calculate the minimum clock period due to the path from Q1 to D2. TW > max tPFF + max tN1 + tsu - min tSK Finally calculate the minimum clock period due to the path from Q2 to D1 TW > max tPFF + max tN2 + tsu + max tSK TW > max tPFF + max tN2 + tsu + (min tPFF + min tN1 - th)

TW > max tPFF + min tPFF + max tN2 + min tN1 + tsu - th
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13.3. Global Setup Time, Hold Time and Propagation Delay

Global setup and hold times (data delayed)
X CLK NET D CK
D Q Q

TSU = tsu + max tNET

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TH = th - min tNET
Sequential Circuit Timing

Global setup & hold time (clock delayed)

D CLK CK
D Q Q

TSU = tsu - min tC

TH = th + max tC
Sequential Circuit Timing

Elec 326

Global setup & hold time (data & clock delayed)

X CLK NET D CK
D Q Q

TSU = tsu + max tNET - min tC

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TH = th - min tNET + max tC

Sequential Circuit Timing

Global propagation delay

D Q

Q NET Y

CLK

CK

TP = tC + tFF + tNET
Elec 326 Sequential Circuit Timing

13.4. Register load control (gating the clock) A very bad way to add a load control signal LD to a register that does not have one is shown below
D LD CLK CK

D Q Q

The reason this is such a bad idea is illustrated by the following timing diagram.

The flip-flop sees two rising edges and will trigger twice. The only one we want is the second one.
Elec 326 Sequential Circuit Timing

 If LD was constrained to only change when the clock was low, then the only problem would be the clock skew.

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Sequential Circuit Timing

If gating the clock is the only way to control the loading of registers, then use the following approach:
D CLK LD

D Q Q

There is still clock skew, but at least we only have one triggering edge.

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Sequential Circuit Timing

The best way to add a LD control signal is as follows:

LD D CLK

D Q Q

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Sequential Circuit Timing