ECE 331 Digital Systems Design

Sequential Logic Circuits:

FSM Design (Mealy) and VHDL Implementation
(Lecture #21)

FSM Design: Procedure

Understand specifications Derive state diagram Create state table Perform state minimization (if necessary)

Encode states (state assignment)

Create state-assigned table Select type of Flip-Flop to use Determine Flip-Flop input equations and FSM output equation(s) Draw circuit diagram
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FSM Design

Mealy Machines

ECE 331 - Digital Systems Design

FSM Design (Mealy)

Example:
Design a FSM that detects a sequence of three or more consecutive ones on an input bit stream.

The FSM should output a 1 when the sequence is detected, and a 0 otherwise.
This is another example of a sequence detector.

ECE 331 - Digital Systems Design

FSM Design: Example (Mealy)

Input:

011101011011101

Output:

000100000000100

ECE 331 - Digital Systems Design

FSM Design: Example (Mealy)

State Diagram
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FSM Design: Example (Moore)

State Diagram

ECE 331 - Digital Systems Design

FSM Design: Example (Mealy)

State Table
Present State w=0 QA A B C D 0 0 1 1 QB 0 1 0 1 A A A QA+ 0 0 0 d QB+ 0 0 0 d B C C Next State w=1 QA+ 0 1 1 d QB+ 1 0 0 d Output w=0 z 0 0 0 d w=1 z 0 0 1 d

Using Binary Encoding for the State Assignment

Next state is a function of the present state and the input

ECE 331 - Digital Systems Design

Output is a function of the present state and the input (Mealy Machine)
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FSM Design: Example (Mealy)

The choice of Flip-Flop determines the complexity of the combinational logic required in the design of the state machine.

Each type of Flip-Flop has a unique characteristic equation.

SR Flip-Flop

JK Flip-Flop

Q+ = S + R'.Q

Q+ = J.Q' + K'.Q

D Flip-Flop

T Flip-Flop

Q+ = D

Q+ = T '.Q + T.Q'

ECE 331 - Digital Systems Design

FSM Design (Mealy)

Synthesis using D Flip-Flops

(Q+ = D)

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FSM Design: Example (Mealy)

Present State QA A B C D 0 0 1 1 QB 0 1 0 1 QA+ 0 0 0 d Next State w=0 QB+ 0 0 0 d 0 1 1 d w=1 QA+ QB+ 1 0 0 d 0 0 0 d w=0 DA DB 0 0 0 d 0 1 1 d FF Inputs w=1 DA DB 1 0 0 d

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FSM Design: Example (Mealy)

Karnaugh Maps
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FSM Design: Example (Mealy)

Karnaugh Maps
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FSM Design: Example (Mealy)

Circuit Diagram
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FSM Design (Mealy)

Synthesis using JK Flip-Flops

(Q+ = J.Q' + K'.Q)

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FSM Design: Example (Mealy)

Q+ +

Excitation Table

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FSM Design: Example (Mealy)

Present State QA A B C 0 0 1 QB 0 1 0 QA+ 0 0 0 Next State w=0 QB+ 0 0 0 0 1 1 w=1 QA+ QB+ 1 0 0 JA 0 0 d d d 1 w=0 KA JB 0 d 0 KB d 1 d JA 0 1 d d d 0 FF Inputs w=1 KA JB 1 d 0 KB d 1 d

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FSM Design: Example (Mealy)

Karnaugh Maps
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FSM Design: Example (Mealy)

Circuit Diagram
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FSM Design (Mealy)

Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should not be detected.
This is another example of a sequence detector.
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FSM Design: Example (Mealy)

Input (w): 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1

Output (z): 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0

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FSM Design: Example (Mealy)

State Diagram
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FSM Design (Mealy)

Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
This is another example of a sequence detector.
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FSM Design: Example (Mealy)

Input (w): 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1

Output (z): 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0

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FSM Design: Example (Mealy)

State Diagram
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FSM Design (Mealy)

Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 010 or the pattern 110 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
This is example of a sequence detector that can detect 2 sequences.
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FSM Design: Example (Mealy)

Input (w): 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1

Output (z): 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0

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FSM Design: Example (Mealy)

State Diagram
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VHDL Implementation of Finite State Machines

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FSMs in VHDL

VHDL does not define a standard method for describing a Finite State Machine. Consequently, there is more than one way to describe a given FSM.

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FSMs in VHDL

Example #1

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Example: State Diagram

Reset w = 1

w = 0

A = 0 z w = 0 w = 0

B = 0 z

w = 1

C = 1 z

w = 1

What type of state machine is this?

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FSM in VHDL (Moore)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY moore IS PORT ( Clock, Resetn, w z END moore ;

: IN : OUT

STD_LOGIC ; STD_LOGIC ) ;

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Create a user-defined signal type.

y represents the state flip-flops

Process statement describes the FSM as a sequential circuit.

7 ARCHITECTURE Behavior OF moore IS VHDL compiler automatically 8 TYPE State_type IS (A, B, C) ; determines the correct number 9 SIGNAL y : State_type ; of state flip-flops required. 10 BEGIN 11 PROCESS ( Resetn, Clock ) Sensitivity list 12 BEGIN Reset is asynchronous 13 IF Resetn = '0' THEN 14 y <= A ; 15 ELSIF (Clock'EVENT AND Clock = '1') THEN 16 CASE y IS Positive edge-triggered 17 WHEN A => 18 IF w = '0' THEN 19 y <= A ; 20 ELSE The Case statement describes 21 y <= B ; the behavior of the FSM. 22 END IF ; 23 WHEN B => Each When clause represents 24 IF w = '0' THEN one state in the FSM. 25 y <= A ; 26 ELSE 27 y <= C ; The When clauses correspond 28 END IF ; to the states in the state diagram. 29 WHEN C => 30 IF w = '0' THEN 31 y <= A ; 32 ELSE 33 y <= C ; 34 END IF ; 35 END CASE ; 36 END IF ; 37 END PROCESS ; 38 z <= '1' WHEN y = C ELSE '0' ; Output specified. 39 END Behavior ;

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FSMs in VHDL

Example #2

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Example: State Diagram

Reset w = 1 = 0 z w = 0 = 0 z w = 1 = 1 z

w = 0 = 0 z

What type of state machine is this?

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FSM in VHDL (Mealy)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS PORT ( Clock, Resetn, w : z : END mealy ;

IN OUT

STD_LOGIC ; STD_LOGIC ) ;

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Create a user-defined signal type.

ARCHITECTURE Behavior OF mealy IS VHDL compiler automatically TYPE State_type IS (A, B) ; determines the correct number SIGNAL y : State_type ; of state flip-flops required. BEGIN PROCESS ( Resetn, Clock ) Sensitivity list BEGIN IF Resetn = '0' THEN Reset is asynchronous y represents the y <= A ; state flip-flops ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => Positive edge-triggered Process statement IF w = '0' THEN y <= A ; describes the FSM ELSE y <= B ; as a sequential circuit. END IF ; This Case statement describes WHEN B => the behavior of the FSM. IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ;

PROCESS ( y, w ) BEGIN CASE y IS WHEN A => Why is the output z <= '0' ; described in a separate WHEN B => Process statement? z <= w ; END CASE ; END PROCESS ; END Behavior ;

This Case statement describes the behavior of the output.

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Acknowledgments

The slides used in this lecture were taken, with permission, from those provided by McGraw-Hill for Fundamentals of Digital Logic with VHDL Design (3rd Edition). They are the property of and are copyrighted by McGraw-Hill Higher Education.

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