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1. Introduction 2. Partially Depleted (PD) SOI 3. Parasitic Bipolar Effect 4. Major Design Issue 5. Double Gate MOSFET 6. Features Of FINFET 7. Application 8. Conclusion
Introduction
The FinFET is a double gate device, one of a number of geometries being introduced to multigate devices, the effects of short channel & reduce drain induced barrier lowering. FinFET are design to use multiple fins to achieve larger channel width. Source/Drain pads contacts, the fin is parallel. As the Fin increased the current through the device increases. E.g. A 5 Fin device has 5 times more current than single Fin device.
Si Fin
Schematic Diagram
Schematic explaining the parts of a FinFET
Histeretic Vt Variation
The hysteretic VT variation due to long time constants of various body charging/discharging mechanisms. A commonly used gauge for hysteretic VT variation is the disparity in the body voltages and delays between the so-called first switch(i/p low) and second switch(o/p high) .
As the channel length of an FET is reduced, the drain potential begins to strongly influence the channel potential
further decrease of the depletion region XD degrades gate influence on the channel and leads to a slower turn on of the channel region
Featurs Of FinFETS
Main Features of Finfet are 1. Ultra thin Si fin for suppression of short channel effects 2. Raised source/drain to reduce parasitic resistance and improve currrent drive 3. Gate_last process with low_T,high_k gate dielectrics 4. Symmetric gates yield great performance,but can built asymmetric gates that target VT
Application
DG devices like Fin FETs offer unique opportunities for microprocessor design. FinFETs have reduced channel and gate leakage currents. - power reductions when converting a planar design to fin FET technology. - Utilizing fin FETs would lead to a reduction in total power, without compromising performance. Another possibility to save power arises when both gates can be controlled separately. The second gate can be used to control the threshold voltage of the device, thereby allowing fast switching on one side and reduced leakage currents when circuits are idle.
Conclusions
FinFETs a necessary semiconductor evolution step because of bulk CMOS scaling problems beyond 32nm. Structure was fabricated by forming the S/D before the gate. Use of the FinFET back gate leads to very interesting design opportunities Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption. Time has arrived to start exploring the architectural trade-offs made possible by switch to FinFETs.