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El ejercicio desarrollado a continuacin, esta propuesto en el libro FPGA PROTOTYPING BY EXAMPLES. Pong P. Chu. Corresponde al problema 5.5.3, pag. 125.
Diagrama de estados
10
01 00 10 B 10 11
A 00 10 01 00 11 01 C D 01
11
SA SB
7 0
Instancia 1 Sensor_A
FSM DB
4
Sensor_B
FSM DB
Instancia 2
4
4
ENTITY DPLDRV IS PORT ( CLK50M : IN STD_LOGIC; DIGITO0 : IN STD_LOGIC_VECTOR (3 DOWNTO 0); --Digito del display de las unidades DIGITO1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0); --Digito del display de las decenas DIGITO2 : IN STD_LOGIC_VECTOR (3 DOWNTO 0); --Digito del display de las centenas -DIGITO3 : IN INTEGER RANGE 0 TO 8; --Digito del display de las millar DPL_ENABLE : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0); DPL_SEG : INOUT STD_LOGIC_VECTOR (0 TO 7) ); END DPLDRV;
Arquitectura DPLDRV
Cdigo aportado por Adrian Costa Ospino
ARCHITECTURE BEHAVIORAL OF DPLDRV IS SIGNAL DIGITO : INTEGER RANGE 0 TO 15:=0; SIGNAL POS_DISPLAY : INTEGER RANGE 0 TO 3:=0; SIGNAL DELAY : STD_LOGIC_VECTOR (13 DOWNTO 0); BEGIN DPL_ENABLE <= "1110" WHEN (POS_DISPLAY = 0) ELSE "1101" WHEN (POS_DISPLAY = 1) ELSE "1011" WHEN (POS_DISPLAY = 2) ELSE "0111"; DIGITO <= DIGITO0 WHEN (POS_DISPLAY = 0) ELSE DIGITO1 WHEN (POS_DISPLAY = 1) ELSE DIGITO2 WHEN (POS_DISPLAY = 2) ELSE DIGITO3; DPL_SEG <= "0000001" WHEN (DIGITO=0) ELSE "1001111" WHEN (DIGITO=1) ELSE "0010010" WHEN (DIGITO=2) ELSE "0000110" WHEN (DIGITO=3) ELSE "1001100" WHEN (DIGITO=4) ELSE "0100100" WHEN (DIGITO=5) ELSE "0100000" WHEN (DIGITO=6) ELSE "0001111" WHEN (DIGITO=7) ELSE "0000000" WHEN (DIGITO=8) ELSE "0000100" WHEN (DIGITO=9) ELSE "1111111"; PROCESS (CLK50M) BEGIN IF (CLK50M'EVENT AND CLK50M='1') THEN DELAY <= DELAY+1; IF ( DELAY="11111111111111" ) THEN POS_DISPLAY <= POS_DISPLAY+1; END IF; END IF; END PROCESS; END BEHAVIORAL;
entity DB_FSM is Port ( clk : in STD_LOGIC; sw : in STD_LOGIC; db : inout STD_LOGIC); end DB_FSM;
process (state_reg, sw, m_db) begin state_next <= state_reg; db <= '0'; case state_reg is when zero => if sw = '1' then state_next <= wait1_1; end if; when wait1_1 => if sw = '0' then state_next <= zero; else if m_db = '1' then state_next <= wait1_2; end if; end if; when wait1_2 => if sw = '0' then state_next <= zero; else if m_db = '1' then state_next <= wait1_3; end if; end if; when wait1_3 => if sw = '0' then state_next <= zero; else if m_db = '1' then state_next <= one; end if; end if; when one => db <= '1'; if sw = '0' then state_next <= wait1_1; end if; when wait0_1 => db <= '1'; if sw = '1' then state_next <= one; else if m_db = '1' then state_next <= wait0_2; end if; end if; when wait0_2 => db <= '1'; if sw = '1' then state_next <= one; else if m_db = '1' then state_next <= wait0_3; end if; end if; when wait0_3 => db <= '1'; if sw = '1' then state_next <= one; else if m_db = '1' then state_next <= zero; end if; end if; end case; end process; end Behavioral;
entity CuentaAutos_vhd is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; sens_a : in STD_LOGIC; sens_b : in STD_LOGIC; cuenta : inout STD_LOGIC_VECTOR (7 DOWNTO 0) ); end CuentaAutos_vhd;
architecture Behavioral of CuentaAutos_vhd is type estados is (edo_a, edo_b, edo_c, edo_d); signal state_act, state_sig, state_prev, state_aux: estados := edo_a; signal cont, contact: STD_LOGIC_VECTOR(7 downto 0):=(others=> '0'); signal sensor_A, sensor_B: STD_LOGIC; begin Antirebote_1: entity work.DB_FSM(behavioral) port map (sw => Sens_A, clk => clk, db=>sensor_A ); Antirebote_2: entity work.DB_FSM(behavioral) port map (sw => Sens_B, clk => clk, db=>sensor_B ); -- state register process (clk, RST) begin if(RST='1') then state_act <= edo_a; state_aux <= edo_a; contact <= (others => '0'); elsif (clk'event and clk='1') then state_act <= state_sig; state_aux <=state_prev; contact<=cont ; end if; end process;
ENTITY BYTE2BCD IS PORT ( BYTE : INOUT STD_LOGIC_VECTOR (7 DIGITO0 : INOUT STD_LOGIC_VECTOR DIGITO1 : INOUT STD_LOGIC_VECTOR DIGITO2 : INOUT STD_LOGIC_VECTOR END BYTE2BCD;
Arquitectura BYTE2BCD
Cdigo aportado por Adrian Costa Ospino
ARCHITECTURE BEHAVIORAL OF BYTE2BCD IS SIGNAL DU0 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DU1 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DU2 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DU3 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DU4 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DU5 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DD0 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DD1 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DD2 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL DC0 : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); BEGIN --UNIDADES. DU0 <= '0'&BYTE(7 DOWNTO 5) WHEN (BYTE(7 DOWNTO 5)<5) ELSE '0'&BYTE(7 DOWNTO 5)+3; DU1 <= DU0(2 DOWNTO 0)&BYTE(4) WHEN ( (DU0(2 DOWNTO 0)&BYTE(4))<5 ) ELSE DU0(2 DOWNTO 0)&BYTE(4)+3; DU2 <= DU1(2 DOWNTO 0)&BYTE(3) WHEN ( (DU1(2 DOWNTO 0)&BYTE(3))<5 ) ELSE DU1(2 DOWNTO 0)&BYTE(3)+3; DU3 <= DU2(2 DOWNTO 0)&BYTE(2) WHEN ( (DU2(2 DOWNTO 0)&BYTE(2))<5 ) ELSE DU2(2 DOWNTO 0)&BYTE(2)+3; DU4 <= DU3(2 DOWNTO 0)&BYTE(1) WHEN ( (DU3(2 DOWNTO 0)&BYTE(1))<5 ) ELSE DU3(2 DOWNTO 0)&BYTE(1)+3; DU5 <= DU4(2 DOWNTO 0)&BYTE(0); --DECENAS. DD0 <= '0'&DU0(3)&DU1(3)&DU2(3) WHEN ( (DU0(3)&DU1(3)&DU2(3))<5 ) ELSE '0'&DU0(3)&DU1(3)&DU2(3)+3; DD1 <= DD0(2)&DD0(1)&DD0(0)&DU3(3) WHEN ( (DD0(2)&DD0(1)&DD0(0)&DU3(3))<5 ) ELSE DD0(2)&DD0(1)&DD0(0)&DU3(3)+3; DD2 <= DD1(2)&DD1(1)&DD1(0)&DU4(3); --CENTENAS. DC0 <= '0'&'0'&DD0(3)&DD1(3); DIGITO0 <= DU5; DIGITO1 <= DD2; DIGITO2 <= DC0; -- DIGITO0 <= CONV_INTEGER(DU5); -- DIGITO1 <= CONV_INTEGER(DD2); -- DIGITO2 <= CONV_INTEGER(DC0); -DIGITO3 <= CONV_INTEGER(PRBDATA); END BEHAVIORAL;
rst: in STD_LOGIC;
SA : in STD_LOGIC; SB : in STD_LOGIC; clk: in STD_LOGIC; Led: out STD_LOGIC_VECTOR (7 downto 0); anodos: out STD_LOGIC_VECTOR (3 downto 0); segmentos: out STD_LOGIC_VECTOR (0 to 7)
); end Estacionamiento;
Signal C : STD_LOGIC_VECTOR (7 downto 0); Signal Seg : STD_LOGIC_VECTOR (7 downto 0); Signal AComun : STD_LOGIC_VECTOR (3 downto 0);
Begin
FSM: CuentaAutos_vhd port map (rst => rst, sens_a => SA, sens_b => SB, clk=> clk, cuenta => C ); Deco7seg: Binario2Display port map (Byte => C, CLK => clk, Enable =>AComun, Segmentos => Seg); segmentos <= Seg; anodos <= AComun; Led <= C;
end Behavioral;