MICROPROCESSORS

Sayyan.Shaikh

Basic Computer System

MEM CPU I/O Buses Peripherals

The Microprocessor

The silicon chip that contains the CPU where most calculations take place Microprocessors are distinguished by 3 characteristics Instruction set: the set of instructions that the microprocessor can execute Bandwidth: the number of bits processed in each instruction Clock speed: (MHz) It determines how many instructions/second the processor can execute

Role of The Microprocessor

Fetch the Instruction from the memory Fetch the operands of the Instruction Decode the Instruction Execute the Instruction Output the results
CPU continuously does the (Fetch-Decode-Execute) Cycle

Microprocessor Architecture
Basic Components

CPU Registers special memory locations constructed from flip-flops and implemented on-chip e.g., accumulator, count register, flag register Arithmetic and Logic Unit (ALU) ALU is where most of the action take place inside the CPU

Microprocessor Architecture
Instruction processing
Fetch 1

Fetch 2

Fetch 3

Fetch 4

Store 1

Fetch 5

Fetch 6

Read 2

Fetch 7

Bus Unit

Decode 1

Decode 2

Decode 3

Decode 4

Idle

Decode 5

Decode 6

Idle

Instruction Unit

Execute 1

Execute 2

Execute 3

Execute 4

Idle

Execute 5

Execute 6

Execution Unit

Generate Address 1

Generate Address 2

Address Unit

Intel x86 Microprocessors

8086 - 20 bit Addr. Bus - 1MB of Memory 80286 - 24 Addr. Bus - Added Protection Mode

80386 - 32 bit regs/busses - Virtual 86 Mode

80486 - RISC Core - L1 Cache - FPU Pentium - Superscalar - Dual Pipeline - Split L1 Cache Pentium Pro - L2 Cache - Branch Pred. - Speculative Exec. Pentium MMX - 57 Instructions - Integrated DSP (MMX) Pentium II - 100 MHz Bus - L2 Cache - MMX Celeron - 66 MHz Bus - True L2 Cache Integration Pentium III - 100 MHz Bus - 70 Internet Streaming SIMD Ext.

Name 8080 8088 80286 80386 80486 Pentium

Date 1974 1979 1982 1985 1989 1993

Transi stors Micron s 6,000 29,000 134,000 275,000 1,200, 000 3,100, 000 6 3 1.5 1.5 1 0.8

Clock speed 2 MHz 5 MHz 6 MHz 16 MHz 25 MHz 60 MHz

Data width 8 bits 16 bits 8-bit bus 16 bits 32 bits 32 bits 32 bits 64-bit bus 32 bits 64-bit bus 32 bits 64-bit bus 32 bits 64-bit bus 32 bits 64-bit bus

MIPS 0.64 0.33 1 5 20 100

Pentium II

1997

7,500, 000

0.35

233 MHz 450 MHz

~300

Pentium III

1999

9,500, 000

0.25

~510

Pentium 4

2000

42,000,000

0.18

1.5 GHz

~1,700

Pentium 4 "Prescott"

2004 125,000,000

0.09

3.6 GHz

~7,000

History of Intels Microprocessors Intel 4004 1971, 4-bit Intel 8008 1972, 8-bit Originally designed for Datapoint Corp. as a CRT display controller Intel 8080 1974, April - Altair 8800, 1975, MITS( 256 bytes of Mem, $395) Apple II -- Steve Jobs and Steve Wozniak 1976, Apple Bill Gates and a fellow student : BASIC, 1975 --> Microsoft Intel 8086/8088 1978, 16 bit: 8088, 1979, 8-bit external bus

 IBM PC ; 1981 29,000 Trs Intel 80286 1982, 16-bit architecture 24-bit addressing, memory protection and virtual memory 16 MB of physical MEM and 1 GB of virtual mem 130,000 Trs onto a single chip IBM PC/AT in 1984, IBM PS/2 Model 50 and 60 Intel 80386 1985, 32 bits 3~5 MIPS (7 MIPS on the 25 MHz chip) memory paging and enhanced I/O permission features 4GB programming model

 Intel 80486 1989 Spring COMDEX show -> 1990 June : actual release 1,200,000 Trs 386+387+8K data and instruction cache, paging and MMU Pentium 1993 110 MIPS on 66 Mhz Chip 16 KB on-chip cache and 64 bit data bus superscalar technology (two instructions/clock) 3.1 million transistors

 Pentium Pro 1995, Superscalar(three-way issue) 5.5 million Trs in the CPU core + 15.5 million Trs in the secondary cache 8K data, 8K instr cache 256 KB SRAM secondary cache 200 SPECint92 at 133 MHz 2.9 V, 0.6 micron BICMOS Pentium II Pentium Pro + MMX, 1997 233, 266, upto 450 MHz 7.5 million Trs in CPU 512KB in secondary cache

 Pentium III
1999 Pentium Pro + MMX + Internet Streaming SIMD Instructions 0.25 micron, 9.5 million Trs 600 MHz, 550 MHz,... 32 K(16K/16K) non-blocking level 1 cache

Processor Data and Address Bus Sizes Examples

Processor 8088 8086 80286 80386dx 80486 80586/Pentium (Pro)

Data Bus 8 16 16 32 32 64

Address Bus 20 20 24 32 32 32

Max Addressable Memory 1,048,576 1,048,576 16,777,21 4,294,976,296 4,294,976,296 4,294,976,296 (1Mb) (1Mb) (16Mb) (4Gb) (4Gb) (4Gb)

Intel
4004 to Pentium.ItaniumDual core Core 2 duo 8031/51,8951, 8751 etc Microcontrollers

Motorola
6800,68000, 68010/20/30/etc.. 6811/12/13 etc Microcontrollers

Zilog
Z80

AMD And so many.

Intel 8086/8088 Microprocessors

Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC compatible computers (8086 introduced in 1978, first IBM-PC released in 1981) All Intel, AMD and other advanced microprocessors are based on and are compatible with the original 8086/8

Intel 8086/8088 Microprocessors

Intel 8086 is a 16b microprocessor: 16b data registers, 16b ALU Width of external data bus: 8086: 16b 8088: 8b Width of external address bus: 16b+4b=20b Some techniques to optimise the CPU performance when its executing programs Segment: Offset memory model Little-Endian Data Format

MICROPROCESSORS

8086/8088 Functional Units

Execution Unit (EU)

Bus Interface Unit(BIU) Fetches Opcodes, Reads Operands, Writes Data

8086/8088 MPU

System Architecture
A19 Address Bus

Address Bus provides a memory address to system memory and I/O address to system I/O devices Data Bus transfers data between the microprocessor and the memory and I/O attached to the system Control Bus provides control signals that cause memory or I/O devices to perform a read or write operation

A0

8086 System

D15 Data Bus (16 bit) D0

To memory and I/O

Control Bus

RD/WR Memory I/O

AX, BX, CX, DX

General Purpose Registers
7 0 7 0

Accumulator Base Counter Data

AH BH CH DH

AL BL CL DL

AX BX CX DX

Can Be Used Separately as 1-byte Registers AX = AH:AL Temporary Storage to Avoid Memory Access Faster Execution Avoids Memory Access Some Special uses for Certain Instructions

AX, BX, CX, DX - Some Specialized Uses

7 0 7 0

Accumulator Base Counter Data

AH BH CH DH

AL BL CL DL

AX BX CX DX

AX, Accumulator Main Register for Performing Arithmetic mult/div must use AH, AL accumulator Means Register with Simple ALU BX, Base Point to Translation Table in Memory Holds Memory Offsets; Function Calls CX, Counter Index Counter for Loop Control DX, Data After Integer Division Execution - Holds Remainder

Intel 8086/8088 Microprocessors

Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC compatible computers (8086 introduced in 1978, first IBM-PC released in 1981) All Intel, AMD and other advanced microprocessors are based on and are compatible with the original 8086/8

Intel 8086/8088 Microprocessors

Intel 8086 is a 16b microprocessor: 16b data registers, 16b ALU Width of external data bus: 8086: 16b 8088: 8b Width of external address bus: 16b+4b=20b Some techniques to optimise the CPU performance when its executing programs Segment: Offset memory model Little-Endian Data Format

8086/8088 (3)

8086/8088 consists of two internal units The execution unit (EU) - executes the instructions The bus interface unit (BIU) - fetches instructions, reads operands and writes results The 8086 has a 6B prefetch queue The 8088 has a 4B prefetch queue

Segment:Offset Address
Logical Address is specified as segment:offset Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address Thus the physical address of the logical address A4FB:4872 is A4FB0 + 4872 A9822

Memory Addressing

Generation of 20-bit linear address from a segment:offset address in the real mode, each segment register (16 bits) is internally appended with a 0h on its rightmost end (i.e., the segment is shifted left by 4 bits) The segment and the offset are then added to form 20-bit memory address.

8086/8088 20-bit Addresses

CS 16-bit Segnment Base Address 0000

IP 16-bit Offset Address

20-bit Physical Address

Memory Addressing Examples

(1) Linear address for Segment:Offset = 2222:3333 = 25553 Segment:offset address for Linear address=25553: Many Answers - One possibility: 2222:3333 Many Answers - One possibility: 2000:5553

Memory Addressing Examples

(2) Linear address for Segment:Offset = 1200:F445 = 21445 Segment:offset address for Linear address=21445: Many Answers - One possibility: 1200:F445 Many Answers - One possibility 2000:1445

The 8086 A Microcomputer CPU

MICROPROCESSORS

Flags

15

x OF DF IF TF SF ZF x AF x PF x CF

Status and Control Bits Maintained in Flags Register Generally Set and Tested Individually
9 1-bit flags in 8086; 7 are unused

CF

Carry Flag

Arithmetic Carry/Borrow

OF
ZF SF PF AF DF IF TF

Overflow Flag
Zero Flag Sign Flag Parity Flag Auxiliary Carry Direction Flag Interrupt Flag Trap Flag

Arithmetic Overflow
Zero Result; Equal Compare Negative Result; Non-Equal Compare Even Number of 1 bits Used with BCD Arithmetic Auto-Increment/Decrement Enables Interrupts Allows Single-Step

used for string operations allows fetch-execute to be interrupted for debugging; causes interrupt after each operation

Flags

An example 1010 1100 0011 01012 1010 0101 0101 10102 ---------------------------------------1) 0 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 2 CF = 1 ; PF = 0 ; AF = 0 ; ZF = 0 ; SF = 0 ; OF = 1

Advantages of Segmentation ?

Though the memory capacity is 1MB ( 20 bit address), 8086 need to manipulate and store 16 bit address only. It can have distinct portion of memory block for data/code/stack etc. Separate block ensures non overlapped data/code. Time shared microcomputer system. several users share a CPU. CPU works for one users program for say 20ms. Each time CPU must switch from one user code to another. CPU just needs to change the segment registers content, and it is easy. RELOCATABILITYwonderful. A re-locatable program is one that can be placed into any area of memory and executed with out change ( without recompiling).

Advantages of Segmentation ? If no segmentation .Say 8085 CPU 0000

; MAIN PROGRAM 1 8000 MOV . 23 8001 SUB CD,AB 8003 BACK: ADD 4D,22 .. .. .. .. .. .. 8010 JMP BACK CD,03,80 8011 8012 ------------------------------------------------------------------------------------------; MAIN PROGRAM 2 9000 MOV . 23 9001 SUB CD,AB 9003 BACK: ADD 4D,22 .. .. .. .. .. .. 9010 JMP BACK CD,03,90 9011 9012

MEMORY
FFFF

Advantages of Segmentation ?
If segmentation 00000
;MAIN PROGRAM 1.. PHY CS : IP 12000, 1200 : 0000 MOV . 23 12001, 1200 : 0001 SUB CD,AB 12003, 1200 : 0003 BACK: ADD 4D,22 .. .. .. .. .. .. 12010, 1200 : 0010 JMP BACK CD,03,00 12011, 1200 : 0011 12012, 1200 : 0012 ------------------------------------------------------------------------------------------;MAIN PROGRAM 2.. PHY CS : IP 13000, 1300 : 0000 MOV . 23 13001, 1300 : 0001 SUB CD,AB 13003, 1300 : 0003 BACK: ADD 4D,22 .. .. .. .. .. .. 13010, 1300 : 0010 JMP BACK CD,03,00 13011, 1300 : 0011 13012, 1300 : 0012

MEMORY
FFFFF

Instruction formats
Advantages of Segmentation ?

Instruction formats
Programming Languages Machine Language Assembly Language

Statement format
OP CODE FIELD OPERAND FIELD COMMENT FIELD

LABEL FIELD

NEXT:

ADD

AL,07H

;ADD CORRECTION FACTOR

High Level Language

The instructions vary form 1 to 6 bytes in length.

Opcode (6) D (1) W (1) MOD (2) REG (3) R/M (3) Low Disp(8) High Disp(8) Low Data(8) High Data(8)

D - Direction, Reg. Is a source or dest. W - Indicates a byte (0), or word (1) access REG register field R/M reg or memory (pointed by which pointer register ?) Disp and Data : part of instruction

What is Hand Coding / Manual Assembly ?

Examples: MOV AL,BL Opcode: 100010 D=0 or 1 say 0 REG= BL=011 say 1 REG= AL=000 W=0 byte access MOD=Register mode 11 without disp R/M=011 (BL) So. 1000 10 0 0 11 011 000 = 88 08 H 1000 10 1 0 11 000 011 = 8A C3H

What is Hand Coding / Manual Assembly ?

Examples: ADD AX,[SI] Opcode = 0000 00 D=1 (to reg AX=000) W=1 REG=000 MOD=00 R/M=100 0000 00 1 1 00 000 100 = 03 04H

What is Hand Coding / Manual Assembly ?

Examples: ADD AL,[ABCDh] Opcode=0000 00 D=1 REG=000 W=0 MOD=00 R/M=110 3rd byte CD 4th byte AB 0000 00 1 0 00 000 110 1100 1101 1010 1011 =02 06 CD AB

What is Hand Coding / Manual Assembly ?

Examples: ADD [BX][DI]+DISP , AX Opcode 0000 00 D= 0 W=1 MOD= 10 REG =000 R/M=001 0000 00 0 1 10 000 001 0011 0100 0001 0010 = 01 81 34 12 H

What is Hand Coding / Manual Assembly ?

Examples: MOV [BP][DI]+1234h , ABCDh Opcode 1100 011 (opcode is 7 bit no D bit) W=1 REG=000 (same for amy immediate and R/M) MOD=10 R/M=011 1100 011 1 10 000 011 ,34, 12, CD, AB C7 83 ,34,12,CD,AB a 6 byte instruction

Addressing Modes

The way in which operand or effective address of operand in memory is specified is called addressing modes. More addressing.more convenient to write the program In other words there will be more way to write the program Complexity of processor is more. 8086 has many addressing modes A given data can be accessed using many ways

Let us see one by one now

Immediate Addressing Mode Data/Source operand is a part of the instruction which may be 8/16 bit in length. Doesnt involve the computation of EA
OPCODE(8) DATA(8)

Ex: MOV AL,15H MOV BX,1234H MOV CX,1234 etc

Direct Addressing Mode The 16 bit address of the data is part of the instruction

OPCODE(8)

EA(16)

Ex:
MOV CX,[1050H] MOV BX,[BETA]

PA =

CS DS ES SS

: Direct Address

Implicit /Implied Addressing Mode In this the instruction assumes that data is in a predefined register. Zero address instruction !.
OPCODE(8)

Ex:
CMC, STD, CLC, CLD, etc

Register Addressing Mode The EA of the operand is specified in some register like BX,BP,SI,DI DS segment register is default most of the time
OPCODE(8) REG

EA

DATA

say SI= 1000h DS= 2000h PA= 20000 +1000 = 21000 h

MOV AX , [SI]

So the content of 21000 h is to AX More clearly content of 21000 an 21001 is to AX .

Based Addressing Mode The PA of the operand is obtained by adding a direct or indirect displacement to the content of either BX or BP and the current value of DS or SS respectively.
OPCODE(8) BASE REG

EA

DATA

say

BX= 1234h DS= 2000h PA= 20000 +1234 = 21234 h

MOV [BX] , AL

So the content of AL is transferred to 21234 h

Based Relative Addressing Mode The PA of the operand is obtained by adding a direct or indirect displacement to the content of either BX or BP and the current value of DS or SS respectively.
OPCODE(8)

BASE REG

DISP 8/16

EA

DATA MOV [BX] +ARRAY , AL

say BX= 1234h ARRAY=2345h DS= 2000h PA= 20000 +1234 +2345h= 23579 h

So the content of AL is transferred to 23579 h

Indexed Addressing Mode Operand is read from EA which is the sum of index register and some 8/16 bit displacement and segment base ( shifted base address ).
DISP

OPCODE(8)

INDEX REG

EA

DATA

say MOV AL, [SI]+ALPHA

Based-Indexed Addressing Mode

OPCODE(8)

BASEREG

INDEX REG

DISP

EA

DATA

say MOV AL , [BX] [SI] + BETA

PA = CS / DS / ES / SS : BX / BP + SI / DI + 8 / 16 Displacement / symbol indicates or CS or DS or ES or etc..

String related I/O related IP relative (more popular as PC relative)

Intrasegment

Direct Indirect

; JMP or CALL instructions

Intersegment

Direct ; JMP or CALL instructions Indirect

Direct program memory addressing ; often called far JMP ex: JMP [10000H] ; EA 00 00 (offset) 00 10 (segment) Relative program memory addressing ; (to IP i.e intrasegment) Indirect program memory addressing ; short / near / far type of CALL or JMP

indirect program memory addressig ; All jmps to current code seg. JMP AX JMP CX JMP NEAR PTR [BX] ; THE JUMP ADDRESS IS IN DATA SEGMENT ! ; POINTED BY BX JMP NEAR PTR [DI+2] JMP TABLE [BX] Relative program memory addressing JMP [02] 10000 EB 10001 02 nxt instn 10002 op nxt instn 10003 op

JMP TABLE[BX] TABLE DW DW DW DW LOC0 LOC1 LOC2 LOC4

MOV BX,4 JMP TABLE[BX]

STACK MEMORY ADDRESSING PUSH INSTRUCTIONS SP-1 HIGHER SP-2 LOWER BYTE POP INSTRUCTIONS

TYPE

INSTRUCTION

SOURCE

ADDRESS GENERATION

DESTINATION

Register

MOV AX, BX

Register BX Data 3AH

Register AX

Immediate

MOV CH, 3AH

Register CH

Direct

MOV [1234H], AX

Register AX

DS x 10H +DISP i.e. 10000H+1234H

Memory Address 11234H

Register Indirect

MOV [BX], CL

Register CL
Register BP

DS x 10H +BX i.e. 10000H+0300H

Memory Address 10300H

Memory Address 10500H

Base + Index

MOV [BX+SI], BP

DS x 10H +BX+SI i.e. 10000H+0300H+0200H

Register Relative

MOV CL, [BX+4]

Memory address 10304H

Register DX

DS x 10H +BX+4 i.e. 10000H+0300H+4

Register CL

Base Relative + Index

MOV ARRAY [BX+SI],DX

DS x 10H +ARRAY+BX+SI i.e. 10000H+1000+0300H+0200H

Memory Address 11500H

DS = 1000H, ARRAY = 1000H

Examples:Addressing Modes

Register MOV AL,BL MOV CH,CL MOV AX,CX MOV SP,BP MOV DS,AX MOV SI,DI MOV BX,ES MOV DS,CX MOV ES,DS MOV BL,DX MOV CX,AX

; NOT ALLOWED ; NOT ALLOWED ; NOT ALLOWED

Examples:Addressing Modes

Immediate MOV AL,44 MOV SI,0 MOV AX,44h MOV CH,100 MOV AL,A MOV AX,AB MOV CL,11001110B

Examples:Addressing Modes

Direct MOV AL,NUMBER MOV AX,COW MOV NEWS,AL MOV THERE,AX

MOV CH, [1234H] ; NUMERIC OFFSET IS RARELY USED. MOV NUMBER,SP

Examples:Addressing Modes

Register Indirect MOV CX,[BX] MOV [BP],DL MOV [DI],BH MOV [DI],BX MOV AL,[BX]

Examples:Addressing Modes

Base + Index MOV CX,[BX+DI] MOV CH,[BP+SI] MOV [BX+SI],SP MOV [BP+SI],BX MOV [BP+DI],AL

Examples:Addressing Modes

Register Relative MOV AX,[SI+100h] MOV ARRAY[SI],BL MOV LIST[SI+2],CL MOV DI,SET_IT[BX]

Examples:Addressing Modes

Base Relative + Index MOV DH,[BX+DI+20H] MOV AX,FILE[BX+DI] MOV LIST[BP+DI],CL MOV LIST[BP+SI+4],DH

Session IV

Assembly Process. Assembler: Is a program that accepts an assembly language program as input and converts it into an object module and prepares for loading the program into memory for execution. Assembly Language must have non executable statements to pre assign values, reserve storage, assign names to constants, form data structures and terminate a compilation, are all called directives.

Source program

ASSEMBLER

Object module

Linker: Converts the object module prepared by the assembler into executable form, by linking it with other object modules and library modules.

Object module

LINKER

Executable module

Loader: The final executable map of the assembly language program is prepared by the loader at the time of loading into the primary memory for actual execution. physically loads it into the memory. Locator: Makes room for the machine files in primary memory.

2 Pass Assembler

Pass1: Analyze the program to be converted. Defines and records the symbols, pseudo operands and directives. It also analyses the segments used by the program types and labels and their memory requirements. Pass 2: Looks for the addresses and data assigned to the labels. It also finds out codes of the instructions from the instruction machine, code database and the program data.

Assembler Directives

They are commands to the assembler. They are required only during assembly process. They are not machine coded. They are also called as pseudo operations, that controls the assembly process. tiny, small, large etc are the assembler memory model tiny means one segment model .COM format small indicates two segment model one data and one code

Assembler Directives
DB DW DD DQ

define byte ; each data item occupies one byte define word ; each data item occupies 2 bytes define double word ; each data item occupies 4 bytes define 10 bytes

10

Data1 Data2

11 12

34
12 0A 04 10 XX XX XX XX XX XX XX XX

Example Data1 Data2 Data3

DB DW DB

10H,11H,12H 1234H 10,4,10H

Data3

XX

Assembler Directives

Example Data4 DB 0, ?, ?, 2EH Data5 DB ?, 20, ? String DW 2 DUP(1,2,?)

00

Data4 Data5

2E 14 -01 00 02 00

String

01 00 02 00

Assembler Directives
DUP for duplicate, reserves memory Data1 DB 5 DUP(?) ;DUP means duplicate

This reserves 5 bytes of memory for an array Data1 and initializes each location with ? i.e junk value, or unknown value.

Assembler Directives SEGMENT: statement to indicate the start of the program and its name. ENDS: Specifies the end of a segment

symbolic

. data ---. code ---end

Assembler Directives
Name SEGMENT Variable_name Variable_name ENDS SEGMENT Data1 Data2 ENDS

DB DW

. .

Name Data

DB DW

. .

Data

Code SEGMENT START: MOV AX,BX Code ENDS END START

Assembler Directives

ALIGN: Memory array is stored in word boundaries ASSUME :for assembler purpose, to know where the segment starts/ends ASSUME CS:CODE,DS:DATA END : END LABEL

Even - Directive

EVEN : Alignment directive Forces the next byte to even address. Words can be accessed in less time if they begin at even addresses. ! EXTERN, PUBLIC

PTR Directive

PTR : pointer Type PTR variable, constants Ex: NUM DB 08 MOV NUM,CX ; AN ERROR !

MOV WORD PTR NUM,CX

ARRAY DW 1234h MOV ARRAY,CL ; AN ERROR ! MOV BYTE PTR ARRAY,CL

LABEL Directive LABEL : variable LABEL Type

1)

ARRAY1 ARRAY2

LABEL BYTE DW 100 DUP(?)

MOV ARRAY1+2,0 ; Set 3rd BYTE TO 00 MOV ARRAY2+2,0 ; Set 3rd AND 4th TO 00 00 But both are in the same location ! 2) In case of JMP instructions next LABEL FAR -----jmp next

ORG The originate directive

Data SEGMENT ORG 1000H Num1 DB ORG 2000H Num2 DB Num3 EQU Data ENDS

10H 20H 30H

ASSUME CS:Code,DS:Data Code SEGMENT START: MOV AX,Data MOV DS,AX MOV AX,Num1 MOV CX,Num2 ADD AX,CX Code ENDS END START

PROC and ENDP directives.

Addition PROC NEAR ADD AX,BX MOV CX,AX RET ENDP

Addition

NEAR , FAR , SHORT are directives

EXTERN and PUBLIC directives

EXTERN : If a variable of other module is used, then it should be declared as EXTERN

PUBLIC : If a variable of a module used by other module, then it should be declared as PUBLIC in this module

THANK U