The steps required for performing an arithmetic or logical operation, for fetching a word from memory, or for storing

a word in memory Performed sequentially changing from one step to another A control unit required implements the steps

Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC). Instruction Register (IR)

Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase). IR [[PC]] Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase). PC [PC] + 4 Carry out the actions specified by the instruction in the IR (execution phase).

Internal processor bus Control signals PC Instruction Address lines MAR Memory bus MDR Data lines IR decoder and control logic

Y Constant 4 R0

Select

MUX Add

ALU control lines

Sub

A ALU

R n - 1

Carry -in XOR Z TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

MDR HAS TWO INPUTS AND TWO OUTPUTS

Datapath

Textbook Page 413

Transfer a word of data from one processor register to another or to the ALU. Perform an arithmetic or a logic operation and store the result in a processor register. Fetch the contents of a given memory location and load them into a processor register. Store a word of data from a processor register into a given memory location.

Internal processor bus Riin

Ri

Riout Yin

Y
Constant 4 Select MUX A ALU Zin Z B

Zout

Figure 7.2. Input and output gating for the registers in Figure 7.1.

The ALU is a combinational circuit that has no internal storage. ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z. What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3?
1. R1out, Yin 2. R2out, SelectY, Add, Zin 3. Zout, R3in

Memory -b us data lines

MDRoutE

MDRout

Internal processor bus

MDR

MDR inE

MDRin

Figure 7.4. Connection and control signals for re MDR. gister

Address into MAR; issue Read operation; data into MDR.

Figure 7.4. Connection and control signals for register MDR.

The response time of each memory access varies (cache miss, memory-mapped I/O,). To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (MemoryFunction-Completed, MFC). Move (R1), R2
MAR [R1] Start a Read operation on the memory bus Wait for the MFC response from the memory Load MDR from the memory bus R2 [MDR]

Add (R3), R1 Fetch the instruction Fetch the first operand (the contents of the memory location pointed to by R3) Perform the addition Load the result into R1

Internal processor bus Riin

Ri

Riout Yin

Y
Constant 4 Select MUX A ALU Zin Z B

Zout

Figure 7.2. Input and output gating for the registers in Figure 7.1.

Internal processor bus Control signals PC Instruction Address lines MAR decoder and control logic

Step 1 2 3 4 5 6 7

Action PCout , MAR in , Read, Select4, dd, Zin A Zout , PCin , Y in , WMF C MDR out , IR in R3out , MAR in , Read R1out , Y in , WMF C MDR out , SelectY,Add, Zin Zout , R1 in , End

Memory bus MDR Data lines IR

Y Constant 4 R0

Select

MUX Add

ALU control lines

Sub

A ALU

R n - 1

Carry -in XOR Z TEMP

Figure 7.6. Control sequence executionof the instruction Add (R3),R1. for

Figure 7.1. Single-bus organization of the datapath inside a processor.

Add (R3), R1

A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction. The offset X is usually the difference between the branch target address and the address immediately following the branch instruction. Conditional branch

Step Action
1 2 PCout , MAR in , Read, Select4,Add, Z in Zout , PCin , Yin , WMF C

3
4 5

MDR out , IR in
Offset-field-of-IR , Add, Z in out Z out , PCin , End

Figure 7.7. Control sequence for an unconditional branch instruction.

Bus A

Bus B
Incrementer

Bus C

PC

Re gister f ile

Constant 4

MUX

A ALU B R

Instruction decoder

IR

MDR

MAR

Memory b us data lines

Address lines

Figure 7.8. Three-b or anization of the datapath. us g

Add R4, R5, R6

Step Action 1 2 3 4 PCout, R=B, MAR in , Read, IncPC WMFC MDR outB , R=B, IR in R4outA , R5outB , SelectA, Add, R6in , End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6, for the three-bus organization in Figure 7.8.

To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence. Two categories: hardwired control and microprogrammed control .

Hardwired control design based on the following Control step counter Decoder/Encoder Circuits External Inputs and Condition code flags Hardwired system can operate at high speed; but with little flexibility

For n sequences of steps, assume that the states are changed in each step from one state to the next from S0 to Sn1 At each state, the set of outputs, Oi,0 to Oi, m 1, depend on the current states and inputs, I0 to Ix1

Hardwired Control Unit generating states by its circuit based Moore state machine or Mealy state machine See Fig (5.4)-Pg No=T1.309
T1 John p.Hayes

its circuit based Moore state machine. A set of outputs for the given set of inputs, assuming that the control unit is generating states by its circuit, which is based on Moore state machine concept Moore state machine concept is that each output signal Oi,0 to Oi, m1 depends on the current state only See Fig (5.4)-Pg No=T1.309

by

Hardwired Control Unit generating states

An encoder takes input from a sequence counter, instruction decoder, condition/status flags and external inputs External inputs can be from an external interrupting source and an external device requesting access to external buses Condition/status flags are as per conditions/ status flags set in earlier instructions

Clock

CLK

Control step counter

External inputs IR Decoder/ encoder Condition codes

Control signals

Figure 7.10. Control unit organization.

Clock

Control step counter

Step decoder T 1 T2 INS1 INS2 IR Instruction decoder INS m Run End Encoder Condition codes Tn

External inputs

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

Zin = T1 + T6 ADD + T4 BR +
Branch
T4 Add T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.

Branch<0 Add N T7 T5 N T4 T5 Branch

End

Figure 7.13. Generation of the End control signal.

End = T7 ADD + T5 BR + (T5 N + T4 N) BRN +

Instruction unit

Inte ger unit

Floating-point unit

Instruction cache

Data cache

Bus interf ace

Processor

Sy stem us b Main memory Input/ Output

Figure 7.14. Block diagram of a complete processor .

Control signals are generated by a program similar to machine language programs. Control Word (CW); microroutine; microinstruction

Control word It is a word whose individual bits represent the various control signals. Micro Instruction Individual Control word in each micro routine Micro routine sequence of control words Control Memory(store) Micro routines for all instructions in the instruction set of a computer are stored in a special memory

Step 1 2 3 4 5 6 7

Action PCout , MAR in , Read, Select4, dd, Zin A Zout , PCin , Y in , WMF C MDR out , IR in R3out , MAR in , Read R1out , Y in , WMF C MDR out , SelectY,Add, Zin Zout , R1 in , End

Figure 7.6. Control sequence executionof the instruction Add (R3),R1. for

MDRout

PCin

1 2 3 4 5 6 7

0 1 0 0 0 0 0

1 0 0 0 0 0 0

1 0 0 1 0 0 0

1 0 0 1 0 0 0

0 0 1 0 0 1 0

0 0 1 0 0 0 0

0 1 0 0 1 0 0

1 0 0 0 0 0 0

1 0 0 0 0 1 0

1 0 0 0 0 1 0

0 1 0 0 0 0 1

0 0 0 0 1 0 0

R1in

Add

Z out

IRin

0 0 0 0 0 0 1

0 0 0 1 0 0 0

0 1 0 0 1 0 0

Figure 7.15 An e xample of microinstructions for Figure 7.6.

Control sequence for Add (R3),R1

Microinstruction for ADD(R3),R1

End
0 0 0 0 0 0 1

Yin

Zin

Micro instruction

WMFC

MAR in

Select

Read

PCout

R1 out

R3 out

IR

Starting address generator

Clock

PC

Control store

CW

Figure 7.16. Basic organization of a microprogrammed control unit.

Control store
One function cannot be carried out by this simple organization.

Step 1: Every time a new instruction is loaded into the IR Step 2: starting address generator is loaded into the micro program counter. Step 3: To read control words sequentially from the control store. Step 4: control signals are delivered to various parts of the processor in the correct sequence.

Micro program counter: It is incremented by the clock Loading starting address of the micro routine when new instruction is loaded into the IR. Loading branch address when a brach mirco instruction is encountered and condn. Is satisfied.

The previous organization cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action. Use conditional branch microinstruction.
Address Microinstruction

0
1

PCout , MAR in , Read, Select4, Add, Z in

Zout , PCin , Y in , WMF C

MDRout , IR in

3 Branch to starting address appropriatemicroroutine of . ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... .. 25 26 27 If N=0, then branch to microinstruction0 Offset-field-of-IRout , SelectY, Add, Z in Zout , PCin , End

Figure 7.17. Microroutine for the instruction Branch<0.

External inputs IR Starting and branch address generator Condition codes

Clock

PC

Control store

CW

Figure 7.18.

Organization of the control unit to allow

conditional branching in the microprogram.

A straightforward way to structure microinstructions is to assign one bit position to each control signal. However, this is very inefficient. The length can be reduced: most signals are not needed simultaneously, and many signals are mutually exclusive. All mutually exclusive signals are placed in the same group in binary coding.

Microinstruction F1 F2 F3 F4 F5

F1 (4 bits) 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1010: 1011:

F2 (3 bits)

F3 (3 bits)

F4 (4 bits) 0000: Add 0001: Sub

F5 (2 bits) 00: No action 01: Read 10: Write

No transf er 000: PC 001: out MDR 010: out Z 011: out R0 100: out R1 101: out R2 110: out R3 111: out TEMP out Of f set out

No transf er000: No transf er PC 001: MARin in IR 010: MDR in in Z 011: TEMP in in R0 100: Y in in R1 in R2 in R3 in

1111: XOR 16 ALU f unctions

F6

F7

F8

F6 (1 bit) 0: SelectY 1: Select4

F7 (1 bit) 0: No action 1: WMFC

F8 (1 bit) 0: Continue 1: End

Figure 7.19. An example of a partial format for field-encoded microinstructions.

What is the price paid for this scheme?

Enumerate the patterns of required signals in all possible microinstructions. Each meaningful combination of active control signals can then be assigned a distinct code. Vertical organization compact codes to specify only a small no. of control functions in each microinstruction Horizontal organization- Many resources can be controlled with a single microinstruction.

Branch micro instructions perform no useful operation in the datapath. They are needed to determine the address of the next microinstruction. Each instruction contains the address of the next instruction

Micro address register :loads next address field in each instruction IR having next instruction address field. So no need for micro program counter.

IR

External Inputs

Condition codes

Decoding circuits

A R

Control store

Next address

I R

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.