By:

Dipendra Kumar Deo (062BEX409) Krishna Prasad Phelu (062BEX416) Nikendra Tandukar (062BEX419) Omi Sunuwar (062BEX422 )
Date: 18 March, 2010.

 Noise is inherent property of all practical channels.

This noise corrupts our data as it passes through the

communication channel. Channel coding is used to increase the reliability of communication system by combating noise. Convolutional code is the most commonly used channel coding technique. Viterbi decoding algorithm is used to decode convolutional codes.

 To simulate convolutional encoding and Viterbi

Decoding using MATLAB tools. To implement the Viterbi Decoder on FPGA. To evaluate the performance improvement of the system with channel coding in terms of BER for randomly generated digital data.

 VHDL MATLAB 7.0 C programming language Spartan-3E FPGA (XC3S500E) ModelSim SE 6.4 Xilinx ISE Project Navigator AT89S52 Microcontroller

Keil Vision 3
Proteus VSM 7
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 Pseudo-random number

Generated using LFSR

Fig: Random number generation.

 Rate, R=1/2
Constraint Length, K=3 Generator Polynomial:

g1=[111] g2=[101]

Fig: (2,1) Convolutional encoder.

Present state, s1s0 = 00

input = 1 output = 11 next state = 01

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Fig: State diagram of (2,1) encoder of R=1/2,K=3.

Fig: Trellis diagram of (2,1) encoder of R=1/2,K=3.

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 It is a maximum-likelihood decoding algorithm

Fixed decoding time

Highly parallelizable

Disadvantage: Decoding complexity grows exponentially as a function of constraint length

Received

00

11

01

3
4

10

 For Binary Symmetric Channel it searches the path in

the trellis which has minimum HD with the received bit sequences.

Fig: Viterbi decoding

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Previous PM

Updated PM

PMM

input

BMU
BM

ACS
BD

SMU
output

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 BMU and ACS unit

merged into a single unit. Four identical units for each state

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Simulation result for ACS unit for state a

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 Metric Normalization Variable Shift Method

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 Survivor Memory Management Register Exchange

Copy Decoded bit output

Shifted in 0
Survivor Path Competing Path

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Channel BER = 0.1 System BER = 0

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Fig: Effect of the channel coding.

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 Avoid catastrophic encoders

Fig: Effect of the Catastrophic Encoder.

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Fig: Effect of increasing constraint.

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Fig: Effect of increasing free distance.

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S.N. 1. 2. 3. 4. 5. 6. 7. 8. 9.

Components Microcontroller (AT89s52) Crystal D Flip-flop XOR gate Buffer (74LS244) MAX 232 FPGA (Spartan 3E) Serial Connector Serial Cable

Nos. 1 1 2 2 1 1 1 1 1

Cost per unit (RS) 175 30 30 25 60 120 12,500 50 500

Cost (RS) 175 30 60 50 60 120 12,500 50 500

10.
11. 12. 13.

Resistors
Capacitors Connecting Wires Miscellaneous Total

20
20 50 1000 14,635

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 Performance of the convolution code is not compared

with performance of other channel coding techniques. System is implemented for randomly generated digital data Convolutional code of rate and constraint length 3 is used Wired channel is used for hardware implementation Trace back method could be used for survivor memory management Mechanism for introducing error is not provided in hardware
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 System is simulated in MATLAB

Viterbi Decoder is implemented in FPGA.

Register exchange is used for survivor memory

management For same SNR BER of the system decreased for using channel coding.

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1. 2. 3. 4. 5.

S. Haykin, "Digital Communication", Wiley, 1988. B. P. Lathi, "Modern Digital and Analog Communication Systems", third edition, Oxford university press, 1998 Fu-hau Huang, "Evaluation of Soft Output Decoding for Turbo Codes, Chapter-2 (Convolutional Codes), Master's Thesis, 29 May, 1997. MATLAB documentation. Ranjan Bose, "An efficient method to calculate the free distance of convolutional codes", Paper, Department of Electrical Engineering, Indian Institute of Technology, Hauz Khas, New Delhi. J. Das, S. K. Mullick and P. K. Chatterjee, "Principles of Digital Communication", Willey, 1986. Feng Lo, "FPGA Realization of the Viterbi Decoder for HDSL2 Systems", Paper, Department of Electrical Engineering, National Central University, Taiwan. D. K. Sharma, "Communication Systems-II", Course Manual, Institute of Engineering, Tribhuvan University, 1999. R. Shakya, S. Maharjan, S. Tuladhar, S.R. Shrestha, CDMA Based Personal Communication System, Department of Electronics and Computer Engineering, Pulchowk Campus, IOE, March 2009.

6. 7. 8. 9.

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1. 2. 3. 4. 5. 6. 7. 8. 9.

Charles H. Roth, Jr, Digital Systems Design Using VHDL, PWS Publishing Company, 1998.

C. Maxfield, The Design Warriors Guide to FPGAs, Newnes Publication, 2004.

FPGA-Based Control: Millions of Transistors at Your Command, National Instruments Developer zone. XILINX, Spartan-3E Starter Kit Board User Guide, UG230 (v1.0), March 2006 Wikipedia, Linear Feedback Shift Register, http://en.wikipedia.org/wiki/linear feedback shift register. L. Van de Meeberg, "A Viterbi Decoder", Report, Eindhoven University of Technology The Nederlands, Department of Electrical Engineering, October 1974. Hema S., Suresh Babu V., Ramesh P.,FPGA Implementation of Viterbi Decoder, Paper, Kerala University, College of Engineering Trivandrum, Dept of ECE, India, February 2007. Chaiwat Keawsai, Keattisak Sripimanwat , and Attasit Lasaku, Modified Register Exchange Method of Viterbi Decoder for 3GPP Mobile System , Paper, King Mongkut's Institute of Technology, Department of Information Engineering, Thiland.

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